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GET /api/patches/803866/?format=api
{ "id": 803866, "url": "http://patchwork.ozlabs.org/api/patches/803866/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170821072101.29375-8-lokeshvutla@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170821072101.29375-8-lokeshvutla@ti.com>", "list_archive_url": null, "date": "2017-08-21T07:20:55", "name": "[U-Boot,v2,07/13] board: ti: dra76-evm: Add DDR data", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "908dbb71ffca949734e9f94783ff793f909f0ee0", "submitter": { "id": 14145, "url": "http://patchwork.ozlabs.org/api/people/14145/?format=api", "name": "Lokesh Vutla", "email": "lokeshvutla@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170821072101.29375-8-lokeshvutla@ti.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/803866/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/803866/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"jmHc4sS1\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xbQQB3Cqzz9s8V\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 21 Aug 2017 17:32:50 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid E1C66C21DC0; Mon, 21 Aug 2017 07:32:12 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id B2454C220D5;\n\tMon, 21 Aug 2017 07:25:51 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 9C624C220A4; Mon, 21 Aug 2017 07:25:25 +0000 (UTC)", "from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17])\n\tby lists.denx.de (Postfix) with ESMTPS id 7EF52C21E1D\n\tfor <u-boot@lists.denx.de>; Mon, 21 Aug 2017 07:25:21 +0000 (UTC)", "from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7L7PK3O031312; \n\tMon, 21 Aug 2017 02:25:20 -0500", "from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7L7PKN7003991; \n\tMon, 21 Aug 2017 02:25:20 -0500", "from DLEE104.ent.ti.com (157.170.170.34) by DLEE103.ent.ti.com\n\t(157.170.170.33) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tMon, 21 Aug 2017 02:25:19 -0500", "from dflp32.itg.ti.com (10.64.6.15) by DLEE104.ent.ti.com\n\t(157.170.170.34) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Mon, 21 Aug 2017 02:25:19 -0500", "from a0131933.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7L7P3Zh010673;\n\tMon, 21 Aug 2017 02:25:18 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1503300320;\n\tbh=MMseHi0TQnJgn0DQ+bJLT0osjfQO0YzJ4EcE9Y1ovIc=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=jmHc4sS1qcaIW3VTwVLBg5pWpeG8s4TqY4ZoouFo35BSMIIz2nvr+5qH29Lq5DTWY\n\thSSvA4J8y1IcXILzWHYYBRx7+RnDw+nYZmd9SbQcF05jOXcfaJ3bciLGTXjA6HbiDe\n\tphyPFPWj0dvASKOEzxVwgqc4nC7UMu/zq1i9UY3Y=", "From": "Lokesh Vutla <lokeshvutla@ti.com>", "To": "Tom Rini <trini@konsulko.com>, <u-boot@lists.denx.de>", "Date": "Mon, 21 Aug 2017 12:50:55 +0530", "Message-ID": "<20170821072101.29375-8-lokeshvutla@ti.com>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170821072101.29375-1-lokeshvutla@ti.com>", "References": "<20170821072101.29375-1-lokeshvutla@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "Tero Kristo <t-kristo@ti.com>", "Subject": "[U-Boot] [PATCH v2 07/13] board: ti: dra76-evm: Add DDR data", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "dra76-evm has the ddr parts connectedi running at 666MHz:\nEMIF1: MT41K512M16HA-125 AIT:A x 2\nEMIF2: MT41K512M8RH-125-AAT:E x 4\nAdd support for configuring the above DDR parts.\n\nReviewed-by: Tom Rini <trini@konsulko.com>\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\n---\n arch/arm/mach-omap2/omap5/hw_data.c | 1 +\n arch/arm/mach-omap2/omap5/sdram.c | 2 ++\n board/ti/dra7xx/evm.c | 61 +++++++++++++++++++++++++++++++++++--\n 3 files changed, 62 insertions(+), 2 deletions(-)", "diff": "diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c\nindex 7aaf379357..147eafa71e 100644\n--- a/arch/arm/mach-omap2/omap5/hw_data.c\n+++ b/arch/arm/mach-omap2/omap5/hw_data.c\n@@ -790,6 +790,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)\n \tcase DRA752_ES1_0:\n \tcase DRA752_ES1_1:\n \tcase DRA752_ES2_0:\n+\tcase DRA762_ES1_0:\n \t\t*regs = &ioregs_dra7xx_es1;\n \t\tbreak;\n \tcase DRA722_ES1_0:\ndiff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c\nindex 7712923d85..67ff63b9f6 100644\n--- a/arch/arm/mach-omap2/omap5/sdram.c\n+++ b/arch/arm/mach-omap2/omap5/sdram.c\n@@ -480,6 +480,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,\n \t\t*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;\n \t\t*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);\n \t\tbreak;\n+\tcase DRA762_ES1_0:\n \tcase DRA722_ES2_0:\n \t\t*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;\n \t\t*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);\n@@ -709,6 +710,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)\n \t\t*iterations = sizeof(omap5_bug_00339_regs)/\n \t\t\t sizeof(omap5_bug_00339_regs[0]);\n \t\tbreak;\n+\tcase DRA762_ES1_0:\n \tcase DRA752_ES1_0:\n \tcase DRA752_ES1_1:\n \tcase DRA752_ES2_0:\ndiff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c\nindex 8e79350111..53226f3167 100644\n--- a/board/ti/dra7xx/evm.c\n+++ b/board/ti/dra7xx/evm.c\n@@ -210,6 +210,56 @@ const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {\n \t.emif_rd_wr_exec_thresh = 0x00000305\n };\n \n+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {\n+\t.sdram_config_init = 0x61862B32,\n+\t.sdram_config = 0x61862B32,\n+\t.sdram_config2\t\t\t= 0x00000000,\n+\t.ref_ctrl = 0x0000514C,\n+\t.ref_ctrl_final\t\t\t= 0x0000144A,\n+\t.sdram_tim1 = 0xD113783C,\n+\t.sdram_tim2 = 0x30B47FE3,\n+\t.sdram_tim3 = 0x409F8AD8,\n+\t.read_idle_ctrl = 0x00050000,\n+\t.zq_config = 0x5007190B,\n+\t.temp_alert_config = 0x00000000,\n+\t.emif_ddr_phy_ctlr_1_init = 0x0824400D,\n+\t.emif_ddr_phy_ctlr_1 = 0x0E24400D,\n+\t.emif_ddr_ext_phy_ctrl_1 = 0x04040100,\n+\t.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,\n+\t.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,\n+\t.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,\n+\t.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,\n+\t.emif_rd_wr_lvl_rmp_win = 0x00000000,\n+\t.emif_rd_wr_lvl_rmp_ctl = 0x80000000,\n+\t.emif_rd_wr_lvl_ctl = 0x00000000,\n+\t.emif_rd_wr_exec_thresh = 0x00000305\n+};\n+\n+const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {\n+\t.sdram_config_init = 0x61862B32,\n+\t.sdram_config = 0x61862B32,\n+\t.sdram_config2\t\t\t= 0x00000000,\n+\t.ref_ctrl = 0x0000514C,\n+\t.ref_ctrl_final\t\t\t= 0x0000144A,\n+\t.sdram_tim1 = 0xD113781C,\n+\t.sdram_tim2 = 0x30B47FE3,\n+\t.sdram_tim3 = 0x409F8AD8,\n+\t.read_idle_ctrl = 0x00050000,\n+\t.zq_config = 0x5007190B,\n+\t.temp_alert_config = 0x00000000,\n+\t.emif_ddr_phy_ctlr_1_init = 0x0824400D,\n+\t.emif_ddr_phy_ctlr_1 = 0x0E24400D,\n+\t.emif_ddr_ext_phy_ctrl_1 = 0x04040100,\n+\t.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,\n+\t.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,\n+\t.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,\n+\t.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,\n+\t.emif_rd_wr_lvl_rmp_win = 0x00000000,\n+\t.emif_rd_wr_lvl_rmp_ctl = 0x80000000,\n+\t.emif_rd_wr_lvl_ctl = 0x00000000,\n+\t.emif_rd_wr_exec_thresh = 0x00000305\n+};\n+\n void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)\n {\n \tu64 ram_size;\n@@ -235,6 +285,12 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)\n \t\t\tbreak;\n \t\t}\n \t\tbreak;\n+\tcase DRA762_ES1_0:\n+\t\tif (emif_nr == 1)\n+\t\t\t*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;\n+\t\telse\n+\t\t\t*regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;\n+\t\tbreak;\n \tcase DRA722_ES1_0:\n \tcase DRA722_ES2_0:\n \t\tif (ram_size < CONFIG_MAX_MEM_MAPPED)\n@@ -290,6 +346,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)\n \tram_size = board_ti_get_emif_size();\n \n \tswitch (omap_revision()) {\n+\tcase DRA762_ES1_0:\n \tcase DRA752_ES1_0:\n \tcase DRA752_ES1_1:\n \tcase DRA752_ES2_0:\n@@ -1009,8 +1066,8 @@ static inline void vtt_regulator_enable(void)\n \tif (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)\n \t\treturn;\n \n-\t/* Do not enable VTT for DRA722 */\n-\tif (is_dra72x())\n+\t/* Do not enable VTT for DRA722 or DRA76x */\n+\tif (is_dra72x() || is_dra76x())\n \t\treturn;\n \n \t/*\n", "prefixes": [ "U-Boot", "v2", "07/13" ] }