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GET /api/patches/803862/?format=api
{ "id": 803862, "url": "http://patchwork.ozlabs.org/api/patches/803862/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170821072101.29375-5-lokeshvutla@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170821072101.29375-5-lokeshvutla@ti.com>", "list_archive_url": null, "date": "2017-08-21T07:20:52", "name": "[U-Boot,v2,04/13] arm: dra76: Add support for ES1.0 detection", "commit_ref": "0f9e6aee9dbcb7fd26f3782c267dffd1de0803ba", "pull_url": null, "state": "accepted", "archived": false, "hash": "73fa2b63f24700cc67f04f4a9b73cc3b4e3c780e", "submitter": { "id": 14145, "url": "http://patchwork.ozlabs.org/api/people/14145/?format=api", "name": "Lokesh Vutla", "email": "lokeshvutla@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170821072101.29375-5-lokeshvutla@ti.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/803862/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/803862/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"upgYyFHP\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xbQM50bdLz9s4s\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 21 Aug 2017 17:30:09 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid C4B3DC220A7; Mon, 21 Aug 2017 07:30:06 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4BA71C2202C;\n\tMon, 21 Aug 2017 07:25:34 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8CFC9C21E28; Mon, 21 Aug 2017 07:25:20 +0000 (UTC)", "from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17])\n\tby lists.denx.de (Postfix) with ESMTPS id 17EFCC22012\n\tfor <u-boot@lists.denx.de>; Mon, 21 Aug 2017 07:25:15 +0000 (UTC)", "from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7L7PDL3031300; \n\tMon, 21 Aug 2017 02:25:13 -0500", "from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7L7PD2V003905; \n\tMon, 21 Aug 2017 02:25:13 -0500", "from DFLE104.ent.ti.com (10.64.6.25) by DFLE100.ent.ti.com\n\t(10.64.6.21) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tMon, 21 Aug 2017 02:25:13 -0500", "from dflp32.itg.ti.com (10.64.6.15) by DFLE104.ent.ti.com\n\t(10.64.6.25) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Mon, 21 Aug 2017 02:25:13 -0500", "from a0131933.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7L7P3Ze010673;\n\tMon, 21 Aug 2017 02:25:11 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1503300313;\n\tbh=mghHnaBmHU3rM5/9M+EccOF+tf3PrykVFrrFO4goMKs=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=upgYyFHP1iKJMbZbAXvhALv12cYHfX9X/cEf9VUvJgVS6yj6hV1QmJ8PbDm+oTP2w\n\tE17H6BQ1RA67EuB0vZI4uMxE0uXtGLi+mlYFA/+sId66E/VvVVvl5ibO2ODhWQRERv\n\tcAXy3gmtI9bCNaqxvRql1ZOWyvc5Js8A0csrXF/g=", "From": "Lokesh Vutla <lokeshvutla@ti.com>", "To": "Tom Rini <trini@konsulko.com>, <u-boot@lists.denx.de>", "Date": "Mon, 21 Aug 2017 12:50:52 +0530", "Message-ID": "<20170821072101.29375-5-lokeshvutla@ti.com>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170821072101.29375-1-lokeshvutla@ti.com>", "References": "<20170821072101.29375-1-lokeshvutla@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "Tero Kristo <t-kristo@ti.com>, Praneeth Bajjuri <praneeth@ti.com>", "Subject": "[U-Boot] [PATCH v2 04/13] arm: dra76: Add support for ES1.0\n\tdetection", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Praneeth Bajjuri <praneeth@ti.com>\n\ndra76 family is a high-performance, infotainment application\ndevice, based on OMAP architecture on a 28-nm technology.\nThis contains most of the subsystems, peripherals that are\navailable on dra74, dra72 family. This SoC mainly features\nSubsystems:\n- 2 x Cortex-A15 with max speed of 1.8GHz\n- 2 X DSP\n- 2 X Cortex-M4 IPU\n- ISS\n- CAL\n- DSS\n- VPE\n- VIP\nConnectivity peripherals:\n- 1 USB3.0 and 3 USB2.0 subsystems\n- 1 x SATA\n- 2 x PCI Express Gen2\n- 3-port Gigabit ethernet switch\n- 2 x CAN\n- MCAN\n\nAdding CPU detection support for the dra76 ES1.0 soc\nand update prcm, control module, dplls data.\n\nReviewed-by: Tom Rini <trini@konsulko.com>\nSigned-off-by: Praneeth Bajjuri <praneeth@ti.com>\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\n---\n arch/arm/include/asm/arch-omap5/omap.h | 1 +\n arch/arm/include/asm/omap_common.h | 8 ++++++++\n arch/arm/mach-omap2/omap5/hw_data.c | 27 +++++++++++++++++++++++++++\n arch/arm/mach-omap2/omap5/hwinit.c | 3 +++\n 4 files changed, 39 insertions(+)", "diff": "diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h\nindex b047f0d650..87a3d23ecb 100644\n--- a/arch/arm/include/asm/arch-omap5/omap.h\n+++ b/arch/arm/include/asm/arch-omap5/omap.h\n@@ -58,6 +58,7 @@\n #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F\n #define OMAP5432_CONTROL_ID_CODE_ES1_0\t\t0x0B99802F\n #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F\n+#define DRA762_CONTROL_ID_CODE_ES1_0\t\t0x0BB5002F\n #define DRA752_CONTROL_ID_CODE_ES1_0\t\t0x0B99002F\n #define DRA752_CONTROL_ID_CODE_ES1_1\t\t0x1B99002F\n #define DRA752_CONTROL_ID_CODE_ES2_0\t\t0x2B99002F\ndiff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h\nindex ef5c481349..e951b232d6 100644\n--- a/arch/arm/include/asm/omap_common.h\n+++ b/arch/arm/include/asm/omap_common.h\n@@ -722,6 +722,7 @@ static inline u8 is_omap54xx(void)\n \n #define DRA7XX\t\t0x07000000\n #define DRA72X\t\t0x07200000\n+#define DRA76X\t\t0x07600000\n \n static inline u8 is_dra7xx(void)\n {\n@@ -734,6 +735,12 @@ static inline u8 is_dra72x(void)\n \textern u32 *const omap_si_rev;\n \treturn (*omap_si_rev & 0xFFF00000) == DRA72X;\n }\n+\n+static inline u8 is_dra76x(void)\n+{\n+\textern u32 *const omap_si_rev;\n+\treturn (*omap_si_rev & 0xFFF00000) == DRA76X;\n+}\n #endif\n \n /*\n@@ -761,6 +768,7 @@ static inline u8 is_dra72x(void)\n #define OMAP5432_ES2_0 0x54320200\n \n /* DRA7XX */\n+#define DRA762_ES1_0\t0x07620100\n #define DRA752_ES1_0\t0x07520100\n #define DRA752_ES1_1\t0x07520110\n #define DRA752_ES2_0\t0x07520200\ndiff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c\nindex 4ad6b530d2..19a8d10cef 100644\n--- a/arch/arm/mach-omap2/omap5/hw_data.c\n+++ b/arch/arm/mach-omap2/omap5/hw_data.c\n@@ -113,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {\n \t{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},\t\t/* 38.4 MHz */\n };\n \n+static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {\n+\t{32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},\t\t/* 12 MHz */\n+\t{96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},\t\t/* 20 MHz */\n+\t{160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},\t\t/* 16.8 MHz */\n+\t{20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},\t\t/* 19.2 MHz */\n+\t{192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},\t\t/* 26 MHz */\n+\t{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},\t/* 27 MHz */\n+\t{10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},\t\t/* 38.4 MHz */\n+};\n+\n static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {\n \t{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},\t/* 12 MHz */\n \t{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},\t/* 13 MHz */\n@@ -234,6 +244,17 @@ struct dplls omap5_dplls_es2 = {\n \t.ddr = NULL\n };\n \n+struct dplls dra76x_dplls = {\n+\t.mpu = mpu_dpll_params_1ghz,\n+\t.core = core_dpll_params_2128mhz_dra7xx,\n+\t.per = per_dpll_params_768mhz_dra76x,\n+\t.abe = abe_dpll_params_sysclk2_361267khz,\n+\t.iva = iva_dpll_params_2330mhz_dra7xx,\n+\t.usb = usb_dpll_params_1920mhz,\n+\t.ddr =\tddr_dpll_params_2664mhz,\n+\t.gmac = gmac_dpll_params_2000mhz,\n+};\n+\n struct dplls dra7xx_dplls = {\n \t.mpu = mpu_dpll_params_1ghz,\n \t.core = core_dpll_params_2128mhz_dra7xx,\n@@ -709,6 +730,12 @@ void __weak hw_data_init(void)\n \t*ctrl = &omap5_ctrl;\n \tbreak;\n \n+\tcase DRA762_ES1_0:\n+\t*prcm = &dra7xx_prcm;\n+\t*dplls_data = &dra76x_dplls;\n+\t*ctrl = &dra7xx_ctrl;\n+\tbreak;\n+\n \tcase DRA752_ES1_0:\n \tcase DRA752_ES1_1:\n \tcase DRA752_ES2_0:\ndiff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c\nindex 85d3518e94..c520a633c4 100644\n--- a/arch/arm/mach-omap2/omap5/hwinit.c\n+++ b/arch/arm/mach-omap2/omap5/hwinit.c\n@@ -362,6 +362,9 @@ void init_omap_revision(void)\n \tcase OMAP5432_CONTROL_ID_CODE_ES2_0:\n \t\t*omap_si_rev = OMAP5432_ES2_0;\n \t\tbreak;\n+\tcase DRA762_CONTROL_ID_CODE_ES1_0:\n+\t\t*omap_si_rev = DRA762_ES1_0;\n+\t\tbreak;\n \tcase DRA752_CONTROL_ID_CODE_ES1_0:\n \t\t*omap_si_rev = DRA752_ES1_0;\n \t\tbreak;\n", "prefixes": [ "U-Boot", "v2", "04/13" ] }