Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 803045,
    "url": "http://patchwork.ozlabs.org/api/patches/803045/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1503035091-28883-3-git-send-email-Ashish.Kumar@nxp.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1503035091-28883-3-git-send-email-Ashish.Kumar@nxp.com>",
    "list_archive_url": null,
    "date": "2017-08-18T05:44:51",
    "name": "[U-Boot,v4,3/3] armv8: ls1088aqds: Add support of LS1088AQDS",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "73a06acf4544c5cc02a80211bb16f08c95a9dd7e",
    "submitter": {
        "id": 68053,
        "url": "http://patchwork.ozlabs.org/api/people/68053/?format=api",
        "name": "Ashish Kumar",
        "email": "Ashish.kumar@nxp.com"
    },
    "delegate": {
        "id": 2666,
        "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api",
        "username": "yorksun",
        "first_name": "York",
        "last_name": "Sun",
        "email": "yorksun@freescale.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1503035091-28883-3-git-send-email-Ashish.Kumar@nxp.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/803045/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/803045/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)",
            "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;"
        ],
        "Received": [
            "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xYXK358R6z9t2x\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 18 Aug 2017 15:51:51 +1000 (AEST)",
            "by lists.denx.de (Postfix, from userid 105)\n\tid 72FF5C21EE0; Fri, 18 Aug 2017 05:51:50 +0000 (UTC)",
            "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 70B85C21E9F;\n\tFri, 18 Aug 2017 05:45:14 +0000 (UTC)",
            "by lists.denx.de (Postfix, from userid 105)\n\tid 5465FC21DB8; Fri, 18 Aug 2017 05:45:11 +0000 (UTC)",
            "from NAM01-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam01on0059.outbound.protection.outlook.com [104.47.32.59])\n\tby lists.denx.de (Postfix) with ESMTPS id 6AF73C21E47\n\tfor <u-boot@lists.denx.de>; Fri, 18 Aug 2017 05:44:58 +0000 (UTC)",
            "from MWHPR03CA0043.namprd03.prod.outlook.com (10.174.173.160) by\n\tCY1PR03MB2267.namprd03.prod.outlook.com (10.166.207.19) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n\t15.1.1341.21; Fri, 18 Aug 2017 05:44:55 +0000",
            "from BL2FFO11FD042.protection.gbl (2a01:111:f400:7c09::134) by\n\tMWHPR03CA0043.outlook.office365.com (2603:10b6:301:3b::32) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1362.18\n\tvia Frontend Transport; Fri, 18 Aug 2017 05:44:55 +0000",
            "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBL2FFO11FD042.mail.protection.outlook.com (10.173.161.138) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.1.1341.15 via Frontend Transport; Fri, 18 Aug 2017 05:44:55 +0000",
            "from ubuntu1604.ap.freescale.net (ubuntu1604.ap.freescale.net\n\t[10.232.133.7])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv7I5ijOe005054; Thu, 17 Aug 2017 22:44:52 -0700"
        ],
        "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de",
        "X-Spam-Level": "",
        "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tSPF_HELO_PASS\n\tautolearn=unavailable autolearn_force=no version=3.4.0",
        "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;",
        "From": "Ashish Kumar <Ashish.Kumar@nxp.com>",
        "To": "<u-boot@lists.denx.de>",
        "Date": "Fri, 18 Aug 2017 11:14:51 +0530",
        "Message-ID": "<1503035091-28883-3-git-send-email-Ashish.Kumar@nxp.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1503035091-28883-1-git-send-email-Ashish.Kumar@nxp.com>",
        "References": "<1503035091-28883-1-git-send-email-Ashish.Kumar@nxp.com>",
        "X-EOPAttributedMessage": "0",
        "X-Matching-Connectors": "131475086952852880;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()",
        "X-Forefront-Antispam-Report": "CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(336005)(39380400002)(39860400002)(2980300002)(1110001)(1109001)(339900001)(199003)(189002)(305945005)(86362001)(8656003)(5660300001)(54906002)(53936002)(68736007)(76176999)(2950100002)(6916009)(53946003)(105606002)(498600001)(110136004)(2351001)(189998001)(50986999)(356003)(50226002)(8936002)(81156014)(104016004)(77096006)(81166006)(106466001)(2906002)(5003940100001)(48376002)(4326008)(36756003)(50466002)(72206003)(97736004)(85426001)(8676002)(626005)(575784001)(47776003)(579004);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR03MB2267;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; ",
        "X-Microsoft-Exchange-Diagnostics": [
            "1; BL2FFO11FD042;\n\t1:rOZ1KD6eV0HTx7iUk4P0FCThOkusYhOxjLKAkoI5iZXjUM/Qw2ILL3JX7pj2VIKQaAAsJNnERjHSNXXZjHovPQU02eSVib7NzoGGS4arodULAKutUmY9qNOxFOSMmWp0",
            "1; CY1PR03MB2267;\n\t3:zWDh0YGak8d6DUtYfnwUsq6JhqziuONXs+y9ofgtmST2rrXOH/yGg0f9TlZk0OFghUA7xzpfOuFVfwznISPhfENmVyQd5lQAj6etoD02ZVKDoao9LuBxt2LdMHX9LDPZlfMX9Zc6MqvVuMClsOCQWdWtp5IvKxRXRcqyLqjpNy171cboqXWyRGRIC3eA2yFkuBm+y3GzwXhbTz4ttxnIO+ICebKDYE+csw2qDwjNB8FioGZgZZVeZ9QHAh+jXWsq9ZnCvcd5uM8NbH9GYJFYdfnHPxyh1LsFVvc+j5ZZfUcZsh2N6noEdmi5HF0haef3FTEaS5KxiLC9Tx88UyaaFr095vVSbPcOFspUFUd2wQU=;\n\t25:CEMMsSt+7JvZkb4f+8iSxpQ0bpvzGnLE/4GOFFMvka9HjXk8VDl6c849JGEw+XnGXGjPQiOP22QZwy076qe1zu9XlsuKJHYwv+wecT9fGplwp+frSYZlIu6Xmb6cRMhLsQncgHwDfMFgakD7/7Nq7b5XTNknnHsWCwHIY0+jLNvBYwEH+ulaaj/sB6n17uewoU0kWNEdT6Zt8HnGBPU6ESB3Of3Xq95UxGc9blrp5G0LP2EePtKAdL38mLk7OAvyWByPtn1EgiI8++KLMVhE4qV59Y2TcARKtlniLcN14hSud5zqreEbDwNbGH/j9qJdh4Jrw4kT4et6+ULOWgwaVQ==",
            "1; CY1PR03MB2267;\n\t31:hrkFbGxoa5OEvVB7aI28TrIwwWos3gyODMlDbgi7KRo+mMys3EbN8eg0VML1GWEjeZqqz0q6qaHmLVTM2Zq840NHpS0erpEpF+3HwgBcHbFnP1yevSybio8e7zZ8Ut7HMkrr8DA6KeFGY8vNxitiQenvsDunAAlEAeCaAcUQgKcXdgCgYvRXo/ZlIF+V2I0eEeIs0nDPqs0MOUyo7zgODj9JswUbEJzWW9Ixh+bk1d8=;\n\t4:boToFgcUyoWLCwLPXm3v2AM6ktD6QlTquFOA+dzD3zqQPQladDSQOE6ZWl8t2IH45ioZgyukDz2n2Z8WgB5W38BF2Es3hSOGUOX7peL8H/tYQoKfNbmYoMZVItZ+qyAD1NA4gnXk1mNhKmUKylnU/huzJsgjZPcxhVPeFiKL/EbTYciaPEBzsymJXg5JgmE0muBMVL7qZLiuXyq2KwSf6aCPYK6mWz2LMDhmAa7A9pG/4p2RlyCZXnuPQdnYslvXplsTMMWREXRHxczpTrtDaYsg4m+0Ff/cvgxCSTsL+fA=",
            "=?us-ascii?Q?1; CY1PR03MB2267;\n\t23:XhSmixIDmiN6iGhjNLHJq1HqKLaL3CcwNAmEEnaIw?=\n\t=?us-ascii?Q?vrjEX8DRvhC6FJyRM5XgHng+pACKauJtaM/SXt4QKq+KDYtybLRHUW200GHO?=\n\t=?us-ascii?Q?Kv+0y+D3T0y/tWOWXszUbfZ2sviFrqMh+lt6tHjqz3mOf3LyqluGaeVUhhZK?=\n\t=?us-ascii?Q?4kSVdrhCo+VtOn1Q0WNNvRgg0f4GjuGfcdYvJiTpdW0sg5lfbUSTlHJ4ZqMX?=\n\t=?us-ascii?Q?y87r3VihC+/gcyuv1PIAvOx4P+RZz1r4TAAJQJ9JAUTk1CsI6mvUfm280dd0?=\n\t=?us-ascii?Q?2RXMlFLJNgNHF0taCES/gTBHs+p7AHK6s8toIAQuKWFphnmjAgYOmW/OWOuN?=\n\t=?us-ascii?Q?8Yx8y7iolEHEi4NevPm22ciVyHFp0bGXbucWc/D3KUo6BvNERESo96qbHvw6?=\n\t=?us-ascii?Q?USPUBtrUEyfRT170R5kZYI4DS34IvLhMEWaAPtSUpn/CowL3710UHR/F/dRt?=\n\t=?us-ascii?Q?vjhf4QbZdxdKFhfpgeZosRQxso3LMoWNzddDk+8d0wzhvTrNl7zhi9k+emE9?=\n\t=?us-ascii?Q?/9VjqaPvaUDMUOGnDbxdebSsdRm6X6GBeymNXYKiLXI5D6PX1cxoASgtD+Hf?=\n\t=?us-ascii?Q?MchC6SdOSj0LJ+gy6CidPN7ShQ+qaKEqsoC1GQbuLB/nxnQFxWwOl8+qHPeF?=\n\t=?us-ascii?Q?fupng5NJz8jGHFiD0qB8flNL5W9GAr+AvyFMCukIDrf3xsWAdE6BjAVRAVU9?=\n\t=?us-ascii?Q?1CeRX2DUdYE16d0JGNF00TFLguKJCoIAikOKBBa+9Jh/OLNBsFgBn9Wg8UnT?=\n\t=?us-ascii?Q?X5N0Z6xaByLIBmSK6lFLU2ZvkXnceNlAj3vqVoA7cqeRbZgs7ceHoGbBHD5/?=\n\t=?us-ascii?Q?qPOY01qA9cU7KCZQXZ7ZVz6JN5G84HdJwvGCcTi8nHUSJGfS9+npdnrta8qf?=\n\t=?us-ascii?Q?tHouoFayVXrY5PlJAxj63w6IW2yvMOsh//IJKtzWLgUtqevFrgSwUtE2Qawc?=\n\t=?us-ascii?Q?Cf04HgvS7q8PYERoqZa2OWA+kKaofinnKeN7uR17eQeHuZKphJxgZAn4V2Z9?=\n\t=?us-ascii?Q?2I0+ut2UyF2kMTs+eX3ddLfjgjuX4XRvXa1w19foHDQiPaKPYfGIEKKBq0bf?=\n\t=?us-ascii?Q?HBZ9SB5CrRqIiq1DMSGXIY4wbf10GKfEllNIEEZgNeHsCkari3WrP4LWZ92g?=\n\t=?us-ascii?Q?R+zaYJgdozsIKbyheho/mIxGwYRLRlRV4p7kTeTpio/aqbj3BwZziwMMvkKp?=\n\t=?us-ascii?Q?pXUFM9g+8V7LCI=3D?=",
            "1; CY1PR03MB2267;\n\t6:fVDEwhHvEKSbK17nKAiA+xmJEXV+ejKBvCJIQkZNAHrrh7Uo05GmbaPVk0JWTtnfmJldaDChxOT1jRWYzGlfqA2O9Ag2tFFvyFa+xKV5ntFLiwQsN/Hx8VqHEkqk4K9/ZzReWdamw8Lmyr0PpjbvNGwZtj9xlmwyZwLS5KtH52NQ1GtvhHnT3GiTYZ1sLqZAJvvCN0B9n7TMLrWqx01WC9/w2aVjtzVcSmXlESlNF6zsMD/0sMaP+M943onBIqcQ8ZzvM4Ap3BHReIPr1+K9HHMfvyWca8LWYDiuu/3jccL1/8mXYNcZ+4Oq9SFQeKNw60cQ4LLkrxgo41WqQLrGQg==;\n\t5:IIGfBcubQMEw8V4cIoJHe25glJVsegK2RByK6bBE7CzJx8f9TTiLLQQUTtC3pRqK4FPTkZ4IyRvvpmovR/G7kHjRjeoRcUNmXKmnfPKAyyUPkWYh0kJWR8rfWalUf4zgy7fiEO5EUVlwL3n+HHPmFg==;\n\t24:XdG2RiMd8HmqTXCwR/0GaHHkVsU98l/rsdmU/dOpeujk5hmjOZXF71K7v1aC23zZwiaphuJokVUR3y6KMoqiyiaOlLpEmBI8umnRl3CJ0rI=;\n\t7:ooU7wP+8FGGKqXP50SVy+KFHxWwYSfstPW3uTMHvYeizEXE8hVLDXFN5qj7Hl1Ce1iZvxjXMesVUHIe5UwHb/2RVuFX1XAuWltLE8GhBzFfs+pzETHDUquTm27u4AJklFJNHVR8o8zcOt7wQycXvslyfBdPKKtymWu/988KNR6Vc7S8OymXu0dzBEtG6KzGRn/NW0kypRHmWo271ugSprPuIu4A+WBD7LpNBbFkyghE="
        ],
        "MIME-Version": "1.0",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-Office365-Filtering-Correlation-Id": "e9e45f8f-c362-426e-0c2f-08d4e5fc4118",
        "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(2017052603031)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:CY1PR03MB2267; ",
        "X-MS-TrafficTypeDiagnostic": "CY1PR03MB2267:",
        "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197);",
        "X-Microsoft-Antispam-PRVS": "<CY1PR03MB22675E2AC42911F994D7CF5F95800@CY1PR03MB2267.namprd03.prod.outlook.com>",
        "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(601004)(2401047)(5005006)(13016025)(8121501046)(13018025)(3002001)(10201501046)(93006095)(93001095)(100000703101)(100105400095)(6055026)(6096035)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123563025)(20161123559100)(20161123561025)(20161123556025)(20161123565025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:CY1PR03MB2267; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY1PR03MB2267; ",
        "X-Forefront-PRVS": "040359335D",
        "SpamDiagnosticOutput": "1:99",
        "SpamDiagnosticMetadata": "NSPM",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Aug 2017 05:44:55.1136\n\t(UTC)",
        "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e",
        "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR03MB2267",
        "Cc": "Shaohui Xie <Shaohui.Xie@nxp.com>",
        "Subject": "[U-Boot] [PATCH v4 3/3] armv8: ls1088aqds: Add support of LS1088AQDS",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.18",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>",
        "List-Post": "<mailto:u-boot@lists.denx.de>",
        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "Content-Type": "text/plain; charset=\"utf-8\"",
        "Content-Transfer-Encoding": "base64",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>"
    },
    "content": "This patch add support of LS1088AQDS platform.\n\nThe LS1088A QorIQTM Development System (QDS) is a\nhigh-performance computing, evaluation, and\ndevelopment platform that supports the LS1088A QorIQ Architecture\nprocessor.\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>\nSigned-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>\nSigned-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>\n---\nv2:\nFix indentaion in commit msg\n\nv3:\nNot sent\n\nv4:\nReview comments on V2 fixed\nPPA enabled\nREADME added \n\n arch/arm/Kconfig                         |  13 +\n arch/arm/cpu/armv8/Kconfig               |   2 +-\n arch/arm/dts/Makefile                    |   3 +-\n arch/arm/dts/fsl-ls1088a-qds.dts         |  70 ++++\n board/freescale/ls1088a/Kconfig          |  16 +\n board/freescale/ls1088a/MAINTAINERS      |   8 +\n board/freescale/ls1088a/Makefile         |   1 +\n board/freescale/ls1088a/README           |  79 ++++\n board/freescale/ls1088a/ddr.h            |   5 +\n board/freescale/ls1088a/eth_ls1088aqds.c | 650 +++++++++++++++++++++++++++++++\n board/freescale/ls1088a/ls1088a.c        |  87 ++++-\n board/freescale/ls1088a/ls1088a_qixis.h  |   5 +\n configs/ls1088aqds_qspi_defconfig        |  29 ++\n include/configs/ls1088aqds.h             | 414 ++++++++++++++++++++\n 14 files changed, 1372 insertions(+), 10 deletions(-)\n create mode 100644 arch/arm/dts/fsl-ls1088a-qds.dts\n create mode 100644 board/freescale/ls1088a/eth_ls1088aqds.c\n create mode 100644 configs/ls1088aqds_qspi_defconfig\n create mode 100644 include/configs/ls1088aqds.h",
    "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex eaeab27..c96bbb4 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -791,6 +791,19 @@ config TARGET_LS2080A_SIMU\n \t  development platform that supports the QorIQ LS2080A\n \t  Layerscape Architecture processor.\n \n+config TARGET_LS1088AQDS\n+\tbool \"Support ls1088aqds\"\n+\tselect ARCH_LS1088A\n+\tselect ARM64\n+\tselect ARMV8_MULTIENTRY\n+\tselect ARCH_MISC_INIT\n+\tselect BOARD_LATE_INIT\n+\thelp\n+\t  Support for NXP LS1088AQDS platform\n+\t  The LS1088A Development System (QDS) is a high-performance\n+\t  development platform that supports the QorIQ LS1088A\n+\t  Layerscape Architecture processor.\n+\n config TARGET_LS2080AQDS\n \tbool \"Support ls2080aqds\"\n \tselect ARCH_LS2080A\ndiff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig\nindex aecdf81..12aba9d 100644\n--- a/arch/arm/cpu/armv8/Kconfig\n+++ b/arch/arm/cpu/armv8/Kconfig\n@@ -88,7 +88,7 @@ config PSCI_RESET\n \tdepends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \\\n \t\t   !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \\\n \t\t   !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \\\n-\t\t   !TARGET_LS1088ARDB && \\\n+\t\t   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \\\n \t\t   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \\\n \t\t   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \\\n \t\t   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \\\ndiff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 6f03a3f..06c6340 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -189,7 +189,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \\\n \tfsl-ls2080a-rdb.dtb \\\n \tfsl-ls2081a-rdb.dtb \\\n \tfsl-ls2088a-rdb-qspi.dtb \\\n-\tfsl-ls1088a-rdb.dtb\n+\tfsl-ls1088a-rdb.dtb \\\n+\tfsl-ls1088a-qds.dtb\n dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \\\n \tfsl-ls1043a-qds-lpuart.dtb \\\n \tfsl-ls1043a-rdb.dtb \\\ndiff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts\nnew file mode 100644\nindex 0000000..9b7bef4\n--- /dev/null\n+++ b/arch/arm/dts/fsl-ls1088a-qds.dts\n@@ -0,0 +1,70 @@\n+/*\n+ * NXP ls1088a QDS board device tree source\n+ *\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/dts-v1/;\n+\n+#include \"fsl-ls1088a.dtsi\"\n+\n+/ {\n+\tmodel = \"NXP Layerscape 1088a QDS Board\";\n+\tcompatible = \"fsl,ls1088a-qds\", \"fsl,ls1088a\";\n+\taliases {\n+\t\tspi0 = &qspi;\n+\t\tspi1 = &dspi;\n+\t};\n+};\n+\n+&dspi {\n+\tbus-num = <0>;\n+\tstatus = \"okay\";\n+\n+\tdflash0: n25q128a {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spi-flash\";\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <1000000>; /* input clock */\n+\t};\n+\n+\tdflash1: sst25wf040b {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spi-flash\";\n+\t\tspi-max-frequency = <3500000>;\n+\t\treg = <1>;\n+\t};\n+\n+\tdflash2: en25s64 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spi-flash\";\n+\t\tspi-max-frequency = <3500000>;\n+\t\treg = <2>;\n+\t};\n+};\n+\n+&qspi {\n+\tbus-num = <0>;\n+\tstatus = \"okay\";\n+\n+\tqflash0: s25fs512s@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spi-flash\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\treg = <0>;\n+\t};\n+\n+\tqflash1: s25fs512s@1 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spi-flash\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\treg = <1>;\n+\t };\n+};\ndiff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig\nindex a4d8223..1ada661 100644\n--- a/board/freescale/ls1088a/Kconfig\n+++ b/board/freescale/ls1088a/Kconfig\n@@ -1,3 +1,19 @@\n+if TARGET_LS1088AQDS\n+\n+config SYS_BOARD\n+\tdefault \"ls1088a\"\n+\n+config SYS_VENDOR\n+\tdefault \"freescale\"\n+\n+config SYS_SOC\n+\tdefault \"fsl-layerscape\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"ls1088aqds\"\n+\n+endif\n+\n if TARGET_LS1088ARDB\n \n config SYS_BOARD\ndiff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS\nindex 12834f6..e1e6d4b 100644\n--- a/board/freescale/ls1088a/MAINTAINERS\n+++ b/board/freescale/ls1088a/MAINTAINERS\n@@ -5,3 +5,11 @@ S:\tMaintained\n F:\tboard/freescale/ls1088a/\n F:\tinclude/configs/ls1088ardb.h\n F:\tconfigs/ls1088ardb_qspi_defconfig\n+\n+LS1088AQDS BOARD\n+M:\tPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>\n+M:\tAshish Kumar <Ashish.Kumar@nxp.com>\n+S:\tMaintained\n+F:\tboard/freescale/ls1088a/\n+F:\tinclude/configs/ls1088aqds.h\n+F:\tconfigs/ls1088aqds_qspi_defconfig\ndiff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile\nindex e997cf1..bdcce9e 100644\n--- a/board/freescale/ls1088a/Makefile\n+++ b/board/freescale/ls1088a/Makefile\n@@ -6,4 +6,5 @@\n \n obj-y += ls1088a.o\n obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o\n+obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o\n obj-y += ddr.o\ndiff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README\nindex 3f4d987..aa0fb6a 100644\n--- a/board/freescale/ls1088a/README\n+++ b/board/freescale/ls1088a/README\n@@ -64,3 +64,82 @@ Alternately you can use this command to switch from QSPI to SD\n  - JTAG support\n  - QSPI emulator support\n  - TDM riser support\n+\n+QDS Default Switch Settings (1: ON; 0: OFF)\n+-------------------------------------------\n+\n+For 16b IFC-NOR\n+SW1 0001 0010\n+SW2 x110 1111\n+\n+For QSPI Boot\n+SW1 0011 0001\n+SW2 0110 1111\n+\n+For SD Boot\n+SW1 0010 0000\n+SW2 0110 1111\n+\n+For eMMC Boot\n+SW1 0010 0000\n+SW2 1110 1111\n+\n+For I2C (ext. addr.)\n+SW1 0010 0100\n+SW2 1110 1111\n+\n+SW3 to SW12 are identical for all boot source\n+\n+SW3 0010 0100\n+SW4 0010 0000\n+SW5 1110 0111\n+SW6 1110 1000\n+SW7 0001 1101\n+SW8 0000 1101\n+SW9 1100 1010\n+SW10 1110 1000\n+SW11 1111 0100\n+SW12 1111 1111\n+\n+ LS1088AQDS board Overview\n+ -------------------------\n+ - SERDES Connections, 16 lanes supporting:\n+      - PCI Express - 3.0\n+      - SATA 3.0\n+      - 2 XFI\n+      - QSGMII, SGMII with help for Riser card\n+      - 2 RGMII\n+      - 5 slot for Riser card or PCIe NIC\n+ - DDR Controller\n+     - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four\n+       chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default\n+       with FSL refernce software is 2100MT/s\n+ - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB\n+ - IFC/Local Bus\n+    - One 2 GB NAND flash with ECC support, not as boot source\n+    - CPLD of size 2K\n+ - USB 3.0\n+    - Two high speed USB 3.0 ports\n+    - First USB 3.0 port configured as Host with Type-A connector\n+    - Second USB 3.0 port configured as OTG with micro-AB connector\n+ - SDHC/eMMC\n+    - SDHC/eMMC slot via adaptor\n+ - 4 I2C controllers\n+ - Two SATA onboard connectors\n+ - 2 UART\n+ - JTAG support\n+ - DSPI\n+ - PROMJET support\n+ - QSPI emulator support\n+ - TDM riser support\n+\n+QSPI flash memory map valid for both QDS and RDB\n+  Image                               Flash Offset\n+ RCW+PBI                             0x00000000\n+ Boot firmware (U-Boot)              0x00100000\n+ Boot firmware Environment           0x00300000\n+ PPA firmware                        0x00400000\n+ DPAA2 MC                            0x00A00000\n+ DPAA2 DPL                           0x00D00000\n+ DPAA2 DPC                           0x00E00000\n+ Kernel.itb                          0x01000000\ndiff --git a/board/freescale/ls1088a/ddr.h b/board/freescale/ls1088a/ddr.h\nindex dfcfc1f..a1ad709 100644\n--- a/board/freescale/ls1088a/ddr.h\n+++ b/board/freescale/ls1088a/ddr.h\n@@ -34,6 +34,11 @@ static const struct board_specific_parameters udimm0[] = {\n \t{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},\n \t{2,  2300, 0, 8,     9, 0x0A0C0E11, 0x1214160F,},\n \t{}\n+#elif defined(CONFIG_TARGET_LS1088AQDS)\n+\t{2,  1666, 0, 8,     8, 0x0A0A0C0E, 0x0F10110C,},\n+\t{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},\n+\t{2,  2300, 0, 4,     9, 0x0A0C0D11, 0x1214150E,},\n+\t{}\n \n #endif\n };\ndiff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c\nnew file mode 100644\nindex 0000000..3e78ac7\n--- /dev/null\n+++ b/board/freescale/ls1088a/eth_ls1088aqds.c\n@@ -0,0 +1,650 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <netdev.h>\n+#include <asm/io.h>\n+#include <asm/arch/fsl_serdes.h>\n+#include <hwconfig.h>\n+#include <fsl_mdio.h>\n+#include <malloc.h>\n+#include <fm_eth.h>\n+#include <i2c.h>\n+#include <miiphy.h>\n+#include <fsl-mc/ldpaa_wriop.h>\n+\n+#include \"../common/qixis.h\"\n+\n+#include \"ls1088a_qixis.h\"\n+\n+#define MC_BOOT_ENV_VAR \"mcinitcmd\"\n+\n+#ifdef CONFIG_FSL_MC_ENET\n+\n+#define SFP_TX\t\t0\n+\n+ /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.\n+ *   Bank 1 -> Lanes A, B, C, D,\n+ *   Bank 2 -> Lanes A,B, C, D,\n+ */\n+\n+ /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here\n+  * means that the mapping must be determined dynamically, or that the lane\n+  * maps to something other than a board slot.\n+  */\n+\n+static u8 lane_to_slot_fsm1[] = {\n+\t0, 0, 0, 0, 0, 0, 0, 0\n+};\n+\n+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs\n+ * housed.\n+ */\n+\n+static int xqsgii_riser_phy_addr[] = {\n+\tXQSGMII_CARD_PHY1_PORT0_ADDR,\n+\tXQSGMII_CARD_PHY2_PORT0_ADDR,\n+\tXQSGMII_CARD_PHY3_PORT0_ADDR,\n+\tXQSGMII_CARD_PHY4_PORT0_ADDR,\n+\tXQSGMII_CARD_PHY3_PORT2_ADDR,\n+\tXQSGMII_CARD_PHY1_PORT2_ADDR,\n+\tXQSGMII_CARD_PHY4_PORT2_ADDR,\n+\tXQSGMII_CARD_PHY2_PORT2_ADDR,\n+};\n+\n+static int sgmii_riser_phy_addr[] = {\n+\tSGMII_CARD_PORT1_PHY_ADDR,\n+\tSGMII_CARD_PORT2_PHY_ADDR,\n+\tSGMII_CARD_PORT3_PHY_ADDR,\n+\tSGMII_CARD_PORT4_PHY_ADDR,\n+};\n+\n+/* Slot2 does not have EMI connections */\n+#define EMI_NONE\t0xFF\n+#define EMI1_RGMII1\t0\n+#define EMI1_RGMII2\t1\n+#define EMI1_SLOT1\t2\n+\n+static const char * const mdio_names[] = {\n+\t\"LS1088A_QDS_MDIO0\",\n+\t\"LS1088A_QDS_MDIO1\",\n+\t\"LS1088A_QDS_MDIO2\",\n+\tDEFAULT_WRIOP_MDIO2_NAME,\n+};\n+\n+struct ls1088a_qds_mdio {\n+\tu8 muxval;\n+\tstruct mii_dev *realbus;\n+};\n+\n+static void sgmii_configure_repeater(int dpmac)\n+{\n+\tstruct mii_dev *bus;\n+\tuint8_t a = 0xf;\n+\tint i, j, ret;\n+\tunsigned short value;\n+\tconst char *dev = \"LS1088A_QDS_MDIO2\";\n+\tint i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};\n+\tint i2c_phy_addr = 0;\n+\tint phy_addr = 0;\n+\n+\tuint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};\n+\tuint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};\n+\tuint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};\n+\tuint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};\n+\n+\t/* Set I2c to Slot 1 */\n+\ti2c_write(0x77, 0, 0, &a, 1);\n+\n+\tswitch (dpmac) {\n+\tcase 1:\n+\t\ti2c_phy_addr = i2c_addr[1];\n+\t\tphy_addr = 4;\n+\t\tbreak;\n+\tcase 2:\n+\t\ti2c_phy_addr = i2c_addr[0];\n+\t\tphy_addr = 0;\n+\t\tbreak;\n+\tcase 3:\n+\t\ti2c_phy_addr = i2c_addr[3];\n+\t\tphy_addr = 0xc;\n+\t\tbreak;\n+\tcase 7:\n+\t\ti2c_phy_addr = i2c_addr[2];\n+\t\tphy_addr = 8;\n+\t\tbreak;\n+\t}\n+\n+\t/* Check the PHY status */\n+\tret = miiphy_set_current_dev(dev);\n+\tif (ret > 0)\n+\t\tgoto error;\n+\n+\tbus = mdio_get_current_dev();\n+\tdebug(\"Reading from bus %s\\n\", bus->name);\n+\n+\tret = miiphy_write(dev, phy_addr, 0x1f, 3);\n+\tif (ret > 0)\n+\t\tgoto error;\n+\n+\tmdelay(10);\n+\tret = miiphy_read(dev, phy_addr, 0x11, &value);\n+\tif (ret > 0)\n+\t\t\tgoto error;\n+\n+\tmdelay(10);\n+\n+\tif ((value & 0xfff) == 0x401) {\n+\t\tmiiphy_write(dev, phy_addr, 0x1f, 0);\n+\t\tprintf(\"DPMAC %d:PHY is ..... Configured\\n\", dpmac);\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\ta = 0x18;\n+\t\t\ti2c_write(i2c_phy_addr, 6, 1, &a, 1);\n+\t\t\ta = 0x38;\n+\t\t\ti2c_write(i2c_phy_addr, 4, 1, &a, 1);\n+\t\t\ta = 0x4;\n+\t\t\ti2c_write(i2c_phy_addr, 8, 1, &a, 1);\n+\n+\t\t\ti2c_write(i2c_phy_addr, 0xf, 1,\n+\t\t\t\t  &ch_a_eq[i], 1);\n+\t\t\ti2c_write(i2c_phy_addr, 0x11, 1,\n+\t\t\t\t  &ch_a_ctl2[j], 1);\n+\n+\t\t\ti2c_write(i2c_phy_addr, 0x16, 1,\n+\t\t\t\t  &ch_b_eq[i], 1);\n+\t\t\ti2c_write(i2c_phy_addr, 0x18, 1,\n+\t\t\t\t  &ch_b_ctl2[j], 1);\n+\n+\t\t\ta = 0x14;\n+\t\t\ti2c_write(i2c_phy_addr, 0x23, 1, &a, 1);\n+\t\t\ta = 0xb5;\n+\t\t\ti2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);\n+\t\t\ta = 0x20;\n+\t\t\ti2c_write(i2c_phy_addr, 4, 1, &a, 1);\n+\t\t\tmdelay(100);\n+\t\t\tret = miiphy_read(dev, phy_addr, 0x11, &value);\n+\t\t\tif (ret > 0)\n+\t\t\t\tgoto error;\n+\n+\t\t\tmdelay(100);\n+\t\t\tret = miiphy_read(dev, phy_addr, 0x11, &value);\n+\t\t\tif (ret > 0)\n+\t\t\t\tgoto error;\n+\n+\t\t\tif ((value & 0xfff) == 0x401) {\n+\t\t\t\tprintf(\"DPMAC %d :PHY is configured \",\n+\t\t\t\t       dpmac);\n+\t\t\t\tprintf(\"after setting repeater 0x%x\\n\",\n+\t\t\t\t       value);\n+\t\t\t\ti = 5;\n+\t\t\t\tj = 5;\n+\t\t\t} else {\n+\t\t\t\tprintf(\"DPMAC %d :PHY is failed to \",\n+\t\t\t\t\t       dpmac);\n+\t\t\t\tprintf(\"configure the repeater 0x%x\\n\", value);\n+\t\t\t}\n+\t\t}\n+\t}\n+\tmiiphy_write(dev, phy_addr, 0x1f, 0);\n+error:\n+\tif (ret)\n+\t\tprintf(\"DPMAC %d ..... FAILED to configure PHY\\n\", dpmac);\n+\treturn;\n+}\n+\n+static void qsgmii_configure_repeater(int dpmac)\n+{\n+\tuint8_t a = 0xf;\n+\tint i, j;\n+\tint i2c_phy_addr = 0;\n+\tint phy_addr = 0;\n+\tint i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};\n+\n+\tuint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};\n+\tuint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};\n+\tuint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};\n+\tuint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};\n+\n+\tconst char *dev = mdio_names[EMI1_SLOT1];\n+\tint ret = 0;\n+\tunsigned short value;\n+\n+\t/* Set I2c to Slot 1 */\n+\ti2c_write(0x77, 0, 0, &a, 1);\n+\n+\tswitch (dpmac) {\n+\tcase 7:\n+\tcase 8:\n+\tcase 9:\n+\tcase 10:\n+\t\ti2c_phy_addr = i2c_addr[2];\n+\t\tphy_addr = 8;\n+\t\tbreak;\n+\n+\tcase 3:\n+\tcase 4:\n+\tcase 5:\n+\tcase 6:\n+\t\ti2c_phy_addr = i2c_addr[3];\n+\t\tphy_addr = 0xc;\n+\t\tbreak;\n+\t}\n+\n+\t/* Check the PHY status */\n+\tret = miiphy_set_current_dev(dev);\n+\tret = miiphy_write(dev, phy_addr, 0x1f, 3);\n+\tmdelay(10);\n+\tret = miiphy_read(dev, phy_addr, 0x11, &value);\n+\tmdelay(10);\n+\tret = miiphy_read(dev, phy_addr, 0x11, &value);\n+\tmdelay(10);\n+\tif ((value & 0xf) == 0xf) {\n+\t\tmiiphy_write(dev, phy_addr, 0x1f, 0);\n+\t\tprintf(\"DPMAC %d :PHY is ..... Configured\\n\", dpmac);\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\ta = 0x18;\n+\t\t\ti2c_write(i2c_phy_addr, 6, 1, &a, 1);\n+\t\t\ta = 0x38;\n+\t\t\ti2c_write(i2c_phy_addr, 4, 1, &a, 1);\n+\t\t\ta = 0x4;\n+\t\t\ti2c_write(i2c_phy_addr, 8, 1, &a, 1);\n+\n+\t\t\ti2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);\n+\t\t\ti2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);\n+\n+\t\t\ti2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);\n+\t\t\ti2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);\n+\n+\t\t\ta = 0x14;\n+\t\t\ti2c_write(i2c_phy_addr, 0x23, 1, &a, 1);\n+\t\t\ta = 0xb5;\n+\t\t\ti2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);\n+\t\t\ta = 0x20;\n+\t\t\ti2c_write(i2c_phy_addr, 4, 1, &a, 1);\n+\t\t\tmdelay(100);\n+\t\t\tret = miiphy_read(dev, phy_addr, 0x11, &value);\n+\t\t\tif (ret > 0)\n+\t\t\t\tgoto error;\n+\t\t\tmdelay(1);\n+\t\t\tret = miiphy_read(dev, phy_addr, 0x11, &value);\n+\t\t\tif (ret > 0)\n+\t\t\t\tgoto error;\n+\t\t\tmdelay(10);\n+\t\t\tif ((value & 0xf) == 0xf) {\n+\t\t\t\tmiiphy_write(dev, phy_addr, 0x1f, 0);\n+\t\t\t\tprintf(\"DPMAC %d :PHY is ..... Configured\\n\",\n+\t\t\t\t       dpmac);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t}\n+\t}\n+error:\n+\tprintf(\"DPMAC %d :PHY ..... FAILED to configure PHY\\n\", dpmac);\n+\treturn;\n+}\n+\n+static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)\n+{\n+\treturn mdio_names[muxval];\n+}\n+\n+struct mii_dev *mii_dev_for_muxval(u8 muxval)\n+{\n+\tstruct mii_dev *bus;\n+\tconst char *name = ls1088a_qds_mdio_name_for_muxval(muxval);\n+\n+\tif (!name) {\n+\t\tprintf(\"No bus for muxval %x\\n\", muxval);\n+\t\treturn NULL;\n+\t}\n+\n+\tbus = miiphy_get_dev_by_name(name);\n+\n+\tif (!bus) {\n+\t\tprintf(\"No bus by name %s\\n\", name);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn bus;\n+}\n+\n+static void ls1088a_qds_enable_SFP_TX(u8 muxval)\n+{\n+\tu8 brdcfg9;\n+\n+\tbrdcfg9 = QIXIS_READ(brdcfg[9]);\n+\tbrdcfg9 &= ~BRDCFG9_SFPTX_MASK;\n+\tbrdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);\n+\tQIXIS_WRITE(brdcfg[9], brdcfg9);\n+}\n+\n+static void ls1088a_qds_mux_mdio(u8 muxval)\n+{\n+\tu8 brdcfg4;\n+\n+\tif (muxval <= 5) {\n+\t\tbrdcfg4 = QIXIS_READ(brdcfg[4]);\n+\t\tbrdcfg4 &= ~BRDCFG4_EMISEL_MASK;\n+\t\tbrdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);\n+\t\tQIXIS_WRITE(brdcfg[4], brdcfg4);\n+\t}\n+}\n+\n+static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,\n+\t\t\t\t int devad, int regnum)\n+{\n+\tstruct ls1088a_qds_mdio *priv = bus->priv;\n+\n+\tls1088a_qds_mux_mdio(priv->muxval);\n+\n+\treturn priv->realbus->read(priv->realbus, addr, devad, regnum);\n+}\n+\n+static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,\n+\t\t\t\t  int regnum, u16 value)\n+{\n+\tstruct ls1088a_qds_mdio *priv = bus->priv;\n+\n+\tls1088a_qds_mux_mdio(priv->muxval);\n+\n+\treturn priv->realbus->write(priv->realbus, addr, devad, regnum, value);\n+}\n+\n+static int ls1088a_qds_mdio_reset(struct mii_dev *bus)\n+{\n+\tstruct ls1088a_qds_mdio *priv = bus->priv;\n+\n+\treturn priv->realbus->reset(priv->realbus);\n+}\n+\n+static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)\n+{\n+\tstruct ls1088a_qds_mdio *pmdio;\n+\tstruct mii_dev *bus = mdio_alloc();\n+\n+\tif (!bus) {\n+\t\tprintf(\"Failed to allocate ls1088a_qds MDIO bus\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpmdio = malloc(sizeof(*pmdio));\n+\tif (!pmdio) {\n+\t\tprintf(\"Failed to allocate ls1088a_qds private data\\n\");\n+\t\tfree(bus);\n+\t\treturn -1;\n+\t}\n+\n+\tbus->read = ls1088a_qds_mdio_read;\n+\tbus->write = ls1088a_qds_mdio_write;\n+\tbus->reset = ls1088a_qds_mdio_reset;\n+\tsprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));\n+\n+\tpmdio->realbus = miiphy_get_dev_by_name(realbusname);\n+\n+\tif (!pmdio->realbus) {\n+\t\tprintf(\"No bus with name %s\\n\", realbusname);\n+\t\tfree(bus);\n+\t\tfree(pmdio);\n+\t\treturn -1;\n+\t}\n+\n+\tpmdio->muxval = muxval;\n+\tbus->priv = pmdio;\n+\n+\treturn mdio_register(bus);\n+}\n+\n+/*\n+ * Initialize the dpmac_info array.\n+ *\n+ */\n+static void initialize_dpmac_to_slot(void)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\tu32 serdes1_prtcl, cfg;\n+\n+\tcfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &\n+\t\t\t\tFSL_CHASSIS3_SRDS1_PRTCL_MASK;\n+\tcfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n+\tserdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);\n+\n+\tswitch (serdes1_prtcl) {\n+\tcase 0x12:\n+\t\tprintf(\"qds: WRIOP: Supported SerDes1 Protocol 0x%02x\\n\",\n+\t\t       serdes1_prtcl);\n+\t\tlane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;\n+\t\tbreak;\n+\tcase 0x15:\n+\tcase 0x1D:\n+\t\tprintf(\"qds: WRIOP: Supported SerDes1 Protocol 0x%02x\\n\",\n+\t\t       serdes1_prtcl);\n+\t\tlane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[2] = EMI_NONE;\n+\t\tlane_to_slot_fsm1[3] = EMI_NONE;\n+\t\tbreak;\n+\tcase 0x1E:\n+\t\tprintf(\"qds: WRIOP: Supported SerDes1 Protocol 0x%02x\\n\",\n+\t\t       serdes1_prtcl);\n+\t\tlane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[3] = EMI_NONE;\n+\t\tbreak;\n+\tcase 0x3A:\n+\t\tprintf(\"qds: WRIOP: Supported SerDes1 Protocol 0x%02x\\n\",\n+\t\t       serdes1_prtcl);\n+\t\tlane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[1] = EMI_NONE;\n+\t\tlane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;\n+\t\tlane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tprintf(\"%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\\n\",\n+\t\t       __func__, serdes1_prtcl);\n+\t\tbreak;\n+\t}\n+}\n+\n+void ls1088a_handle_phy_interface_sgmii(int dpmac_id)\n+{\n+\tstruct mii_dev *bus;\n+\tstruct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\tu32 serdes1_prtcl, cfg;\n+\n+\tcfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &\n+\t\t\t\tFSL_CHASSIS3_SRDS1_PRTCL_MASK;\n+\tcfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n+\tserdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);\n+\n+\tint *riser_phy_addr;\n+\tchar *env_hwconfig = getenv(\"hwconfig\");\n+\n+\tif (hwconfig_f(\"xqsgmii\", env_hwconfig))\n+\t\triser_phy_addr = &xqsgii_riser_phy_addr[0];\n+\telse\n+\t\triser_phy_addr = &sgmii_riser_phy_addr[0];\n+\n+\tswitch (serdes1_prtcl) {\n+\tcase 0x12:\n+\tcase 0x15:\n+\tcase 0x1E:\n+\tcase 0x3A:\n+\t\tswitch (dpmac_id) {\n+\t\tcase 1:\n+\t\t\twriop_set_phy_address(dpmac_id, riser_phy_addr[1]);\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\twriop_set_phy_address(dpmac_id, riser_phy_addr[0]);\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\twriop_set_phy_address(dpmac_id, riser_phy_addr[3]);\n+\t\t\tbreak;\n+\t\tcase 7:\n+\t\t\twriop_set_phy_address(dpmac_id, riser_phy_addr[2]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tprintf(\"WRIOP: Wrong DPMAC%d set to SGMII\", dpmac_id);\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\\n\",\n+\t\t       __func__, serdes1_prtcl);\n+\t\treturn;\n+\t}\n+\tdpmac_info[dpmac_id].board_mux = EMI1_SLOT1;\n+\tbus = mii_dev_for_muxval(EMI1_SLOT1);\n+\twriop_set_mdio(dpmac_id, bus);\n+}\n+\n+void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)\n+{\n+\tstruct mii_dev *bus;\n+\tstruct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\tu32 serdes1_prtcl, cfg;\n+\n+\tcfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &\n+\t\t\t\tFSL_CHASSIS3_SRDS1_PRTCL_MASK;\n+\tcfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n+\tserdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);\n+\n+\tswitch (serdes1_prtcl) {\n+\tcase 0x1D:\n+\tcase 0x1E:\n+\t\tswitch (dpmac_id) {\n+\t\tcase 3:\n+\t\tcase 4:\n+\t\tcase 5:\n+\t\tcase 6:\n+\t\t\twriop_set_phy_address(dpmac_id, dpmac_id + 9);\n+\t\t\tbreak;\n+\t\tcase 7:\n+\t\tcase 8:\n+\t\tcase 9:\n+\t\tcase 10:\n+\t\t\twriop_set_phy_address(dpmac_id, dpmac_id + 1);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tdpmac_info[dpmac_id].board_mux = EMI1_SLOT1;\n+\t\tbus = mii_dev_for_muxval(EMI1_SLOT1);\n+\t\twriop_set_mdio(dpmac_id, bus);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"qds: WRIOP: Unsupported SerDes Protocol 0x%02x\\n\",\n+\t\t       serdes1_prtcl);\n+\t\tbreak;\n+\t}\n+}\n+\n+void ls1088a_handle_phy_interface_xsgmii(int i)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\tu32 serdes1_prtcl, cfg;\n+\n+\tcfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &\n+\t\t\t\tFSL_CHASSIS3_SRDS1_PRTCL_MASK;\n+\tcfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n+\tserdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);\n+\n+\tswitch (serdes1_prtcl) {\n+\tcase 0x15:\n+\tcase 0x1D:\n+\tcase 0x1E:\n+\t\twriop_set_phy_address(i, i + 26);\n+\t\tls1088a_qds_enable_SFP_TX(SFP_TX);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"qds: WRIOP: Unsupported SerDes Protocol 0x%02x\\n\",\n+\t\t       serdes1_prtcl);\n+\t\tbreak;\n+\t}\n+}\n+#endif\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\tint error = 0, i;\n+\tchar *mc_boot_env_var;\n+#ifdef CONFIG_FSL_MC_ENET\n+\tstruct memac_mdio_info *memac_mdio0_info;\n+\tchar *env_hwconfig = getenv(\"hwconfig\");\n+\n+\tinitialize_dpmac_to_slot();\n+\n+\tmemac_mdio0_info = (struct memac_mdio_info *)malloc(\n+\t\t\t\t\tsizeof(struct memac_mdio_info));\n+\tmemac_mdio0_info->regs =\n+\t\t(struct memac_mdio_controller *)\n+\t\t\t\t\tCONFIG_SYS_FSL_WRIOP1_MDIO1;\n+\tmemac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;\n+\n+\t/* Register the real MDIO1 bus */\n+\tfm_memac_mdio_init(bis, memac_mdio0_info);\n+\n+\t/* Register the muxing front-ends to the MDIO buses */\n+\tls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);\n+\tls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);\n+\tls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);\n+\n+\tfor (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {\n+\t\tswitch (wriop_get_enet_if(i)) {\n+\t\tcase PHY_INTERFACE_MODE_QSGMII:\n+\t\t\tls1088a_handle_phy_interface_qsgmii(i);\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\t\tls1088a_handle_phy_interface_sgmii(i);\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_XGMII:\n+\t\t\tls1088a_handle_phy_interface_xsgmii(i);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\n+\t\tif (i == 16)\n+\t\t\ti = NUM_WRIOP_PORTS;\n+\t\t}\n+\t}\n+\n+\tmc_boot_env_var = getenv(MC_BOOT_ENV_VAR);\n+\tif (mc_boot_env_var)\n+\t\trun_command_list(mc_boot_env_var, -1, 0);\n+\terror = cpu_eth_init(bis);\n+\n+\tif (hwconfig_f(\"xqsgmii\", env_hwconfig)) {\n+\t\tfor (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {\n+\t\t\tswitch (wriop_get_enet_if(i)) {\n+\t\t\tcase PHY_INTERFACE_MODE_QSGMII:\n+\t\t\t\tqsgmii_configure_repeater(i);\n+\t\t\t\tbreak;\n+\t\t\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\t\t\tsgmii_configure_repeater(i);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (i == 16)\n+\t\t\t\ti = NUM_WRIOP_PORTS;\n+\t\t}\n+\t}\n+#endif\n+\terror = pci_eth_init(bis);\n+\treturn error;\n+}\ndiff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c\nindex f3c20ac..d1de4d1 100644\n--- a/board/freescale/ls1088a/ls1088a.c\n+++ b/board/freescale/ls1088a/ls1088a.c\n@@ -50,14 +50,20 @@ int checkboard(void)\n \t\t\t\t\t    \"100 separate SSCG\"};\n \tint clock;\n \n-\n+#ifdef CONFIG_TARGET_LS1088AQDS\n+\tprintf(\"Board: LS1088A-QDS, \");\n+#else\n \tprintf(\"Board: LS1088A-RDB, \");\n+#endif\n \n \tsw = QIXIS_READ(arch);\n \tprintf(\"Board Arch: V%d, \", sw >> 4);\n \n+#ifdef CONFIG_TARGET_LS1088AQDS\n+\tprintf(\"Board version: %c, boot from \", (sw & 0xf) + 'A' - 1);\n+#else\n \tprintf(\"Board version: %c, boot from \", (sw & 0xf) + 'A');\n-\n+#endif\n \n \tmemset((u8 *)buf, 0x00, ARRAY_SIZE(buf));\n \n@@ -68,9 +74,27 @@ int checkboard(void)\n \tputs(\"SD card\\n\");\n #endif\n \tswitch (sw) {\n-\n+#ifdef CONFIG_TARGET_LS1088AQDS\n \tcase 0:\n-\n+\tcase 1:\n+\tcase 2:\n+\tcase 3:\n+\tcase 4:\n+\tcase 5:\n+\tcase 6:\n+\tcase 7:\n+\t\tprintf(\"vBank: %d\\n\", sw);\n+\t\tbreak;\n+\tcase 8:\n+\t\tputs(\"PromJet\\n\");\n+\t\tbreak;\n+\tcase 15:\n+\t\tputs(\"IFCCard\\n\");\n+\t\tbreak;\n+\tcase 14:\n+#else\n+\tcase 0:\n+#endif\n \t\tputs(\"QSPI:\");\n \t\tsw = QIXIS_READ(brdcfg[0]);\n \t\tsw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;\n@@ -87,9 +111,15 @@ int checkboard(void)\n \t\tbreak;\n \t}\n \n-\n+#ifdef CONFIG_TARGET_LS1088AQDS\n+\tprintf(\"FPGA: v%d (%s), build %d\",\n+\t       (int)QIXIS_READ(scver), qixis_read_tag(buf),\n+\t       (int)qixis_read_minor());\n+\t/* the timestamp string contains \"\\n\" at the end */\n+\tprintf(\" on %s\", qixis_read_time(buf));\n+#else\n \tprintf(\"CPLD: v%d.%d\\n\", QIXIS_READ(scver), QIXIS_READ(tagdata));\n-\n+#endif\n \n \t/*\n \t * Display the actual SERDES reference clocks as configured by the\n@@ -117,10 +147,13 @@ int checkboard(void)\n \n bool if_board_diff_clk(void)\n {\n-\n+#ifdef CONFIG_TARGET_LS1088AQDS\n+\tu8 diff_conf = QIXIS_READ(brdcfg[11]);\n+\treturn diff_conf & 0x40;\n+#else\n \tu8 diff_conf = QIXIS_READ(dutcfg[11]);\n \treturn diff_conf & 0x80;\n-\n+#endif\n }\n \n unsigned long get_board_sys_clk(void)\n@@ -220,7 +253,45 @@ void board_retimer_init(void)\n \treg |= 0x70;\n \ti2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);\n \n+#ifdef\tCONFIG_TARGET_LS1088AQDS\n+\t/* Retimer is connected to I2C1_CH5 */\n+\tselect_i2c_ch_pca9547(I2C_MUX_CH5);\n+\n+\t/* Access to Control/Shared register */\n+\treg = 0x0;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);\n+\n+\t/* Read device revision and ID */\n+\ti2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);\n+\tdebug(\"Retimer version id = 0x%x\\n\", reg);\n \n+\t/* Enable Broadcast. All writes target all channel register sets */\n+\treg = 0x0c;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);\n+\n+\t/* Reset Channel Registers */\n+\ti2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);\n+\treg |= 0x4;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);\n+\n+\t/* Set data rate as 10.3125 Gbps */\n+\treg = 0x90;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);\n+\treg = 0xb3;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);\n+\treg = 0x90;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);\n+\treg = 0xb3;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);\n+\treg = 0xcd;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);\n+\n+\t/* Select VCO Divider to full rate (000) */\n+\ti2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);\n+\treg &= 0x0f;\n+\treg |= 0x70;\n+\ti2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);\n+#endif\n \t/*return the default channel*/\n \tselect_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);\n }\ndiff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h\nindex 9757d1b..4790461 100644\n--- a/board/freescale/ls1088a/ls1088a_qixis.h\n+++ b/board/freescale/ls1088a/ls1088a_qixis.h\n@@ -31,4 +31,9 @@\n #define QIXIS_SDCLK1_165\t\t0x2\n #define QIXIS_SDCLK1_100_SP\t\t0x3\n \n+#define BRDCFG4_EMISEL_MASK\t\t0xE0\n+#define BRDCFG4_EMISEL_SHIFT\t\t5\n+#define BRDCFG9_SFPTX_MASK\t\t0x10\n+#define BRDCFG9_SFPTX_SHIFT\t\t4\n+\n #endif\ndiff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig\nnew file mode 100644\nindex 0000000..6fff149\n--- /dev/null\n+++ b/configs/ls1088aqds_qspi_defconfig\n@@ -0,0 +1,29 @@\n+CONFIG_ARM=y\n+CONFIG_TARGET_LS1088AQDS=y\n+# CONFIG_SYS_MALLOC_F is not set\n+CONFIG_DM_SPI=y\n+CONFIG_DM_SPI_FLASH=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"fsl-ls1088a-qds\"\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_OF_BOARD_SETUP=y\n+CONFIG_OF_STDOUT_VIA_ALIAS=y\n+CONFIG_SYS_EXTRA_OPTIONS=\"SYS_FSL_DDR4, QSPI_BOOT\"\n+CONFIG_HUSH_PARSER=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_SF=y\n+CONFIG_CMD_I2C=y\n+# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_PING=y\n+CONFIG_OF_CONTROL=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_DM=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_NETDEVICES=y\n+CONFIG_E1000=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_FSL_DSPI=y\n+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y\n+# CONFIG_DISPLAY_BOARDINFO is not set\n+CONFIG_FSL_LS_PPA=y\ndiff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h\nnew file mode 100644\nindex 0000000..3547b0b\n--- /dev/null\n+++ b/include/configs/ls1088aqds.h\n@@ -0,0 +1,414 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LS1088A_QDS_H\n+#define __LS1088A_QDS_H\n+\n+#include \"ls1088a_common.h\"\n+\n+\n+#define CONFIG_DISPLAY_BOARDINFO_LATE\n+\n+\n+#ifndef __ASSEMBLY__\n+unsigned long get_board_sys_clk(void);\n+unsigned long get_board_ddr_clk(void);\n+#endif\n+\n+\n+#if defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_ENV_IS_IN_SPI_FLASH\n+#define CONFIG_ENV_SIZE\t\t\t0x2000          /* 8KB */\n+#define CONFIG_ENV_OFFSET\t\t0x300000        /* 3MB */\n+#define CONFIG_ENV_SECT_SIZE\t\t0x40000\n+#else\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_ADDR\t\t\t(CONFIG_SYS_FLASH_BASE + 0x300000)\n+#define CONFIG_ENV_SECT_SIZE\t\t0x20000\n+#define CONFIG_ENV_SIZE\t\t\t0x20000\n+#endif\n+\n+#if defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_QIXIS_I2C_ACCESS\n+#define SYS_NO_FLASH\n+\n+#undef CONFIG_CMD_IMLS\n+#define CONFIG_SYS_CLK_FREQ\t\t100000000\n+#define CONFIG_DDR_CLK_FREQ\t\t100000000\n+#else\n+#define CONFIG_SYS_CLK_FREQ\t\tget_board_sys_clk()\n+#define CONFIG_DDR_CLK_FREQ\t\tget_board_ddr_clk()\n+#endif\n+\n+#define COUNTER_FREQUENCY_REAL\t\t(CONFIG_SYS_CLK_FREQ/4)\n+#define COUNTER_FREQUENCY\t\t25000000\t/* 25MHz */\n+\n+#define CONFIG_DIMM_SLOTS_PER_CTLR\t1\n+\n+#define CONFIG_DDR_SPD\n+#define CONFIG_DDR_ECC\n+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\n+#define CONFIG_MEM_INIT_VALUE           0xdeadbeef\n+#define SPD_EEPROM_ADDRESS\t\t0x51\n+#define CONFIG_SYS_SPD_BUS_NUM\t\t0\n+\n+\n+/*\n+ * IFC Definitions\n+ */\n+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)\n+#define CONFIG_SYS_NOR0_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_NOR_AMASK\t\tIFC_AMASK(128*1024*1024)\n+#define CONFIG_SYS_NOR_AMASK_EARLY\tIFC_AMASK(64*1024*1024)\n+\n+#define CONFIG_SYS_NOR0_CSPR\t\t\t\t\t\\\n+\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)\t\t| \\\n+\tCSPR_PORT_SIZE_16\t\t\t\t\t| \\\n+\tCSPR_MSEL_NOR\t\t\t\t\t\t| \\\n+\tCSPR_V)\n+#define CONFIG_SYS_NOR0_CSPR_EARLY\t\t\t\t\\\n+\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)\t| \\\n+\tCSPR_PORT_SIZE_16\t\t\t\t\t| \\\n+\tCSPR_MSEL_NOR\t\t\t\t\t\t| \\\n+\tCSPR_V)\n+#define CONFIG_SYS_NOR1_CSPR\t\t\t\t\t\\\n+\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)\t\t| \\\n+\tCSPR_PORT_SIZE_16\t\t\t\t\t| \\\n+\tCSPR_MSEL_NOR\t\t\t\t\t\t| \\\n+\tCSPR_V)\n+#define CONFIG_SYS_NOR1_CSPR_EARLY\t\t\t\t\\\n+\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)\t| \\\n+\tCSPR_PORT_SIZE_16\t\t\t\t\t| \\\n+\tCSPR_MSEL_NOR\t\t\t\t\t\t| \\\n+\tCSPR_V)\n+#define CONFIG_SYS_NOR_CSOR\tCSOR_NOR_ADM_SHIFT(12)\n+#define CONFIG_SYS_NOR_FTIM0\t(FTIM0_NOR_TACSE(0x4) | \\\n+\t\t\t\tFTIM0_NOR_TEADC(0x5) | \\\n+\t\t\t\tFTIM0_NOR_TEAHC(0x5))\n+#define CONFIG_SYS_NOR_FTIM1\t(FTIM1_NOR_TACO(0x35) | \\\n+\t\t\t\tFTIM1_NOR_TRAD_NOR(0x1a) |\\\n+\t\t\t\tFTIM1_NOR_TSEQRAD_NOR(0x13))\n+#define CONFIG_SYS_NOR_FTIM2\t(FTIM2_NOR_TCS(0x4) | \\\n+\t\t\t\tFTIM2_NOR_TCH(0x4) | \\\n+\t\t\t\tFTIM2_NOR_TWPH(0x0E) | \\\n+\t\t\t\tFTIM2_NOR_TWP(0x1c))\n+#define CONFIG_SYS_NOR_FTIM3\t0x04000000\n+#define CONFIG_SYS_IFC_CCR\t0x01000000\n+\n+#ifndef SYS_NO_FLASH\n+#define CONFIG_FLASH_CFI_DRIVER\n+#define CONFIG_SYS_FLASH_CFI\n+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n+#define CONFIG_SYS_FLASH_QUIET_TEST\n+#define CONFIG_FLASH_SHOW_PROGRESS\t45 /* count down from 45/5: 9..1 */\n+\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t2\t/* number of banks */\n+#define CONFIG_SYS_MAX_FLASH_SECT\t1024\t/* sectors per device */\n+#define CONFIG_SYS_FLASH_ERASE_TOUT\t60000\t/* Flash Erase Timeout (ms) */\n+#define CONFIG_SYS_FLASH_WRITE_TOUT\t500\t/* Flash Write Timeout (ms) */\n+\n+#define CONFIG_SYS_FLASH_EMPTY_INFO\n+#define CONFIG_SYS_FLASH_BANKS_LIST\t{ CONFIG_SYS_FLASH_BASE,\\\n+\t\t\t\t\t CONFIG_SYS_FLASH_BASE + 0x40000000}\n+#endif\n+#endif\n+\n+#define CONFIG_NAND_FSL_IFC\n+#define CONFIG_SYS_NAND_MAX_ECCPOS\t256\n+#define CONFIG_SYS_NAND_MAX_OOBFREE\t2\n+\n+#define CONFIG_SYS_NAND_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_NAND_CSPR\t(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \\\n+\t\t\t\t| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \\\n+\t\t\t\t| CSPR_MSEL_NAND\t/* MSEL = NAND */ \\\n+\t\t\t\t| CSPR_V)\n+#define CONFIG_SYS_NAND_AMASK\tIFC_AMASK(64 * 1024)\n+\n+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \\\n+\t\t\t\t| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \\\n+\t\t\t\t| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \\\n+\t\t\t\t| CSOR_NAND_RAL_3\t/* RAL = 3Byes */ \\\n+\t\t\t\t| CSOR_NAND_PGS_2K\t/* Page Size = 2K */ \\\n+\t\t\t\t| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \\\n+\t\t\t\t| CSOR_NAND_PB(64))\t/*Pages Per Block = 64*/\n+\n+#define CONFIG_SYS_NAND_ONFI_DETECTION\n+\n+/* ONFI NAND Flash mode0 Timing Params */\n+#define CONFIG_SYS_NAND_FTIM0\t\t(FTIM0_NAND_TCCST(0x07) | \\\n+\t\t\t\t\tFTIM0_NAND_TWP(0x18)   | \\\n+\t\t\t\t\tFTIM0_NAND_TWCHT(0x07) | \\\n+\t\t\t\t\tFTIM0_NAND_TWH(0x0a))\n+#define CONFIG_SYS_NAND_FTIM1\t\t(FTIM1_NAND_TADLE(0x32) | \\\n+\t\t\t\t\tFTIM1_NAND_TWBE(0x39)  | \\\n+\t\t\t\t\tFTIM1_NAND_TRR(0x0e)   | \\\n+\t\t\t\t\tFTIM1_NAND_TRP(0x18))\n+#define CONFIG_SYS_NAND_FTIM2\t\t(FTIM2_NAND_TRAD(0x0f) | \\\n+\t\t\t\t\tFTIM2_NAND_TREH(0x0a) | \\\n+\t\t\t\t\tFTIM2_NAND_TWHRE(0x1e))\n+#define CONFIG_SYS_NAND_FTIM3\t\t0x0\n+\n+#define CONFIG_SYS_NAND_BASE_LIST\t{ CONFIG_SYS_NAND_BASE }\n+#define CONFIG_SYS_MAX_NAND_DEVICE\t1\n+#define CONFIG_MTD_NAND_VERIFY_WRITE\n+#define CONFIG_CMD_NAND\n+\n+#define CONFIG_SYS_NAND_BLOCK_SIZE\t(128 * 1024)\n+\n+#define CONFIG_FSL_QIXIS\n+#define CONFIG_SYS_I2C_FPGA_ADDR\t0x66\n+#define QIXIS_LBMAP_SWITCH\t\t6\n+#define QIXIS_QMAP_MASK\t\t\t0xe0\n+#define QIXIS_QMAP_SHIFT\t\t5\n+#define QIXIS_LBMAP_MASK\t\t0x0f\n+#define QIXIS_LBMAP_SHIFT\t\t0\n+#define QIXIS_LBMAP_DFLTBANK\t\t0x0e\n+#define QIXIS_LBMAP_ALTBANK\t\t0x2e\n+#define QIXIS_LBMAP_SD\t\t\t0x00\n+#define QIXIS_LBMAP_SD_QSPI\t\t0x0e\n+#define QIXIS_LBMAP_QSPI\t\t0x0e\n+#define QIXIS_RCW_SRC_SD\t\t0x40\n+#define QIXIS_RCW_SRC_QSPI\t\t0x62\n+#define QIXIS_RST_CTL_RESET\t\t0x41\n+#define QIXIS_RCFG_CTL_RECONFIG_IDLE\t0x20\n+#define QIXIS_RCFG_CTL_RECONFIG_START\t0x21\n+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE\t0x08\n+#define\tQIXIS_RST_FORCE_MEM\t\t0x01\n+#define QIXIS_STAT_PRES1\t\t0xb\n+#define QIXIS_SDID_MASK\t\t\t0x07\n+#define QIXIS_ESDHC_NO_ADAPTER\t\t0x7\n+\n+#define CONFIG_SYS_FPGA_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_FPGA_CSPR\t\t(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \\\n+\t\t\t\t\t| CSPR_PORT_SIZE_8 \\\n+\t\t\t\t\t| CSPR_MSEL_GPCM \\\n+\t\t\t\t\t| CSPR_V)\n+#define SYS_FPGA_CSPR_FINAL\t(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \\\n+\t\t\t\t\t| CSPR_PORT_SIZE_8 \\\n+\t\t\t\t\t| CSPR_MSEL_GPCM \\\n+\t\t\t\t\t| CSPR_V)\n+\n+#define CONFIG_SYS_FPGA_AMASK\t\tIFC_AMASK(64*1024)\n+#if defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_SYS_FPGA_CSOR\t\tCSOR_GPCM_ADM_SHIFT(0)\n+#else\n+#define CONFIG_SYS_FPGA_CSOR\t\tCSOR_GPCM_ADM_SHIFT(12)\n+#endif\n+/* QIXIS Timing parameters*/\n+#define SYS_FPGA_CS_FTIM0\t(FTIM0_GPCM_TACSE(0x0e) | \\\n+\t\t\t\t\tFTIM0_GPCM_TEADC(0x0e) | \\\n+\t\t\t\t\tFTIM0_GPCM_TEAHC(0x0e))\n+#define SYS_FPGA_CS_FTIM1\t(FTIM1_GPCM_TACO(0xff) | \\\n+\t\t\t\t\tFTIM1_GPCM_TRAD(0x3f))\n+#define SYS_FPGA_CS_FTIM2\t(FTIM2_GPCM_TCS(0xf) | \\\n+\t\t\t\t\tFTIM2_GPCM_TCH(0xf) | \\\n+\t\t\t\t\tFTIM2_GPCM_TWP(0x3E))\n+#define SYS_FPGA_CS_FTIM3\t0x0\n+\n+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NAND_CSPR_EXT\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NAND_CSPR\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NAND_AMASK\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NAND_CSOR\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NAND_FTIM0\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NAND_FTIM1\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NAND_FTIM2\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NAND_FTIM3\n+#define CONFIG_SYS_CSPR2_EXT\t\tCONFIG_SYS_FPGA_CSPR_EXT\n+#define CONFIG_SYS_CSPR2\t\tCONFIG_SYS_FPGA_CSPR\n+#define CONFIG_SYS_CSPR2_FINAL\t\tSYS_FPGA_CSPR_FINAL\n+#define CONFIG_SYS_AMASK2\t\tCONFIG_SYS_FPGA_AMASK\n+#define CONFIG_SYS_CSOR2\t\tCONFIG_SYS_FPGA_CSOR\n+#define CONFIG_SYS_CS2_FTIM0\t\tSYS_FPGA_CS_FTIM0\n+#define CONFIG_SYS_CS2_FTIM1\t\tSYS_FPGA_CS_FTIM1\n+#define CONFIG_SYS_CS2_FTIM2\t\tSYS_FPGA_CS_FTIM2\n+#define CONFIG_SYS_CS2_FTIM3\t\tSYS_FPGA_CS_FTIM3\n+#else\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NOR0_CSPR_EXT\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NOR0_CSPR_EARLY\n+#define CONFIG_SYS_CSPR0_FINAL\t\tCONFIG_SYS_NOR0_CSPR\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR1_EXT\t\tCONFIG_SYS_NOR0_CSPR_EXT\n+#define CONFIG_SYS_CSPR1\t\tCONFIG_SYS_NOR1_CSPR_EARLY\n+#define CONFIG_SYS_CSPR1_FINAL\t\tCONFIG_SYS_NOR1_CSPR\n+#define CONFIG_SYS_AMASK1\t\tCONFIG_SYS_NOR_AMASK_EARLY\n+#define CONFIG_SYS_AMASK1_FINAL\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR1\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS1_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS1_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS1_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS1_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR2_EXT\t\tCONFIG_SYS_NAND_CSPR_EXT\n+#define CONFIG_SYS_CSPR2\t\tCONFIG_SYS_NAND_CSPR\n+#define CONFIG_SYS_AMASK2\t\tCONFIG_SYS_NAND_AMASK\n+#define CONFIG_SYS_CSOR2\t\tCONFIG_SYS_NAND_CSOR\n+#define CONFIG_SYS_CS2_FTIM0\t\tCONFIG_SYS_NAND_FTIM0\n+#define CONFIG_SYS_CS2_FTIM1\t\tCONFIG_SYS_NAND_FTIM1\n+#define CONFIG_SYS_CS2_FTIM2\t\tCONFIG_SYS_NAND_FTIM2\n+#define CONFIG_SYS_CS2_FTIM3\t\tCONFIG_SYS_NAND_FTIM3\n+#define CONFIG_SYS_CSPR3_EXT\t\tCONFIG_SYS_FPGA_CSPR_EXT\n+#define CONFIG_SYS_CSPR3\t\tCONFIG_SYS_FPGA_CSPR\n+#define CONFIG_SYS_CSPR3_FINAL\t\tCONFIG_SYS_FPGA_CSPR_FINAL\n+#define CONFIG_SYS_AMASK3\t\tCONFIG_SYS_FPGA_AMASK\n+#define CONFIG_SYS_CSOR3\t\tCONFIG_SYS_FPGA_CSOR\n+#define CONFIG_SYS_CS3_FTIM0\t\tCONFIG_SYS_FPGA_CS_FTIM0\n+#define CONFIG_SYS_CS3_FTIM1\t\tCONFIG_SYS_FPGA_CS_FTIM1\n+#define CONFIG_SYS_CS3_FTIM2\t\tCONFIG_SYS_FPGA_CS_FTIM2\n+#define CONFIG_SYS_CS3_FTIM3\t\tCONFIG_SYS_FPGA_CS_FTIM3\n+#endif\n+\n+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000\n+\n+/*\n+ * I2C bus multiplexer\n+ */\n+#define I2C_MUX_PCA_ADDR_PRI\t\t0x77\n+#define I2C_MUX_PCA_ADDR_SEC\t\t0x76 /* Secondary multiplexer */\n+#define I2C_RETIMER_ADDR\t\t0x18\n+#define I2C_RETIMER_ADDR2\t\t0x19\n+#define I2C_MUX_CH_DEFAULT\t\t0x8\n+#define I2C_MUX_CH5\t\t\t0xD\n+\n+/*\n+* RTC configuration\n+*/\n+#define RTC\n+#define CONFIG_RTC_PCF8563 1\n+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/\n+#define CONFIG_CMD_DATE\n+\n+/* EEPROM */\n+#define CONFIG_ID_EEPROM\n+#define CONFIG_SYS_I2C_EEPROM_NXID\n+#define CONFIG_SYS_EEPROM_BUS_NUM\t\t0\n+#define CONFIG_SYS_I2C_EEPROM_ADDR\t\t0x57\n+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN\t\t1\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS\t3\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS\t5\n+\n+/* QSPI device */\n+#if defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_FSL_QSPI\n+#define CONFIG_SPI_FLASH_SPANSION\n+#define FSL_QSPI_FLASH_SIZE\t\t(1 << 26)\n+#define FSL_QSPI_FLASH_NUM\t\t2\n+\n+#endif\n+\n+#ifdef CONFIG_FSL_DSPI\n+#define CONFIG_SPI_FLASH_STMICRO\n+#define CONFIG_SPI_FLASH_SST\n+#define CONFIG_SPI_FLASH_EON\n+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)\n+#define CONFIG_SF_DEFAULT_BUS\t\t1\n+#define CONFIG_SF_DEFAULT_CS\t\t0\n+#endif\n+#endif\n+\n+#define CONFIG_CMD_MEMINFO\n+#define CONFIG_CMD_MEMTEST\n+#define CONFIG_SYS_MEMTEST_START\t0x80000000\n+#define CONFIG_SYS_MEMTEST_END\t\t0x9fffffff\n+\n+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE\n+\n+#define CONFIG_FSL_MEMAC\n+\n+/*  MMC  */\n+#define CONFIG_FSL_ESDHC\n+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33\n+#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \\\n+\tQIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)\n+\n+/* Initial environment variables */\n+#if defined(CONFIG_QSPI_BOOT)\n+#undef CONFIG_EXTRA_ENV_SETTINGS\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\n+\t\"hwconfig=fsl_ddr:bank_intlv=auto\\0\"\t\\\n+\t\"loadaddr=0x90100000\\0\"\t\t\t\\\n+\t\"kernel_addr=0x100000\\0\"\t\t\\\n+\t\"ramdisk_addr=0x800000\\0\"\t\t\\\n+\t\"ramdisk_size=0x2000000\\0\"\t\t\\\n+\t\"fdt_high=0xa0000000\\0\"\t\t\t\\\n+\t\"initrd_high=0xffffffffffffffff\\0\"\t\\\n+\t\"kernel_start=0x1000000\\0\"\t\t\\\n+\t\"kernel_load=0xa0000000\\0\"\t\t\\\n+\t\"kernel_size=0x2800000\\0\"\t\t\\\n+\t\"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;\"\t\\\n+\t\"sf read 0x80100000 0xE00000 0x100000;\" \\\n+\t\"fsl_mc start mc 0x80000000 0x80100000\\0\"\t\\\n+\t\"mcmemsize=0x70000000 \\0\"\n+#else\t/* NOR BOOT */\n+#undef CONFIG_EXTRA_ENV_SETTINGS\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\n+\t\"hwconfig=fsl_ddr:bank_intlv=auto\\0\"\t\\\n+\t\"loadaddr=0x90100000\\0\"\t\t\t\\\n+\t\"kernel_addr=0x100000\\0\"\t\t\\\n+\t\"ramdisk_addr=0x800000\\0\"\t\t\\\n+\t\"ramdisk_size=0x2000000\\0\"\t\t\\\n+\t\"fdt_high=0xa0000000\\0\"\t\t\t\\\n+\t\"initrd_high=0xffffffffffffffff\\0\"\t\\\n+\t\"kernel_start=0x1000000\\0\"\t\t\\\n+\t\"kernel_load=0xa0000000\\0\"\t\t\\\n+\t\"kernel_size=0x2800000\\0\"\t\t\\\n+\t\"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\\0\"\t\\\n+\t\"mcmemsize=0x70000000 \\0\"\n+#endif\n+\n+#ifdef CONFIG_FSL_MC_ENET\n+#define CONFIG_FSL_MEMAC\n+#define\tCONFIG_PHYLIB\n+#define CONFIG_PHYLIB_10G\n+#define CONFIG_PHY_VITESSE\n+#define CONFIG_PHY_REALTEK\n+#define CONFIG_PHY_TERANETICS\n+#define RGMII_PHY1_ADDR\t\t0x1\n+#define RGMII_PHY2_ADDR\t\t0x2\n+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C\n+#define SGMII_CARD_PORT2_PHY_ADDR 0x1d\n+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E\n+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F\n+\n+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0\n+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1\n+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2\n+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3\n+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4\n+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5\n+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6\n+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7\n+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8\n+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9\n+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa\n+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb\n+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc\n+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd\n+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe\n+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf\n+\n+#define CONFIG_MII\t\t/* MII PHY management */\n+#define CONFIG_ETHPRIME\t\t\"DPMAC1@xgmii\"\n+#define CONFIG_PHY_GIGE\t\t/* Include GbE speed/duplex detection */\n+\n+#endif\n+\n+#undef CONFIG_CMDLINE_EDITING\n+#include <config_distro_defaults.h>\n+#define BOOT_TARGET_DEVICES(func) \\\n+\tfunc(USB, usb, 0) \\\n+\tfunc(MMC, mmc, 0) \\\n+\tfunc(SCSI, scsi, 0) \\\n+\tfunc(DHCP, dhcp, na)\n+#include <config_distro_bootcmd.h>\n+\n+#include <asm/fsl_secure_boot.h>\n+\n+#endif /* __LS1088A_QDS_H */\n",
    "prefixes": [
        "U-Boot",
        "v4",
        "3/3"
    ]
}