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{
    "id": 803038,
    "url": "http://patchwork.ozlabs.org/api/patches/803038/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1503033876-23379-2-git-send-email-Ashish.Kumar@nxp.com/",
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    "msgid": "<1503033876-23379-2-git-send-email-Ashish.Kumar@nxp.com>",
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    "date": "2017-08-18T05:24:36",
    "name": "[U-Boot] armv8: fsl-lsch3: Make CCN-504 related code conditional",
    "commit_ref": "c055cee1951a01a3306f54f20bcfb85adf28721a",
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    "hash": "24d141bf7c914e7259b38bea97b2262e03190475",
    "submitter": {
        "id": 68053,
        "url": "http://patchwork.ozlabs.org/api/people/68053/?format=api",
        "name": "Ashish Kumar",
        "email": "Ashish.kumar@nxp.com"
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    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/803038/comments/",
    "check": "pending",
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    "tags": {},
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        "From": "Ashish Kumar <Ashish.Kumar@nxp.com>",
        "To": "<u-boot@lists.denx.de>",
        "Date": "Fri, 18 Aug 2017 10:54:36 +0530",
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        "Subject": "[U-Boot] [PATCH] armv8: fsl-lsch3: Make CCN-504 related code\n\tconditional",
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    },
    "content": "LS2080 family has CCN-504 cache coherent interconnet.\nOther SoCs from LSCH3 may have differnt interconnect like\nLS1088.\n\nSigned-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>\nSigned-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>\n---\nFor clean git am this \"http://patchwork.ozlabs.org/patch/800408/\"\nshould be applied first\n\n README                                       | 4 ++++\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig    | 4 ++++\n arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 8 +++++---\n 3 files changed, 13 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/README b/README\nindex a66a7ae..585e285 100644\n--- a/README\n+++ b/README\n@@ -322,6 +322,10 @@ build a config tool - later.\n \t\tDefined For SoC that has cache coherent interconnect\n \t\tCCN-400\n \n+\t\tCONFIG_SYS_FSL_HAS_CCN504\n+\n+\t\tDefined for SoC that has cache coherent interconnect CCN-504\n+\n The following options need to be configured:\n \n - CPU Type:\tDefine exactly one, e.g. CONFIG_MPC85XX.\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex 1132969..bb69ca6 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -60,6 +60,7 @@ config ARCH_LS2080A\n \tselect SYS_FSL_DDR\n \tselect SYS_FSL_DDR_LE\n \tselect SYS_FSL_DDR_VER_50\n+\tselect SYS_FSL_HAS_CCN504\n \tselect SYS_FSL_HAS_DP_DDR\n \tselect SYS_FSL_HAS_SEC\n \tselect SYS_FSL_HAS_DDR4\n@@ -267,6 +268,9 @@ config SYS_FSL_IFC_BANK_COUNT\n config SYS_FSL_HAS_CCI400\n \tbool\n \n+config SYS_FSL_HAS_CCN504\n+\tbool\n+\n config SYS_FSL_HAS_DP_DDR\n \tbool\n \ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S\nindex 3136e3f..5ff01a0 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S\n@@ -76,7 +76,7 @@ ENTRY(lowlevel_init)\n \tswitch_el x1, 1f, 100f, 100f\t/* skip if not in EL3 */\n 1:\n \n-#ifdef CONFIG_FSL_LSCH3\n+#if defined (CONFIG_SYS_FSL_HAS_CCN504)\n \n \t/* Set Wuo bit for RN-I 20 */\n #ifdef CONFIG_ARCH_LS2080A\n@@ -171,7 +171,7 @@ ENTRY(lowlevel_init)\n \tldr\tx0, =CCI_S2_QOS_CONTROL_BASE(20)\n \tldr\tx1, =0x00FF000C\n \tbl\tccn504_set_qos\n-#endif\n+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */\n \n #ifdef SMMU_BASE\n \t/* Set the SMMU page size in the sACR register */\n@@ -338,7 +338,9 @@ get_svr:\n \tldr\tx1, =FSL_LSCH3_SVR\n \tldr\tw0, [x1]\n \tret\n+#endif\n \n+#ifdef CONFIG_SYS_FSL_HAS_CCN504\n hnf_pstate_poll:\n \t/* x0 has the desired status, return 0 for success, 1 for timeout\n \t * clobber x1, x2, x3, x4, x6, x7\n@@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache)\n \tmov\tlr, x29\n \tret\n ENDPROC(__asm_flush_l3_dcache)\n-#endif\n+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */\n \n #ifdef CONFIG_MP\n \t/* Keep literals not used by the secondary boot code outside it */\n",
    "prefixes": [
        "U-Boot"
    ]
}