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{
    "id": 802400,
    "url": "http://patchwork.ozlabs.org/api/patches/802400/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-6-git-send-email-ran.wang_1@nxp.com/",
    "project": {
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        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
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    "msgid": "<1502955089-2049-6-git-send-email-ran.wang_1@nxp.com>",
    "list_archive_url": null,
    "date": "2017-08-17T07:31:27",
    "name": "[U-Boot,v3,6/8] armv7: Add workaround for USB erratum A-009798",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "601729e7bb68544144172ba2a2cef848afc2ad49",
    "submitter": {
        "id": 71939,
        "url": "http://patchwork.ozlabs.org/api/people/71939/?format=api",
        "name": "Ran Wang",
        "email": "ran.wang_1@nxp.com"
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        "username": "yorksun",
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    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-6-git-send-email-ran.wang_1@nxp.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/802400/comments/",
    "check": "pending",
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    "tags": {},
    "related": [],
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        "From": "Ran Wang <ran.wang_1@nxp.com>",
        "To": "open list <u-boot@lists.denx.de>, Albert Aribaud\n\t<albert.u.boot@aribaud.net>, York Sun <york.sun@nxp.com>, Suresh Gupta\n\t<suresh.bhagat@nxp.com>, Sriram Dash <sriram.dash@nxp.com>",
        "Date": "Thu, 17 Aug 2017 15:31:27 +0800",
        "Message-ID": "<1502955089-2049-6-git-send-email-ran.wang_1@nxp.com>",
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        "Cc": "Priyanka Jain <priyanka.jain@nxp.com>, ran.wang_1@nxp.com",
        "Subject": "[U-Boot] [PATCH v3 6/8] armv7: Add workaround for USB erratum\n\tA-009798",
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        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>"
    },
    "content": "The default setting for USB High Speed Squelch Threshold results\nin a threshold close to or lower than 100mV. This leads to Receive\nCompliance test failure for a 100mV threshold.\n\nThe changes shift the threshold from ~100mV towards ~130mV resulting\nin passing of USB High Speed Receiver Sensitivity Compliance test.\n\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Suresh Gupta <suresh.gupta@nxp.com>\nSigned-off-by: Ran Wang <ran.wang_1@nxp.com>\n---\nChange in v3:\n- none\n\nChange in v2:\n\tIn function erratum_a009798():\n\t1.Put a blank line after variable declaration.\n\n arch/arm/cpu/armv7/ls102xa/Kconfig                |  8 +++++++-\n arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +\n 3 files changed, 18 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig\nindex 96e9782..609333e 100644\n--- a/arch/arm/cpu/armv7/ls102xa/Kconfig\n+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig\n@@ -6,6 +6,7 @@ config ARCH_LS1021A\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010315\n \tselect SYS_FSL_ERRATUM_A009008\n+\tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_SRDS_1\n \tselect SYS_HAS_SERDES\n \tselect SYS_FSL_DDR_BE if SYS_FSL_DDR\n@@ -55,7 +56,12 @@ config SYS_FSL_ERRATUM_A010315\n config SYS_FSL_ERRATUM_A009008\n \tbool\n \thelp\n-\t\tWorkaround for USB erratum A009008\n+\t\tWorkaround for USB PHY erratum A009008\n+\n+config SYS_FSL_ERRATUM_A009798\n+\tbool\n+\thelp\n+\t\tWorkaround for USB PHY erratum A009798\n \n config SYS_FSL_SRDS_1\n \tbool\ndiff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c\nindex ac060bb..9401175 100644\n--- a/arch/arm/cpu/armv7/ls102xa/soc.c\n+++ b/arch/arm/cpu/armv7/ls102xa/soc.c\n@@ -71,6 +71,15 @@ static void erratum_a009008(void)\n #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */\n }\n \n+static void erratum_a009798(void)\n+{\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798\n+\tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+\tu32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);\n+\n+\tout_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */\n+}\n \n void s_init(void)\n {\n@@ -160,6 +169,7 @@ int arch_soc_init(void)\n \n \t/* Erratum */\n \terratum_a009008();\n+\terratum_a009798();\n \n \treturn 0;\n }\ndiff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex 6ea8c4b..8cafa07 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -176,6 +176,7 @@ struct ccsr_gur {\n #define SCFG_BASE\t\t\t0x01570000\n #define SCFG_USB3PRM1CR\t\t\t0x070\n #define USB_TXVREFTUNE\t\t\t0x9\n+#define USB_SQRXTUNE\t\t\t0xFC7FFFFF\n \n /* Supplemental Configuration Unit */\n struct ccsr_scfg {\n",
    "prefixes": [
        "U-Boot",
        "v3",
        "6/8"
    ]
}