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GET /api/patches/801850/?format=api
{ "id": 801850, "url": "http://patchwork.ozlabs.org/api/patches/801850/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1502882010-27829-1-git-send-email-sumit.garg@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1502882010-27829-1-git-send-email-sumit.garg@nxp.com>", "list_archive_url": null, "date": "2017-08-16T11:13:28", "name": "[U-Boot,v3,1/3] SECURE_BOOT: Unify memory map for Layerscape based platforms", "commit_ref": "06fb06f66c57912b53bda9fd1772d5d069433cbd", "pull_url": null, "state": "accepted", "archived": false, "hash": "b10c8319bf5f2d69d62bf2890c3c5d4a4e8de9dd", "submitter": { "id": 68653, "url": "http://patchwork.ozlabs.org/api/people/68653/?format=api", "name": "Sumit Garg", "email": "sumit.garg@nxp.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1502882010-27829-1-git-send-email-sumit.garg@nxp.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/801850/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/801850/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Tue, 15 Aug 2017 21:44:59 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tDATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4,\n\tRCVD_IN_MSPIKE_WL, \n\tSPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Sumit Garg <sumit.garg@nxp.com>", "To": "<u-boot@lists.denx.de>", "Date": "Wed, 16 Aug 2017 07:13:28 -0400", "Message-ID": "<1502882010-27829-1-git-send-email-sumit.garg@nxp.com>", "X-Mailer": "git-send-email 1.8.1.4", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131473323024872394;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; IPV:NLI; CTRY:US; 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BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(2017052603031)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:CY4PR03MB3318; ", "X-MS-TrafficTypeDiagnostic": "CY4PR03MB3318:", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197);", "X-Microsoft-Antispam-PRVS": "<CY4PR03MB3318B3AF7C1209D2784E643F98820@CY4PR03MB3318.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(601004)(2401047)(13018025)(8121501046)(13016025)(5005006)(100000703101)(100105400095)(93006095)(93001095)(10201501046)(3002001)(6055026)(6096035)(20161123563025)(20161123565025)(20161123561025)(201703131430075)(201703131433075)(201703131441075)(201703131448075)(201703161259150)(20161123556025)(20161123559100)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:CY4PR03MB3318; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY4PR03MB3318; ", "X-Forefront-PRVS": "0401647B7F", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Aug 2017 04:45:02.2064\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR03MB3318", "Cc": "ruchika.gupta@nxp.com", "Subject": "[U-Boot] [PATCH v3 1/3] SECURE_BOOT: Unify memory map for\n\tLayerscape based platforms", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Unify memory map for Layerscape based platforms. This patch includes\nchanges in bootscript, bootscript header and PPA header addresses\nchange as per unified memory map.\n\nSigned-off-by: Sumit Garg <sumit.garg@nxp.com>\nTested-by: Vinitha Pillai <vinitha.pillai@nxp.com>\n---\n\nChanges in v3:\nRebasing of the patch on top commit.\nThis patch supersedes https://patchwork.ozlabs.org/patch/756260/\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 +++----\n arch/arm/include/asm/fsl_secure_boot.h | 54 +++++++++++++------------------\n 2 files changed, 28 insertions(+), 38 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex 5825f9b..b7549a0 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -194,12 +194,12 @@ config SYS_LS_PPA_FW_ADDR\n config SYS_LS_PPA_ESBC_ADDR\n \thex \"hdr address of PPA firmware loading from\"\n \tdepends on FSL_LS_PPA && CHAIN_OF_TRUST\n-\tdefault 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A\n-\tdefault 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A\n-\tdefault 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A\n-\tdefault 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3\n-\tdefault 0x700000 if SYS_LS_PPA_FW_IN_MMC\n-\tdefault 0x700000 if SYS_LS_PPA_FW_IN_NAND\n+\tdefault 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A\n+\tdefault 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A\n+\tdefault 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A\n+\tdefault 0x580680000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3\n+\tdefault 0x680000 if SYS_LS_PPA_FW_IN_MMC\n+\tdefault 0x680000 if SYS_LS_PPA_FW_IN_NAND\n \thelp\n \t If the PPA header firmware locate at XIP flash, such as NOR or\n \t QSPI flash, this address is a directly memory-mapped.\ndiff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h\nindex b0b3b93..63845a2 100644\n--- a/arch/arm/include/asm/fsl_secure_boot.h\n+++ b/arch/arm/include/asm/fsl_secure_boot.h\n@@ -1,5 +1,6 @@\n /*\n * Copyright 2015 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n@@ -71,55 +72,44 @@\n * DDR memory map\n */\n #ifdef CONFIG_FSL_LSCH3\n-#define CONFIG_BS_HDR_ADDR_DEVICE\t0x580d00000\n-#define CONFIG_BS_ADDR_DEVICE\t\t0x580e00000\n-#define CONFIG_BS_HDR_ADDR_RAM\t\t0xa0d00000\n-#define CONFIG_BS_ADDR_RAM\t\t0xa0e00000\n-#define CONFIG_BS_HDR_SIZE\t\t0x00002000\n+#define CONFIG_BS_ADDR_DEVICE\t\t0x580600000\n+#define CONFIG_BS_HDR_ADDR_DEVICE\t0x580640000\n #define CONFIG_BS_SIZE\t\t\t0x00001000\n+#define CONFIG_BS_HDR_SIZE\t\t0x00004000\n+#define CONFIG_BS_ADDR_RAM\t\t0xa0600000\n+#define CONFIG_BS_HDR_ADDR_RAM\t\t0xa0640000\n #else\n #ifdef CONFIG_SD_BOOT\n /* For SD boot address and size are assigned in terms of sector\n * offset and no. of sectors respectively.\n */\n-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n-#define CONFIG_BS_HDR_ADDR_DEVICE\t0x00000920\n-#else\n-#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900\n-#endif\n-#define CONFIG_BS_ADDR_DEVICE\t\t0x00000940\n-#define CONFIG_BS_HDR_SIZE\t\t0x00000010\n+#define CONFIG_BS_ADDR_DEVICE\t\t0x00003000\n+#define CONFIG_BS_HDR_ADDR_DEVICE\t0x00003200\n #define CONFIG_BS_SIZE\t\t\t0x00000008\n+#define CONFIG_BS_HDR_SIZE\t\t0x00000010\n #elif defined(CONFIG_NAND_BOOT)\n-#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000\n-#define CONFIG_BS_ADDR_DEVICE 0x00802000\n-#define CONFIG_BS_HDR_SIZE 0x00002000\n-#define CONFIG_BS_SIZE 0x00001000\n-#elif defined(CONFIG_QSPI_BOOT)\n-#ifdef CONFIG_ARCH_LS1046A\n-#define CONFIG_BS_HDR_ADDR_DEVICE\t0x40780000\n-#define CONFIG_BS_ADDR_DEVICE\t\t0x40800000\n-#elif defined(CONFIG_ARCH_LS1012A)\n-#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000\n-#define CONFIG_BS_ADDR_DEVICE 0x40060000\n-#else\n-#error \"Platform not supported\"\n-#endif\n+#define CONFIG_BS_ADDR_DEVICE\t\t0x00600000\n+#define CONFIG_BS_HDR_ADDR_DEVICE\t0x00640000\n+#define CONFIG_BS_SIZE\t\t\t0x00001000\n #define CONFIG_BS_HDR_SIZE\t\t0x00002000\n+#elif defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_BS_ADDR_DEVICE\t\t0x40600000\n+#define CONFIG_BS_HDR_ADDR_DEVICE\t0x40640000\n #define CONFIG_BS_SIZE\t\t\t0x00001000\n-#else /* Default NOR Boot */\n-#define CONFIG_BS_HDR_ADDR_DEVICE\t0x600a0000\n-#define CONFIG_BS_ADDR_DEVICE\t\t0x60060000\n #define CONFIG_BS_HDR_SIZE\t\t0x00002000\n+#else /* Default NOR Boot */\n+#define CONFIG_BS_ADDR_DEVICE\t\t0x60600000\n+#define CONFIG_BS_HDR_ADDR_DEVICE\t0x60640000\n #define CONFIG_BS_SIZE\t\t\t0x00001000\n+#define CONFIG_BS_HDR_SIZE\t\t0x00002000\n #endif\n-#define CONFIG_BS_HDR_ADDR_RAM\t\t0x81000000\n-#define CONFIG_BS_ADDR_RAM\t\t0x81020000\n+#define CONFIG_BS_ADDR_RAM\t\t0x81000000\n+#define CONFIG_BS_HDR_ADDR_RAM\t\t0x81020000\n #endif\n \n #ifdef CONFIG_BOOTSCRIPT_COPY_RAM\n-#define CONFIG_BOOTSCRIPT_HDR_ADDR\tCONFIG_BS_HDR_ADDR_RAM\n #define CONFIG_BOOTSCRIPT_ADDR\t\tCONFIG_BS_ADDR_RAM\n+#define CONFIG_BOOTSCRIPT_HDR_ADDR\tCONFIG_BS_HDR_ADDR_RAM\n #else\n #define CONFIG_BOOTSCRIPT_HDR_ADDR\tCONFIG_BS_HDR_ADDR_DEVICE\n /* BOOTSCRIPT_ADDR is not required */\n", "prefixes": [ "U-Boot", "v3", "1/3" ] }