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GET /api/patches/801005/?format=api
{ "id": 801005, "url": "http://patchwork.ozlabs.org/api/patches/801005/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20170813142117.3977-1-wsa@the-dreams.de/", "project": { "id": 35, "url": "http://patchwork.ozlabs.org/api/projects/35/?format=api", "name": "Linux I2C development", "link_name": "linux-i2c", "list_id": "linux-i2c.vger.kernel.org", "list_email": "linux-i2c@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170813142117.3977-1-wsa@the-dreams.de>", "list_archive_url": null, "date": "2017-08-13T14:21:17", "name": "[RESEND] blackfin: merge the two TWI header files", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "b962eb1900de997a05566927dbef5f7469bd714c", "submitter": { "id": 22495, "url": "http://patchwork.ozlabs.org/api/people/22495/?format=api", "name": "Wolfram Sang", "email": "wsa@the-dreams.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20170813142117.3977-1-wsa@the-dreams.de/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/801005/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/801005/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-i2c-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-i2c-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xVgsQ2QYnz9sQl\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 14 Aug 2017 00:21:30 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750974AbdHMOV2 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tSun, 13 Aug 2017 10:21:28 -0400", "from sauhun.de ([88.99.104.3]:46515 \"EHLO pokefinder.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750907AbdHMOV0 (ORCPT <rfc822;linux-i2c@vger.kernel.org>);\n\tSun, 13 Aug 2017 10:21:26 -0400", "from localhost (p54B33788.dip0.t-ipconnect.de [84.179.55.136])\n\tby pokefinder.org (Postfix) with ESMTPSA id 5F0252C3188;\n\tSun, 13 Aug 2017 16:21:25 +0200 (CEST)" ], "From": "Wolfram Sang <wsa@the-dreams.de>", "To": "adi-buildroot-devel@lists.sourceforge.net", "Cc": "Wolfram Sang <wsa@the-dreams.de>, Steven Miao <realmz6@gmail.com>,\n\tSonic Zhang <sonic.zhang@analog.com>,\n\tlinux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org", "Subject": "[PATCH RESEND] blackfin: merge the two TWI header files", "Date": "Sun, 13 Aug 2017 16:21:17 +0200", "Message-Id": "<20170813142117.3977-1-wsa@the-dreams.de>", "X-Mailer": "git-send-email 2.11.0", "Sender": "linux-i2c-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-i2c.vger.kernel.org>", "X-Mailing-List": "linux-i2c@vger.kernel.org" }, "content": "There seems to be no need for separate ones since all users include both\nfiles anyhow. Merge them because include/linux/i2c is to be deprecated.\n\nSigned-off-by: Wolfram Sang <wsa@the-dreams.de>\n---\n\nReseding, rebased on v4.13-rc4. Now subscribed to the adi-ML as well.\nI'd prefer if this goes via the ADI tree but I can pick it, too, if desired.\n\n arch/blackfin/include/asm/bfin_twi.h | 134 +++++++++++++++++++++++++++++++-\n arch/blackfin/kernel/debug-mmrs.c | 1 -\n drivers/i2c/busses/i2c-bfin-twi.c | 1 -\n include/linux/i2c/bfin_twi.h | 145 -----------------------------------\n 4 files changed, 133 insertions(+), 148 deletions(-)\n delete mode 100644 include/linux/i2c/bfin_twi.h", "diff": "diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h\nindex aaa0834d34aa7e..211e9c78f6fb89 100644\n--- a/arch/blackfin/include/asm/bfin_twi.h\n+++ b/arch/blackfin/include/asm/bfin_twi.h\n@@ -1,7 +1,7 @@\n /*\n * bfin_twi.h - interface to Blackfin TWIs\n *\n- * Copyright 2005-2010 Analog Devices Inc.\n+ * Copyright 2005-2014 Analog Devices Inc.\n *\n * Licensed under the GPL-2 or later.\n */\n@@ -10,6 +10,138 @@\n #define __ASM_BFIN_TWI_H__\n \n #include <asm/blackfin.h>\n+#include <linux/types.h>\n+#include <linux/i2c.h>\n+\n+/*\n+ * ADI twi registers layout\n+ */\n+struct bfin_twi_regs {\n+\tu16 clkdiv;\n+\tu16 dummy1;\n+\tu16 control;\n+\tu16 dummy2;\n+\tu16 slave_ctl;\n+\tu16 dummy3;\n+\tu16 slave_stat;\n+\tu16 dummy4;\n+\tu16 slave_addr;\n+\tu16 dummy5;\n+\tu16 master_ctl;\n+\tu16 dummy6;\n+\tu16 master_stat;\n+\tu16 dummy7;\n+\tu16 master_addr;\n+\tu16 dummy8;\n+\tu16 int_stat;\n+\tu16 dummy9;\n+\tu16 int_mask;\n+\tu16 dummy10;\n+\tu16 fifo_ctl;\n+\tu16 dummy11;\n+\tu16 fifo_stat;\n+\tu16 dummy12;\n+\tu32 __pad[20];\n+\tu16 xmt_data8;\n+\tu16 dummy13;\n+\tu16 xmt_data16;\n+\tu16 dummy14;\n+\tu16 rcv_data8;\n+\tu16 dummy15;\n+\tu16 rcv_data16;\n+\tu16 dummy16;\n+};\n+\n+struct bfin_twi_iface {\n+\tint\t\t\tirq;\n+\tspinlock_t\t\tlock;\n+\tchar\t\t\tread_write;\n+\tu8\t\t\tcommand;\n+\tu8\t\t\t*transPtr;\n+\tint\t\t\treadNum;\n+\tint\t\t\twriteNum;\n+\tint\t\t\tcur_mode;\n+\tint\t\t\tmanual_stop;\n+\tint\t\t\tresult;\n+\tstruct i2c_adapter\tadap;\n+\tstruct completion\tcomplete;\n+\tstruct i2c_msg\t\t*pmsg;\n+\tint\t\t\tmsg_num;\n+\tint\t\t\tcur_msg;\n+\tu16\t\t\tsaved_clkdiv;\n+\tu16\t\t\tsaved_control;\n+\tstruct bfin_twi_regs __iomem *regs_base;\n+};\n+\n+/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/\n+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */\n+#define\tCLKLOW(x)\t((x) & 0xFF)\t/* Periods Clock Is Held Low */\n+#define CLKHI(y)\t(((y)&0xFF)<<0x8) /* Periods Before New Clock Low */\n+\n+/* TWI_PRESCALE Masks */\n+#define\tPRESCALE\t0x007F\t/* SCLKs Per Internal Time Reference (10MHz) */\n+#define\tTWI_ENA\t\t0x0080\t/* TWI Enable */\n+#define\tSCCB\t\t0x0200\t/* SCCB Compatibility Enable */\n+\n+/* TWI_SLAVE_CTL Masks */\n+#define\tSEN\t\t0x0001\t/* Slave Enable */\n+#define\tSADD_LEN\t0x0002\t/* Slave Address Length */\n+#define\tSTDVAL\t\t0x0004\t/* Slave Transmit Data Valid */\n+#define\tNAK\t\t0x0008\t/* NAK Generated At Conclusion Of Transfer */\n+#define\tGEN\t\t0x0010\t/* General Call Address Matching Enabled */\n+\n+/* TWI_SLAVE_STAT Masks\t*/\n+#define\tSDIR\t\t0x0001\t/* Slave Transfer Direction (RX/TX*) */\n+#define GCALL\t\t0x0002\t/* General Call Indicator */\n+\n+/* TWI_MASTER_CTL Masks\t*/\n+#define\tMEN\t\t0x0001\t/* Master Mode Enable */\n+#define\tMADD_LEN\t0x0002\t/* Master Address Length */\n+#define\tMDIR\t\t0x0004\t/* Master Transmit Direction (RX/TX*) */\n+#define\tFAST\t\t0x0008\t/* Use Fast Mode Timing Specs */\n+#define\tSTOP\t\t0x0010\t/* Issue Stop Condition */\n+#define\tRSTART\t\t0x0020\t/* Repeat Start or Stop* At End Of Transfer */\n+#define\tDCNT\t\t0x3FC0\t/* Data Bytes To Transfer */\n+#define\tSDAOVR\t\t0x4000\t/* Serial Data Override */\n+#define\tSCLOVR\t\t0x8000\t/* Serial Clock Override */\n+\n+/* TWI_MASTER_STAT Masks */\n+#define\tMPROG\t\t0x0001\t/* Master Transfer In Progress */\n+#define\tLOSTARB\t\t0x0002\t/* Lost Arbitration Indicator (Xfer Aborted) */\n+#define\tANAK\t\t0x0004\t/* Address Not Acknowledged */\n+#define\tDNAK\t\t0x0008\t/* Data Not Acknowledged */\n+#define\tBUFRDERR\t0x0010\t/* Buffer Read Error */\n+#define\tBUFWRERR\t0x0020\t/* Buffer Write Error */\n+#define\tSDASEN\t\t0x0040\t/* Serial Data Sense */\n+#define\tSCLSEN\t\t0x0080\t/* Serial Clock Sense */\n+#define\tBUSBUSY\t\t0x0100\t/* Bus Busy Indicator */\n+\n+/* TWI_INT_SRC and TWI_INT_ENABLE Masks\t*/\n+#define\tSINIT\t\t0x0001\t/* Slave Transfer Initiated */\n+#define\tSCOMP\t\t0x0002\t/* Slave Transfer Complete */\n+#define\tSERR\t\t0x0004\t/* Slave Transfer Error */\n+#define\tSOVF\t\t0x0008\t/* Slave Overflow */\n+#define\tMCOMP\t\t0x0010\t/* Master Transfer Complete */\n+#define\tMERR\t\t0x0020\t/* Master Transfer Error */\n+#define\tXMTSERV\t\t0x0040\t/* Transmit FIFO Service */\n+#define\tRCVSERV\t\t0x0080\t/* Receive FIFO Service */\n+\n+/* TWI_FIFO_CTRL Masks */\n+#define\tXMTFLUSH\t0x0001\t/* Transmit Buffer Flush */\n+#define\tRCVFLUSH\t0x0002\t/* Receive Buffer Flush */\n+#define\tXMTINTLEN\t0x0004\t/* Transmit Buffer Interrupt Length */\n+#define\tRCVINTLEN\t0x0008\t/* Receive Buffer Interrupt Length */\n+\n+/* TWI_FIFO_STAT Masks */\n+#define\tXMTSTAT\t\t0x0003\t/* Transmit FIFO Status */\n+#define\tXMT_EMPTY\t0x0000\t/* Transmit FIFO Empty */\n+#define\tXMT_HALF\t0x0001\t/* Transmit FIFO Has 1 Byte To Write */\n+#define\tXMT_FULL\t0x0003\t/* Transmit FIFO Full (2 Bytes To Write) */\n+\n+#define\tRCVSTAT\t\t0x000C\t/* Receive FIFO Status */\n+#define\tRCV_EMPTY\t0x0000\t/* Receive FIFO Empty */\n+#define\tRCV_HALF\t0x0004\t/* Receive FIFO Has 1 Byte To Read */\n+#define\tRCV_FULL\t0x000C\t/* Receive FIFO Full (2 Bytes To Read) */\n \n #define DEFINE_TWI_REG(reg_name, reg) \\\n static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \\\ndiff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c\nindex e272bca93c648f..f31ace221392c4 100644\n--- a/arch/blackfin/kernel/debug-mmrs.c\n+++ b/arch/blackfin/kernel/debug-mmrs.c\n@@ -10,7 +10,6 @@\n #include <linux/fs.h>\n #include <linux/kernel.h>\n #include <linux/module.h>\n-#include <linux/i2c/bfin_twi.h>\n #include <linux/gpio.h>\n \n #include <asm/blackfin.h>\ndiff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c\nindex 9fe942b8c61047..ff3343186a8295 100644\n--- a/drivers/i2c/busses/i2c-bfin-twi.c\n+++ b/drivers/i2c/busses/i2c-bfin-twi.c\n@@ -21,7 +21,6 @@\n #include <linux/interrupt.h>\n #include <linux/platform_device.h>\n #include <linux/delay.h>\n-#include <linux/i2c/bfin_twi.h>\n \n #include <asm/irq.h>\n #include <asm/portmux.h>\ndiff --git a/include/linux/i2c/bfin_twi.h b/include/linux/i2c/bfin_twi.h\ndeleted file mode 100644\nindex 135a4e0876aeba..00000000000000\n--- a/include/linux/i2c/bfin_twi.h\n+++ /dev/null\n@@ -1,145 +0,0 @@\n-/*\n- * i2c-bfin-twi.h - interface to ADI TWI controller\n- *\n- * Copyright 2005-2014 Analog Devices Inc.\n- *\n- * Licensed under the GPL-2 or later.\n- */\n-\n-#ifndef __I2C_BFIN_TWI_H__\n-#define __I2C_BFIN_TWI_H__\n-\n-#include <linux/types.h>\n-#include <linux/i2c.h>\n-\n-/*\n- * ADI twi registers layout\n- */\n-struct bfin_twi_regs {\n-\tu16 clkdiv;\n-\tu16 dummy1;\n-\tu16 control;\n-\tu16 dummy2;\n-\tu16 slave_ctl;\n-\tu16 dummy3;\n-\tu16 slave_stat;\n-\tu16 dummy4;\n-\tu16 slave_addr;\n-\tu16 dummy5;\n-\tu16 master_ctl;\n-\tu16 dummy6;\n-\tu16 master_stat;\n-\tu16 dummy7;\n-\tu16 master_addr;\n-\tu16 dummy8;\n-\tu16 int_stat;\n-\tu16 dummy9;\n-\tu16 int_mask;\n-\tu16 dummy10;\n-\tu16 fifo_ctl;\n-\tu16 dummy11;\n-\tu16 fifo_stat;\n-\tu16 dummy12;\n-\tu32 __pad[20];\n-\tu16 xmt_data8;\n-\tu16 dummy13;\n-\tu16 xmt_data16;\n-\tu16 dummy14;\n-\tu16 rcv_data8;\n-\tu16 dummy15;\n-\tu16 rcv_data16;\n-\tu16 dummy16;\n-};\n-\n-struct bfin_twi_iface {\n-\tint\t\t\tirq;\n-\tspinlock_t\t\tlock;\n-\tchar\t\t\tread_write;\n-\tu8\t\t\tcommand;\n-\tu8\t\t\t*transPtr;\n-\tint\t\t\treadNum;\n-\tint\t\t\twriteNum;\n-\tint\t\t\tcur_mode;\n-\tint\t\t\tmanual_stop;\n-\tint\t\t\tresult;\n-\tstruct i2c_adapter\tadap;\n-\tstruct completion\tcomplete;\n-\tstruct i2c_msg\t\t*pmsg;\n-\tint\t\t\tmsg_num;\n-\tint\t\t\tcur_msg;\n-\tu16\t\t\tsaved_clkdiv;\n-\tu16\t\t\tsaved_control;\n-\tstruct bfin_twi_regs __iomem *regs_base;\n-};\n-\n-/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/\n-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */\n-#define\tCLKLOW(x)\t((x) & 0xFF)\t/* Periods Clock Is Held Low */\n-#define CLKHI(y)\t(((y)&0xFF)<<0x8) /* Periods Before New Clock Low */\n-\n-/* TWI_PRESCALE Masks */\n-#define\tPRESCALE\t0x007F\t/* SCLKs Per Internal Time Reference (10MHz) */\n-#define\tTWI_ENA\t\t0x0080\t/* TWI Enable */\n-#define\tSCCB\t\t0x0200\t/* SCCB Compatibility Enable */\n-\n-/* TWI_SLAVE_CTL Masks */\n-#define\tSEN\t\t0x0001\t/* Slave Enable */\n-#define\tSADD_LEN\t0x0002\t/* Slave Address Length */\n-#define\tSTDVAL\t\t0x0004\t/* Slave Transmit Data Valid */\n-#define\tNAK\t\t0x0008\t/* NAK Generated At Conclusion Of Transfer */\n-#define\tGEN\t\t0x0010\t/* General Call Address Matching Enabled */\n-\n-/* TWI_SLAVE_STAT Masks\t*/\n-#define\tSDIR\t\t0x0001\t/* Slave Transfer Direction (RX/TX*) */\n-#define GCALL\t\t0x0002\t/* General Call Indicator */\n-\n-/* TWI_MASTER_CTL Masks\t*/\n-#define\tMEN\t\t0x0001\t/* Master Mode Enable */\n-#define\tMADD_LEN\t0x0002\t/* Master Address Length */\n-#define\tMDIR\t\t0x0004\t/* Master Transmit Direction (RX/TX*) */\n-#define\tFAST\t\t0x0008\t/* Use Fast Mode Timing Specs */\n-#define\tSTOP\t\t0x0010\t/* Issue Stop Condition */\n-#define\tRSTART\t\t0x0020\t/* Repeat Start or Stop* At End Of Transfer */\n-#define\tDCNT\t\t0x3FC0\t/* Data Bytes To Transfer */\n-#define\tSDAOVR\t\t0x4000\t/* Serial Data Override */\n-#define\tSCLOVR\t\t0x8000\t/* Serial Clock Override */\n-\n-/* TWI_MASTER_STAT Masks */\n-#define\tMPROG\t\t0x0001\t/* Master Transfer In Progress */\n-#define\tLOSTARB\t\t0x0002\t/* Lost Arbitration Indicator (Xfer Aborted) */\n-#define\tANAK\t\t0x0004\t/* Address Not Acknowledged */\n-#define\tDNAK\t\t0x0008\t/* Data Not Acknowledged */\n-#define\tBUFRDERR\t0x0010\t/* Buffer Read Error */\n-#define\tBUFWRERR\t0x0020\t/* Buffer Write Error */\n-#define\tSDASEN\t\t0x0040\t/* Serial Data Sense */\n-#define\tSCLSEN\t\t0x0080\t/* Serial Clock Sense */\n-#define\tBUSBUSY\t\t0x0100\t/* Bus Busy Indicator */\n-\n-/* TWI_INT_SRC and TWI_INT_ENABLE Masks\t*/\n-#define\tSINIT\t\t0x0001\t/* Slave Transfer Initiated */\n-#define\tSCOMP\t\t0x0002\t/* Slave Transfer Complete */\n-#define\tSERR\t\t0x0004\t/* Slave Transfer Error */\n-#define\tSOVF\t\t0x0008\t/* Slave Overflow */\n-#define\tMCOMP\t\t0x0010\t/* Master Transfer Complete */\n-#define\tMERR\t\t0x0020\t/* Master Transfer Error */\n-#define\tXMTSERV\t\t0x0040\t/* Transmit FIFO Service */\n-#define\tRCVSERV\t\t0x0080\t/* Receive FIFO Service */\n-\n-/* TWI_FIFO_CTRL Masks */\n-#define\tXMTFLUSH\t0x0001\t/* Transmit Buffer Flush */\n-#define\tRCVFLUSH\t0x0002\t/* Receive Buffer Flush */\n-#define\tXMTINTLEN\t0x0004\t/* Transmit Buffer Interrupt Length */\n-#define\tRCVINTLEN\t0x0008\t/* Receive Buffer Interrupt Length */\n-\n-/* TWI_FIFO_STAT Masks */\n-#define\tXMTSTAT\t\t0x0003\t/* Transmit FIFO Status */\n-#define\tXMT_EMPTY\t0x0000\t/* Transmit FIFO Empty */\n-#define\tXMT_HALF\t0x0001\t/* Transmit FIFO Has 1 Byte To Write */\n-#define\tXMT_FULL\t0x0003\t/* Transmit FIFO Full (2 Bytes To Write) */\n-\n-#define\tRCVSTAT\t\t0x000C\t/* Receive FIFO Status */\n-#define\tRCV_EMPTY\t0x0000\t/* Receive FIFO Empty */\n-#define\tRCV_HALF\t0x0004\t/* Receive FIFO Has 1 Byte To Read */\n-#define\tRCV_FULL\t0x000C\t/* Receive FIFO Full (2 Bytes To Read) */\n-\n-#endif\n", "prefixes": [ "RESEND" ] }