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GET /api/patches/800419/?format=api
{ "id": 800419, "url": "http://patchwork.ozlabs.org/api/patches/800419/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1502432577-5911-2-git-send-email-alistair@popple.id.au/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1502432577-5911-2-git-send-email-alistair@popple.id.au>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1502432577-5911-2-git-send-email-alistair@popple.id.au/", "date": "2017-08-11T06:22:57", "name": "[2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "61c127c32f5168e2f9c7244acd313a5cd2a306b7", "submitter": { "id": 24781, "url": "http://patchwork.ozlabs.org/api/people/24781/?format=api", "name": "Alistair Popple", "email": "alistair@popple.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1502432577-5911-2-git-send-email-alistair@popple.id.au/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/800419/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/800419/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xTFN91BRrz9t16\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 11 Aug 2017 16:24:41 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xTFN90KhwzDr5F\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 11 Aug 2017 16:24:41 +1000 (AEST)", "from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xTFM03G4GzDr44\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 11 Aug 2017 16:23:40 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xTFM00jVlz9t3x; Fri, 11 Aug 2017 16:23:40 +1000 (AEST)", "from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xTFM00HF8z9t3w;\n\tFri, 11 Aug 2017 16:23:40 +1000 (AEST)" ], "From": "Alistair Popple <alistair@popple.id.au>", "To": "mpe@ellerman.id.au", "Subject": "[PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb", "Date": "Fri, 11 Aug 2017 16:22:57 +1000", "Message-Id": "<1502432577-5911-2-git-send-email-alistair@popple.id.au>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1502432577-5911-1-git-send-email-alistair@popple.id.au>", "References": "<1502432577-5911-1-git-send-email-alistair@popple.id.au>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "linuxppc-dev@ozlabs.org, sbaskaran@nvidia.com, fbarrat@linux.vnet.ibm.com,\n\tarbab@linux.vnet.ibm.com, Alistair Popple <alistair@popple.id.au>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The nest mmu required an explicit flush as a tlbi would not flush it in the\nsame way as the core. However an alternate firmware fix exists which should\neliminate the need for this flush, so instead add a device-tree property\n(ibm,nmmu-flush) on the NVLink2 PHB to enable it only if required.\n\nSigned-off-by: Alistair Popple <alistair@popple.id.au>\n---\n\nMichael,\n\nThis patch depends on http://patchwork.ozlabs.org/patch/796775/ - [v3,1/3]\npowerpc/mm: Add marker for contexts requiring global TLB invalidations.\n\n- Alistair\n\n arch/powerpc/platforms/powernv/npu-dma.c | 27 +++++++++++++++++++++------\n arch/powerpc/platforms/powernv/pci.h | 3 +++\n 2 files changed, 24 insertions(+), 6 deletions(-)", "diff": "diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c\nindex 3d4f879..ac07800 100644\n--- a/arch/powerpc/platforms/powernv/npu-dma.c\n+++ b/arch/powerpc/platforms/powernv/npu-dma.c\n@@ -544,12 +544,7 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,\n \tstruct pci_dev *npdev;\n \tstruct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];\n \tunsigned long pid = npu_context->mm->context.id;\n-\n-\t/*\n-\t * Unfortunately the nest mmu does not support flushing specific\n-\t * addresses so we have to flush the whole mm.\n-\t */\n-\tflush_tlb_mm(npu_context->mm);\n+\tbool nmmu_flushed = false;\n \n \t/*\n \t * Loop over all the NPUs this process is active on and launch\n@@ -566,6 +561,17 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,\n \t\t\tnpu = &nphb->npu;\n \t\t\tmmio_atsd_reg[i].npu = npu;\n \n+\t\t\tif (nphb->npu.nmmu_flush && !nmmu_flushed) {\n+\t\t\t\t/*\n+\t\t\t\t * Unfortunately the nest mmu does not support\n+\t\t\t\t * flushing specific addresses so we have to\n+\t\t\t\t * flush the whole mm once before shooting down\n+\t\t\t\t * the GPU translation.\n+\t\t\t\t */\n+\t\t\t\tflush_tlb_mm(npu_context->mm);\n+\t\t\t\tnmmu_flushed = true;\n+\t\t\t}\n+\n \t\t\tif (va)\n \t\t\t\tmmio_atsd_reg[i].reg =\n \t\t\t\t\tmmio_invalidate_va(npu, address, pid,\n@@ -732,6 +738,13 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,\n \t\treturn ERR_PTR(-ENODEV);\n \tnpu_context->npdev[npu->index][nvlink_index] = npdev;\n \n+\tif (!nphb->npu.nmmu_flush)\n+\t\t/*\n+\t\t * If we're not explicitly flushing ourselves we need to mark\n+\t\t * the thread for global flushes\n+\t\t */\n+\t\tmm_context_set_global_tlbi(&mm->context);\n+\n \treturn npu_context;\n }\n EXPORT_SYMBOL(pnv_npu2_init_context);\n@@ -829,6 +842,8 @@ int pnv_npu2_init(struct pnv_phb *phb)\n \tstatic int npu_index;\n \tuint64_t rc = 0;\n \n+\tphb->npu.nmmu_flush =\n+\t\tof_property_read_bool(phb->hose->dn, \"ibm,nmmu-flush\");\n \tfor_each_child_of_node(phb->hose->dn, dn) {\n \t\tgpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));\n \t\tif (gpdev) {\ndiff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h\nindex f16bc40..e8e3e20 100644\n--- a/arch/powerpc/platforms/powernv/pci.h\n+++ b/arch/powerpc/platforms/powernv/pci.h\n@@ -184,6 +184,9 @@ struct pnv_phb {\n \n \t\t/* Bitmask for MMIO register usage */\n \t\tunsigned long mmio_atsd_usage;\n+\n+\t\t/* Do we need to explicitly flush the nest mmu? */\n+\t\tbool nmmu_flush;\n \t} npu;\n \n #ifdef CONFIG_CXL_BASE\n", "prefixes": [ "2/2" ] }