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{
    "id": 800410,
    "url": "http://patchwork.ozlabs.org/api/patches/800410/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1502429956-31604-2-git-send-email-Ashish.Kumar@nxp.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
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    "msgid": "<1502429956-31604-2-git-send-email-Ashish.Kumar@nxp.com>",
    "list_archive_url": null,
    "date": "2017-08-11T05:39:15",
    "name": "[U-Boot,v5,2/3] armv7: Consolidate registers space defination for CCI-400 bus",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "48154b6d17963b4bf7b5c39383750052fda3f947",
    "submitter": {
        "id": 68053,
        "url": "http://patchwork.ozlabs.org/api/people/68053/?format=api",
        "name": "Ashish Kumar",
        "email": "Ashish.kumar@nxp.com"
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        "username": "yorksun",
        "first_name": "York",
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        "email": "yorksun@freescale.com"
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    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1502429956-31604-2-git-send-email-Ashish.Kumar@nxp.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/800410/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/800410/checks/",
    "tags": {},
    "related": [],
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        "From": "Ashish Kumar <Ashish.Kumar@nxp.com>",
        "To": "<u-boot@lists.denx.de>",
        "Date": "Fri, 11 Aug 2017 11:09:15 +0530",
        "Message-ID": "<1502429956-31604-2-git-send-email-Ashish.Kumar@nxp.com>",
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        "Subject": "[U-Boot] [PATCH v5 2/3] armv7: Consolidate registers space\n\tdefination for CCI-400 bus",
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        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>"
    },
    "content": "CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which\nprovides full cache coherency between two clusters of multi-core\nCPUs and I/O coherency for devices and I/O masters.\n\nThis patch add new CONFIG defination \"FSL_SYS_HAS_CCI400\" and\nremoves register space definaton of CCI-400 bus from\nimmap_ls102xa to fsl_immap, since same is defined there already\n\n\"CONFIG_SYS_CCI400_ADDR\" is depricated and new SYS_CCI400_OFFSET\nis introduced in Kconfig\n\nSigned-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>\n---\nv3: \n This is v3 for https://patchwork.ozlabs.org/patch/731464/\nv4:\n No change\nv5:\n Moving ls1021aqds here\n\n arch/arm/cpu/armv7/ls102xa/Kconfig                | 12 ++++++\n arch/arm/cpu/armv7/ls102xa/soc.c                  |  3 +-\n arch/arm/include/asm/arch-ls102xa/config.h        |  1 -\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 49 +----------------------\n board/freescale/ls1021aqds/ls1021aqds.c           |  9 +++--\n 5 files changed, 22 insertions(+), 52 deletions(-)",
    "diff": "diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig\nindex 6a013b2..61dd522 100644\n--- a/arch/arm/cpu/armv7/ls102xa/Kconfig\n+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig\n@@ -5,6 +5,7 @@ config ARCH_LS1021A\n \tselect SYS_FSL_ERRATUM_A009663\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010315\n+\tselect SYS_FSL_HAS_CCI400\n \tselect SYS_FSL_SRDS_1\n \tselect SYS_HAS_SERDES\n \tselect SYS_FSL_DDR_BE if SYS_FSL_DDR\n@@ -48,9 +49,20 @@ config SECURE_BOOT\n \t\tEnable Freescale Secure Boot feature. Normally selected\n \t\tby defconfig. If unsure, do not change.\n \n+config SYS_CCI400_OFFSET\n+\thex \"Offset for CCI400 base\"\n+\tdepends on SYS_FSL_HAS_CCI400\n+\tdefault 0x180000\n+\thelp\n+\t  Offset for CCI400 base.\n+\t  CCI400 base addr = CCSRBAR + CCI400_OFFSET\n+\n config SYS_FSL_ERRATUM_A010315\n \tbool \"Workaround for PCIe erratum A010315\"\n \n+config SYS_FSL_HAS_CCI400\n+\tbool\n+\n config SYS_FSL_SRDS_1\n \tbool\n \ndiff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c\nindex b84a1a6..c043b82 100644\n--- a/arch/arm/cpu/armv7/ls102xa/soc.c\n+++ b/arch/arm/cpu/armv7/ls102xa/soc.c\n@@ -80,7 +80,8 @@ void erratum_a010315(void)\n int arch_soc_init(void)\n {\n \tstruct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;\n-\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n+\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +\n+\t\t\t\t\tCONFIG_SYS_CCI400_OFFSET);\n \tunsigned int major;\n \n #ifdef CONFIG_LAYERSCAPE_NS_ACCESS\ndiff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h\nindex fc954c5..ff0fc47 100644\n--- a/arch/arm/include/asm/arch-ls102xa/config.h\n+++ b/arch/arm/include/asm/arch-ls102xa/config.h\n@@ -20,7 +20,6 @@\n \n #define SYS_FSL_GIC_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x00400000)\n #define CONFIG_SYS_FSL_DDR_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x00080000)\n-#define CONFIG_SYS_CCI400_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x00180000)\n #define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)\n #define CONFIG_SYS_IFC_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x00530000)\n #define CONFIG_SYS_FSL_ESDHC_ADDR\t\t(CONFIG_SYS_IMMR + 0x00560000)\ndiff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex c34fd63..1415b0b 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -6,6 +6,7 @@\n \n #ifndef __ASM_ARCH_LS102XA_IMMAP_H_\n #define __ASM_ARCH_LS102XA_IMMAP_H_\n+#include <fsl_immap.h>\n \n #define SVR_MAJ(svr)\t\t(((svr) >>  4) & 0xf)\n #define SVR_MIN(svr)\t\t(((svr) >>  0) & 0xf)\n@@ -374,53 +375,7 @@ struct ccsr_serdes {\n \tu8\tres_a00[0x1000-0xa00];\t/* from 0xa00 to 0xfff */\n };\n \n-#define CCI400_CTRLORD_TERM_BARRIER\t0x00000008\n-#define CCI400_CTRLORD_EN_BARRIER\t0\n-#define CCI400_SHAORD_NON_SHAREABLE\t0x00000002\n-#define CCI400_DVM_MESSAGE_REQ_EN\t0x00000002\n-#define CCI400_SNOOP_REQ_EN\t\t0x00000001\n-\n-/* CCI-400 registers */\n-struct ccsr_cci400 {\n-\tu32 ctrl_ord;\t\t\t/* Control Override */\n-\tu32 spec_ctrl;\t\t\t/* Speculation Control */\n-\tu32 secure_access;\t\t/* Secure Access */\n-\tu32 status;\t\t\t/* Status */\n-\tu32 impr_err;\t\t\t/* Imprecise Error */\n-\tu8 res_14[0x100 - 0x14];\n-\tu32 pmcr;\t\t\t/* Performance Monitor Control */\n-\tu8 res_104[0xfd0 - 0x104];\n-\tu32 pid[8];\t\t\t/* Peripheral ID */\n-\tu32 cid[4];\t\t\t/* Component ID */\n-\tstruct {\n-\t\tu32 snoop_ctrl;\t\t/* Snoop Control */\n-\t\tu32 sha_ord;\t\t/* Shareable Override */\n-\t\tu8 res_1008[0x1100 - 0x1008];\n-\t\tu32 rc_qos_ord;\t\t/* read channel QoS Value Override */\n-\t\tu32 wc_qos_ord;\t\t/* read channel QoS Value Override */\n-\t\tu8 res_1108[0x110c - 0x1108];\n-\t\tu32 qos_ctrl;\t\t/* QoS Control */\n-\t\tu32 max_ot;\t\t/* Max OT */\n-\t\tu8 res_1114[0x1130 - 0x1114];\n-\t\tu32 target_lat;\t\t/* Target Latency */\n-\t\tu32 latency_regu;\t/* Latency Regulation */\n-\t\tu32 qos_range;\t\t/* QoS Range */\n-\t\tu8 res_113c[0x2000 - 0x113c];\n-\t} slave[5];\t\t\t/* Slave Interface */\n-\tu8 res_6000[0x9004 - 0x6000];\n-\tu32 cycle_counter;\t\t/* Cycle counter */\n-\tu32 count_ctrl;\t\t\t/* Count Control */\n-\tu32 overflow_status;\t\t/* Overflow Flag Status */\n-\tu8 res_9010[0xa000 - 0x9010];\n-\tstruct {\n-\t\tu32 event_select;\t/* Event Select */\n-\t\tu32 event_count;\t/* Event Count */\n-\t\tu32 counter_ctrl;\t/* Counter Control */\n-\t\tu32 overflow_status;\t/* Overflow Flag Status */\n-\t\tu8 res_a010[0xb000 - 0xa010];\n-\t} pcounter[4];\t\t\t/* Performance Counter */\n-\tu8 res_e004[0x10000 - 0xe004];\n-};\n+\n \n /* AHCI (sata) register map */\n struct ccsr_ahci {\ndiff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c\nindex d81d8ab..8b3f4ad 100644\n--- a/board/freescale/ls1021aqds/ls1021aqds.c\n+++ b/board/freescale/ls1021aqds/ls1021aqds.c\n@@ -204,7 +204,8 @@ int board_early_init_f(void)\n #ifdef CONFIG_SPL_BUILD\n void board_init_f(ulong dummy)\n {\n-\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n+\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +\n+\t\t\t\t\tCONFIG_SYS_CCI400_OFFSET);\n \tunsigned int major;\n \n #ifdef CONFIG_NAND_BOOT\n@@ -425,7 +426,8 @@ int misc_init_r(void)\n \n int board_init(void)\n {\n-\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n+\tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +\n+\t\t\t\t\tCONFIG_SYS_CCI400_OFFSET);\n \tunsigned int major;\n \n #ifdef CONFIG_SYS_FSL_ERRATUM_A010315\n@@ -460,7 +462,8 @@ int board_init(void)\n #if defined(CONFIG_DEEP_SLEEP)\n void board_sleep_prepare(void)\n {\n-\tstruct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;\n+\tstruct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +\n+\t\t\t\t\t\tCONFIG_SYS_CCI400_OFFSET);\n \tunsigned int major;\n \n \tmajor = get_soc_major_rev();\n",
    "prefixes": [
        "U-Boot",
        "v5",
        "2/3"
    ]
}