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GET /api/patches/798937/?format=api
{ "id": 798937, "url": "http://patchwork.ozlabs.org/api/patches/798937/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170807142839.60975-3-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170807142839.60975-3-alice.michael@intel.com>", "list_archive_url": null, "date": "2017-08-07T14:28:29", "name": "[next,S78-V6,02/12] i40e: Add support for 'ethtool -m'", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "1fb37d26fd9c970f49f011f4981168374f30a564", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170807142839.60975-3-alice.michael@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/798937/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/798937/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xRC3f4qZtz9sPr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 8 Aug 2017 08:33:18 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id F3C6A2FBD9;\n\tMon, 7 Aug 2017 22:33:16 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 1zP7sYYvo13D; Mon, 7 Aug 2017 22:33:13 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 110822F970;\n\tMon, 7 Aug 2017 22:33:13 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id D530A1C2679\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 7 Aug 2017 22:33:10 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id CFAAB2FBCD\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 7 Aug 2017 22:33:10 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id PUdAUI-PNxIw for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 7 Aug 2017 22:33:09 +0000 (UTC)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby silver.osuosl.org (Postfix) with ESMTPS id E66262FBB1\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 7 Aug 2017 22:33:08 +0000 (UTC)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t07 Aug 2017 15:33:08 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.16.121])\n\tby orsmga003.jf.intel.com with ESMTP; 07 Aug 2017 15:33:07 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.41,339,1498546800\"; d=\"scan'208\";\n\ta=\"1001084720\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Mon, 7 Aug 2017 10:28:29 -0400", "Message-Id": "<20170807142839.60975-3-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.9.4", "In-Reply-To": "<20170807142839.60975-1-alice.michael@intel.com>", "References": "<20170807142839.60975-1-alice.michael@intel.com>", "Cc": "Filip Sadowski <filip.sadowski@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S78-V6 02/12] i40e: Add support for\n\t'ethtool -m'", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Filip Sadowski <filip.sadowski@intel.com>\n\nThis patch adds support for 'ethtool -m' command which displays\ninformation about (Q)SFP+ module plugged into NIC's cage.\n\nSigned-off-by: Filip Sadowski <filip.sadowski@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h | 18 +++\n drivers/net/ethernet/intel/i40e/i40e_common.c | 69 +++++++++\n drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 154 +++++++++++++++++++++\n drivers/net/ethernet/intel/i40e/i40e_prototype.h | 9 ++\n drivers/net/ethernet/intel/i40e/i40e_type.h | 12 ++\n .../net/ethernet/intel/i40evf/i40e_adminq_cmd.h | 18 +++\n drivers/net/ethernet/intel/i40evf/i40e_common.c | 69 +++++++++\n drivers/net/ethernet/intel/i40evf/i40e_prototype.h | 9 ++\n drivers/net/ethernet/intel/i40evf/i40e_type.h | 12 ++\n 9 files changed, 370 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\nindex 0477faa..ef0a897 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n@@ -244,6 +244,8 @@ enum i40e_admin_queue_opc {\n \ti40e_aqc_opc_set_phy_debug\t\t= 0x0622,\n \ti40e_aqc_opc_upload_ext_phy_fm\t\t= 0x0625,\n \ti40e_aqc_opc_run_phy_activity\t\t= 0x0626,\n+\ti40e_aqc_opc_set_phy_register\t\t= 0x0628,\n+\ti40e_aqc_opc_get_phy_register\t\t= 0x0629,\n \n \t/* NVM commands */\n \ti40e_aqc_opc_nvm_read\t\t\t= 0x0701,\n@@ -2058,6 +2060,22 @@ struct i40e_aqc_run_phy_activity {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);\n \n+/* Set PHY Register command (0x0628) */\n+/* Get PHY Register command (0x0629) */\n+struct i40e_aqc_phy_register_access {\n+\tu8\tphy_interface;\n+#define I40E_AQ_PHY_REG_ACCESS_INTERNAL\t0\n+#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL\t1\n+#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE\t2\n+\tu8\tdev_address;\n+\tu8\treserved1[2];\n+\tu32\treg_address;\n+\tu32\treg_value;\n+\tu8\treserved2[4];\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);\n+\n /* NVM Read command (indirect 0x0701)\n * NVM Erase commands (direct 0x0702)\n * NVM Update commands (indirect 0x0703)\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex 37bac74..59a0a56 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -5067,6 +5067,75 @@ void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)\n }\n \n /**\n+ * i40e_aq_set_phy_register\n+ * @hw: pointer to the hw struct\n+ * @phy_select: select which phy should be accessed\n+ * @dev_addr: PHY device address\n+ * @reg_addr: PHY register address\n+ * @reg_val: new register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Write the external PHY register.\n+ **/\n+i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 phy_select, u8 dev_addr,\n+\t\t\t\t u32 reg_addr, u32 reg_val,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_phy_register_access *cmd =\n+\t\t(struct i40e_aqc_phy_register_access *)&desc.params.raw;\n+\ti40e_status status;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_set_phy_register);\n+\n+\tcmd->phy_interface = phy_select;\n+\tcmd->dev_address = dev_addr;\n+\tcmd->reg_address = reg_addr;\n+\tcmd->reg_value = reg_val;\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_aq_get_phy_register\n+ * @hw: pointer to the hw struct\n+ * @phy_select: select which phy should be accessed\n+ * @dev_addr: PHY device address\n+ * @reg_addr: PHY register address\n+ * @reg_val: read register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Read the external PHY register.\n+ **/\n+i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 phy_select, u8 dev_addr,\n+\t\t\t\t u32 reg_addr, u32 *reg_val,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_phy_register_access *cmd =\n+\t\t(struct i40e_aqc_phy_register_access *)&desc.params.raw;\n+\ti40e_status status;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_get_phy_register);\n+\n+\tcmd->phy_interface = phy_select;\n+\tcmd->dev_address = dev_addr;\n+\tcmd->reg_address = reg_addr;\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\tif (!status)\n+\t\t*reg_val = cmd->reg_value;\n+\n+\treturn status;\n+}\n+\n+/**\n * i40e_aq_write_ppp - Write pipeline personalization profile (ppp)\n * @hw: pointer to the hw struct\n * @buff: command buffer (size in bytes = buff_size)\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\nindex e3cbf07..0a2ead5 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n@@ -4205,6 +4205,158 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)\n \treturn 0;\n }\n \n+/**\n+ * i40e_get_module_info - get (Q)SFP+ module type info\n+ * @netdev: network interface device structure\n+ * @modinfo: module EEPROM size and layout information structure\n+ **/\n+static int i40e_get_module_info(struct net_device *netdev,\n+\t\t\t\tstruct ethtool_modinfo *modinfo)\n+{\n+\ti40e_status status;\n+\tstruct i40e_netdev_priv *np = netdev_priv(netdev);\n+\tstruct i40e_vsi *vsi = np->vsi;\n+\tstruct i40e_pf *pf = vsi->back;\n+\tstruct i40e_hw *hw = &pf->hw;\n+\tu32 sff8472_comp = 0;\n+\tu32 sff8472_swap = 0;\n+\tu32 sff8636_rev = 0;\n+\tu32 type = 0;\n+\n+\t/* Check if firmware supports reading module EEPROM. */\n+\tif (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {\n+\t\tnetdev_err(vsi->netdev, \"Module EEPROM memory read not supported. Please update the NVM image.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tstatus = i40e_update_link_info(hw);\n+\tif (status)\n+\t\treturn -EIO;\n+\n+\tif (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {\n+\t\tnetdev_err(vsi->netdev, \"Cannot read module EEPROM memory. No module connected.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttype = hw->phy.link_info.module_type[0];\n+\n+\tswitch (type) {\n+\tcase I40E_MODULE_TYPE_SFP:\n+\t\tstatus = i40e_aq_get_phy_register(hw,\n+\t\t\t\tI40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,\n+\t\t\t\tI40E_I2C_EEPROM_DEV_ADDR,\n+\t\t\t\tI40E_MODULE_SFF_8472_COMP,\n+\t\t\t\t&sff8472_comp, NULL);\n+\t\tif (status)\n+\t\t\treturn -EIO;\n+\n+\t\tstatus = i40e_aq_get_phy_register(hw,\n+\t\t\t\tI40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,\n+\t\t\t\tI40E_I2C_EEPROM_DEV_ADDR,\n+\t\t\t\tI40E_MODULE_SFF_8472_SWAP,\n+\t\t\t\t&sff8472_swap, NULL);\n+\t\tif (status)\n+\t\t\treturn -EIO;\n+\n+\t\t/* Check if the module requires address swap to access\n+\t\t * the other EEPROM memory page.\n+\t\t */\n+\t\tif (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {\n+\t\t\tnetdev_warn(vsi->netdev, \"Module address swap to access page 0xA2 is not supported.\\n\");\n+\t\t\tmodinfo->type = ETH_MODULE_SFF_8079;\n+\t\t\tmodinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;\n+\t\t} else if (sff8472_comp == 0x00) {\n+\t\t\t/* Module is not SFF-8472 compliant */\n+\t\t\tmodinfo->type = ETH_MODULE_SFF_8079;\n+\t\t\tmodinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;\n+\t\t} else {\n+\t\t\tmodinfo->type = ETH_MODULE_SFF_8472;\n+\t\t\tmodinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;\n+\t\t}\n+\t\tbreak;\n+\tcase I40E_MODULE_TYPE_QSFP_PLUS:\n+\t\t/* Read from memory page 0. */\n+\t\tstatus = i40e_aq_get_phy_register(hw,\n+\t\t\t\tI40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,\n+\t\t\t\t0,\n+\t\t\t\tI40E_MODULE_REVISION_ADDR,\n+\t\t\t\t&sff8636_rev, NULL);\n+\t\tif (status)\n+\t\t\treturn -EIO;\n+\t\t/* Determine revision compliance byte */\n+\t\tif (sff8636_rev > 0x02) {\n+\t\t\t/* Module is SFF-8636 compliant */\n+\t\t\tmodinfo->type = ETH_MODULE_SFF_8636;\n+\t\t\tmodinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;\n+\t\t} else {\n+\t\t\tmodinfo->type = ETH_MODULE_SFF_8436;\n+\t\t\tmodinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;\n+\t\t}\n+\t\tbreak;\n+\tcase I40E_MODULE_TYPE_QSFP28:\n+\t\tmodinfo->type = ETH_MODULE_SFF_8636;\n+\t\tmodinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;\n+\t\tbreak;\n+\tdefault:\n+\t\tnetdev_err(vsi->netdev, \"Module type unrecognized\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * i40e_get_module_eeprom - fills buffer with (Q)SFP+ module memory contents\n+ * @netdev: network interface device structure\n+ * @ee: EEPROM dump request structure\n+ * @data: buffer to be filled with EEPROM contents\n+ **/\n+static int i40e_get_module_eeprom(struct net_device *netdev,\n+\t\t\t\t struct ethtool_eeprom *ee,\n+\t\t\t\t u8 *data)\n+{\n+\ti40e_status status;\n+\tstruct i40e_netdev_priv *np = netdev_priv(netdev);\n+\tstruct i40e_vsi *vsi = np->vsi;\n+\tstruct i40e_pf *pf = vsi->back;\n+\tstruct i40e_hw *hw = &pf->hw;\n+\tbool is_sfp = false;\n+\tu32 value = 0;\n+\tint i;\n+\n+\tif (!ee || !ee->len || !data)\n+\t\treturn -EINVAL;\n+\n+\tif (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)\n+\t\tis_sfp = true;\n+\n+\tfor (i = 0; i < ee->len; i++) {\n+\t\tu32 offset = i + ee->offset;\n+\t\tu32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;\n+\n+\t\t/* Check if we need to access the other memory page */\n+\t\tif (is_sfp) {\n+\t\t\tif (offset >= ETH_MODULE_SFF_8079_LEN) {\n+\t\t\t\toffset -= ETH_MODULE_SFF_8079_LEN;\n+\t\t\t\taddr = I40E_I2C_EEPROM_DEV_ADDR2;\n+\t\t\t}\n+\t\t} else {\n+\t\t\twhile (offset >= ETH_MODULE_SFF_8436_LEN) {\n+\t\t\t\t/* Compute memory page number and offset. */\n+\t\t\t\toffset -= ETH_MODULE_SFF_8436_LEN / 2;\n+\t\t\t\taddr++;\n+\t\t\t}\n+\t\t}\n+\n+\t\tstatus = i40e_aq_get_phy_register(hw,\n+\t\t\t\tI40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,\n+\t\t\t\taddr, offset, &value, NULL);\n+\t\tif (status)\n+\t\t\treturn -EIO;\n+\t\tdata[i] = value;\n+\t}\n+\treturn 0;\n+}\n+\n static const struct ethtool_ops i40e_ethtool_ops = {\n \t.get_drvinfo\t\t= i40e_get_drvinfo,\n \t.get_regs_len\t\t= i40e_get_regs_len,\n@@ -4237,6 +4389,8 @@ static const struct ethtool_ops i40e_ethtool_ops = {\n \t.set_rxfh\t\t= i40e_set_rxfh,\n \t.get_channels\t\t= i40e_get_channels,\n \t.set_channels\t\t= i40e_set_channels,\n+\t.get_module_info\t= i40e_get_module_info,\n+\t.get_module_eeprom\t= i40e_get_module_eeprom,\n \t.get_ts_info\t\t= i40e_get_ts_info,\n \t.get_priv_flags\t\t= i40e_get_priv_flags,\n \t.set_priv_flags\t\t= i40e_set_priv_flags,\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\nindex df613ea..6254ad5 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n@@ -362,6 +362,15 @@ i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,\n \t\t\t\tu32 reg_addr, u32 reg_val,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);\n+i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 phy_select, u8 dev_addr,\n+\t\t\t\t u32 reg_addr, u32 reg_val,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details);\n+i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 phy_select, u8 dev_addr,\n+\t\t\t\t u32 reg_addr, u32 *reg_val,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details);\n+\n i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,\n \t\t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h\nindex fd4bbdd..4bb5914 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h\n@@ -428,6 +428,18 @@ struct i40e_nvm_access {\n \tu8 data[1];\n };\n \n+/* (Q)SFP module access definitions */\n+#define I40E_I2C_EEPROM_DEV_ADDR\t0xA0\n+#define I40E_I2C_EEPROM_DEV_ADDR2\t0xA2\n+#define I40E_MODULE_TYPE_ADDR\t\t0x00\n+#define I40E_MODULE_REVISION_ADDR\t0x01\n+#define I40E_MODULE_SFF_8472_COMP\t0x5E\n+#define I40E_MODULE_SFF_8472_SWAP\t0x5C\n+#define I40E_MODULE_SFF_ADDR_MODE\t0x04\n+#define I40E_MODULE_TYPE_QSFP_PLUS\t0x0D\n+#define I40E_MODULE_TYPE_QSFP28\t\t0x11\n+#define I40E_MODULE_QSFP_MAX_LEN\t640\n+\n /* PCI bus types */\n enum i40e_bus_type {\n \ti40e_bus_type_unknown = 0,\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\nindex e2581c6..5a271a4 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n@@ -244,6 +244,8 @@ enum i40e_admin_queue_opc {\n \ti40e_aqc_opc_set_phy_debug\t\t= 0x0622,\n \ti40e_aqc_opc_upload_ext_phy_fm\t\t= 0x0625,\n \ti40e_aqc_opc_run_phy_activity\t\t= 0x0626,\n+\ti40e_aqc_opc_set_phy_register\t\t= 0x0628,\n+\ti40e_aqc_opc_get_phy_register\t\t= 0x0629,\n \n \t/* NVM commands */\n \ti40e_aqc_opc_nvm_read\t\t\t= 0x0701,\n@@ -2051,6 +2053,22 @@ struct i40e_aqc_run_phy_activity {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);\n \n+/* Set PHY Register command (0x0628) */\n+/* Get PHY Register command (0x0629) */\n+struct i40e_aqc_phy_register_access {\n+\tu8\tphy_interface;\n+#define I40E_AQ_PHY_REG_ACCESS_INTERNAL\t0\n+#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL\t1\n+#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE\t2\n+\tu8\tdev_address;\n+\tu8\treserved1[2];\n+\tu32\treg_address;\n+\tu32\treg_value;\n+\tu8\treserved2[4];\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);\n+\n /* NVM Read command (indirect 0x0701)\n * NVM Erase commands (direct 0x0702)\n * NVM Update commands (indirect 0x0703)\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/i40evf/i40e_common.c\nindex 8d3a2bf..7df4610 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_common.c\n@@ -1042,6 +1042,75 @@ void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)\n }\n \n /**\n+ * i40evf_aq_set_phy_register\n+ * @hw: pointer to the hw struct\n+ * @phy_select: select which phy should be accessed\n+ * @dev_addr: PHY device address\n+ * @reg_addr: PHY register address\n+ * @reg_val: new register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Reset the external PHY.\n+ **/\n+i40e_status i40evf_aq_set_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 phy_select, u8 dev_addr,\n+\t\t\t\t u32 reg_addr, u32 reg_val,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_phy_register_access *cmd =\n+\t\t(struct i40e_aqc_phy_register_access *)&desc.params.raw;\n+\ti40e_status status;\n+\n+\ti40evf_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_set_phy_register);\n+\n+\tcmd->phy_interface = phy_select;\n+\tcmd->dev_address = dev_addr;\n+\tcmd->reg_address = reg_addr;\n+\tcmd->reg_value = reg_val;\n+\n+\tstatus = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40evf_aq_get_phy_register\n+ * @hw: pointer to the hw struct\n+ * @phy_select: select which phy should be accessed\n+ * @dev_addr: PHY device address\n+ * @reg_addr: PHY register address\n+ * @reg_val: read register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Reset the external PHY.\n+ **/\n+i40e_status i40evf_aq_get_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 phy_select, u8 dev_addr,\n+\t\t\t\t u32 reg_addr, u32 *reg_val,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_phy_register_access *cmd =\n+\t\t(struct i40e_aqc_phy_register_access *)&desc.params.raw;\n+\ti40e_status status;\n+\n+\ti40evf_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_get_phy_register);\n+\n+\tcmd->phy_interface = phy_select;\n+\tcmd->dev_address = dev_addr;\n+\tcmd->reg_address = reg_addr;\n+\n+\tstatus = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\tif (!status)\n+\t\t*reg_val = cmd->reg_value;\n+\n+\treturn status;\n+}\n+\n+/**\n * i40e_aq_send_msg_to_pf\n * @hw: pointer to the hardware structure\n * @v_opcode: opcodes for VF-PF communication\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\nindex c9836bb..b624b59 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n@@ -111,6 +111,15 @@ i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,\n \t\t\t\tu32 reg_addr, u32 reg_val,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);\n+i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 phy_select, u8 dev_addr,\n+\t\t\t\t u32 reg_addr, u32 reg_val,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details);\n+i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 phy_select, u8 dev_addr,\n+\t\t\t\t u32 reg_addr, u32 *reg_val,\n+\t\t\t\t struct i40e_asq_cmd_details *cmd_details);\n+\n i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,\n \t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h\nindex 2ea919d..b53584e 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h\n@@ -401,6 +401,18 @@ struct i40e_nvm_access {\n \tu8 data[1];\n };\n \n+/* (Q)SFP module access definitions */\n+#define I40E_I2C_EEPROM_DEV_ADDR\t0xA0\n+#define I40E_I2C_EEPROM_DEV_ADDR2\t0xA2\n+#define I40E_MODULE_TYPE_ADDR\t\t0x00\n+#define I40E_MODULE_REVISION_ADDR\t0x01\n+#define I40E_MODULE_SFF_8472_COMP\t0x5E\n+#define I40E_MODULE_SFF_8472_SWAP\t0x5C\n+#define I40E_MODULE_SFF_ADDR_MODE\t0x04\n+#define I40E_MODULE_TYPE_QSFP_PLUS\t0x0D\n+#define I40E_MODULE_TYPE_QSFP28\t\t0x11\n+#define I40E_MODULE_QSFP_MAX_LEN\t640\n+\n /* PCI bus types */\n enum i40e_bus_type {\n \ti40e_bus_type_unknown = 0,\n", "prefixes": [ "next", "S78-V6", "02/12" ] }