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GET /api/patches/798905/?format=api
{ "id": 798905, "url": "http://patchwork.ozlabs.org/api/patches/798905/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170807131812.86747-3-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170807131812.86747-3-alice.michael@intel.com>", "list_archive_url": null, "date": "2017-08-07T13:18:03", "name": "[next,S78-V5,03/12] i40e: use admin queue for setting LEDs behavior", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "cc691bd812ff08ff0340b81cd23b6f4f4ec9cadc", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170807131812.86747-3-alice.michael@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/798905/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/798905/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xR9VP1xpgz9sNV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 8 Aug 2017 07:22:53 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 897AD2A29E;\n\tMon, 7 Aug 2017 21:22:51 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 9m8TldCKT8QJ; Mon, 7 Aug 2017 21:22:50 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 51A182F98A;\n\tMon, 7 Aug 2017 21:22:50 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id F20171C203E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 7 Aug 2017 21:22:47 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id ED77A85D18\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 7 Aug 2017 21:22:47 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id soofidTRmiGC for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 7 Aug 2017 21:22:44 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id B99E685FDC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 7 Aug 2017 21:22:44 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t07 Aug 2017 14:22:44 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.16.121])\n\tby orsmga004.jf.intel.com with ESMTP; 07 Aug 2017 14:22:43 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.41,339,1498546800\"; d=\"scan'208\";a=\"116660460\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Mon, 7 Aug 2017 09:18:03 -0400", "Message-Id": "<20170807131812.86747-3-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.9.4", "In-Reply-To": "<20170807131812.86747-1-alice.michael@intel.com>", "References": "<20170807131812.86747-1-alice.michael@intel.com>", "Cc": "Mariusz Stachura <mariusz.stachura@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S78-V5 03/12] i40e: use admin queue\n\tfor setting LEDs behavior", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Mariusz Stachura <mariusz.stachura@intel.com>\n\nInstead of accessing register directly, use newly added AQC in\norder to blink LEDs. Introduce and utilize a new flag to prevent\nexcessive API version checking.\n\nSigned-off-by: Mariusz Stachura <mariusz.stachura@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_adminq.c | 6 ++\n drivers/net/ethernet/intel/i40e/i40e_common.c | 148 ++++++++++++++++++++------\n drivers/net/ethernet/intel/i40e/i40e_type.h | 1 +\n drivers/net/ethernet/intel/i40evf/i40e_type.h | 2 +\n 4 files changed, 122 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.c b/drivers/net/ethernet/intel/i40e/i40e_adminq.c\nindex ba04988..340e5a2 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_adminq.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.c\n@@ -607,6 +607,12 @@ i40e_status i40e_init_adminq(struct i40e_hw *hw)\n \t\t\t &oem_lo);\n \thw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;\n \n+\tif (hw->mac.type == I40E_MAC_XL710 &&\n+\t hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&\n+\t hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {\n+\t\thw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;\n+\t}\n+\n \tif (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {\n \t\tret_code = I40E_ERR_FIRMWARE_API_VERSION;\n \t\tgoto init_adminq_free_arq;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex 4e560ae..6b7712c 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -4855,24 +4855,38 @@ i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,\n \tu16 temp_addr;\n \tu8 port_num;\n \tu32 i;\n-\n-\ttemp_addr = I40E_PHY_LED_PROV_REG_1;\n-\ti = rd32(hw, I40E_PFGEN_PORTNUM);\n-\tport_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);\n-\tphy_addr = i40e_get_phy_address(hw, port_num);\n-\n-\tfor (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,\n-\t temp_addr++) {\n-\t\tstatus = i40e_read_phy_register_clause45(hw,\n+\tu32 reg_val_aq;\n+\n+\tif (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {\n+\t\tstatus =\n+\t\t i40e_aq_get_phy_register(hw,\n+\t\t\t\t\t I40E_AQ_PHY_REG_ACCESS_EXTERNAL,\n+\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t I40E_PHY_LED_PROV_REG_1,\n+\t\t\t\t\t ®_val_aq, NULL);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t\t*val = (u16)reg_val_aq;\n+\t} else {\n+\t\ttemp_addr = I40E_PHY_LED_PROV_REG_1;\n+\t\ti = rd32(hw, I40E_PFGEN_PORTNUM);\n+\t\tport_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);\n+\t\tphy_addr = i40e_get_phy_address(hw, port_num);\n+\n+\t\tfor (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,\n+\t\t temp_addr++) {\n+\t\t\tstatus =\n+\t\t\t i40e_read_phy_register_clause45(hw,\n \t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n \t\t\t\t\t\t\t temp_addr, phy_addr,\n \t\t\t\t\t\t\t ®_val);\n-\t\tif (status)\n-\t\t\treturn status;\n-\t\t*val = reg_val;\n-\t\tif (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {\n-\t\t\t*led_addr = temp_addr;\n-\t\t\tbreak;\n+\t\t\tif (status)\n+\t\t\t\treturn status;\n+\t\t\t*val = reg_val;\n+\t\t\tif (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {\n+\t\t\t\t*led_addr = temp_addr;\n+\t\t\t\tbreak;\n+\t\t\t}\n \t\t}\n \t}\n \treturn status;\n@@ -4890,51 +4904,115 @@ i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,\n \t\t\t u16 led_addr, u32 mode)\n {\n \ti40e_status status = 0;\n-\tu16 led_ctl = 0;\n-\tu16 led_reg = 0;\n+\tu32 led_ctl = 0;\n+\tu32 led_reg = 0;\n \tu8 phy_addr = 0;\n \tu8 port_num;\n \tu32 i;\n \n-\ti = rd32(hw, I40E_PFGEN_PORTNUM);\n-\tport_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);\n-\tphy_addr = i40e_get_phy_address(hw, port_num);\n-\tstatus = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t led_addr, phy_addr, &led_reg);\n+\tif (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {\n+\t\tstatus =\n+\t\t i40e_aq_get_phy_register(hw,\n+\t\t\t\t\t I40E_AQ_PHY_REG_ACCESS_EXTERNAL,\n+\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t I40E_PHY_LED_PROV_REG_1,\n+\t\t\t\t\t &led_reg, NULL);\n+\t} else {\n+\t\ti = rd32(hw, I40E_PFGEN_PORTNUM);\n+\t\tport_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);\n+\t\tphy_addr = i40e_get_phy_address(hw, port_num);\n+\t\tstatus = i40e_read_phy_register_clause45(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t\t (u16 *)&led_reg);\n+\t}\n \tif (status)\n \t\treturn status;\n \tled_ctl = led_reg;\n \tif (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {\n \t\tled_reg = 0;\n-\t\tstatus = i40e_write_phy_register_clause45(hw,\n-\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t\t led_addr, phy_addr,\n-\t\t\t\t\t\t\t led_reg);\n+\t\tif (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&\n+\t\t hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {\n+\t\t\tstatus = i40e_aq_set_phy_register(hw,\n+\t\t\t\t\tI40E_AQ_PHY_REG_ACCESS_EXTERNAL,\n+\t\t\t\t\tI40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\tI40E_PHY_LED_PROV_REG_1,\n+\t\t\t\t\tled_reg, NULL);\n+\t\t} else {\n+\t\t\tstatus = i40e_write_phy_register_clause45(hw,\n+\t\t\t\t\t\t\tI40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\tled_addr, phy_addr,\n+\t\t\t\t\t\t\t(u16)led_reg);\n+\t\t}\n \t\tif (status)\n \t\t\treturn status;\n \t}\n-\tstatus = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t led_addr, phy_addr, &led_reg);\n+\tif (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {\n+\t\tstatus =\n+\t\t i40e_aq_get_phy_register(hw,\n+\t\t\t\t\t I40E_AQ_PHY_REG_ACCESS_EXTERNAL,\n+\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t I40E_PHY_LED_PROV_REG_1,\n+\t\t\t\t\t &led_reg, NULL);\n+\t} else {\n+\t\tstatus = i40e_read_phy_register_clause45(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t\t (u16 *)&led_reg);\n+\t}\n \tif (status)\n \t\tgoto restore_config;\n \tif (on)\n \t\tled_reg = I40E_PHY_LED_MANUAL_ON;\n \telse\n \t\tled_reg = 0;\n-\tstatus = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t led_addr, phy_addr, led_reg);\n+\n+\tif (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {\n+\t\tstatus =\n+\t\t i40e_aq_set_phy_register(hw,\n+\t\t\t\t\t I40E_AQ_PHY_REG_ACCESS_EXTERNAL,\n+\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t I40E_PHY_LED_PROV_REG_1,\n+\t\t\t\t\t led_reg, NULL);\n+\t} else {\n+\t\tstatus =\n+\t\t i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t (u16)led_reg);\n+\t}\n \tif (status)\n \t\tgoto restore_config;\n \tif (mode & I40E_PHY_LED_MODE_ORIG) {\n \t\tled_ctl = (mode & I40E_PHY_LED_MODE_MASK);\n-\t\tstatus = i40e_write_phy_register_clause45(hw,\n-\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t led_addr, phy_addr, led_ctl);\n+\t\tif (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {\n+\t\t\tstatus = i40e_aq_set_phy_register(hw,\n+\t\t\t\t\tI40E_AQ_PHY_REG_ACCESS_EXTERNAL,\n+\t\t\t\t\tI40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\tI40E_PHY_LED_PROV_REG_1,\n+\t\t\t\t\tled_ctl, NULL);\n+\t\t} else {\n+\t\t\tstatus = i40e_write_phy_register_clause45(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t\t (u16)led_ctl);\n+\t\t}\n \t}\n \treturn status;\n restore_config:\n-\tstatus = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t led_addr, phy_addr, led_ctl);\n+\tif (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {\n+\t\tstatus =\n+\t\t i40e_aq_set_phy_register(hw,\n+\t\t\t\t\t I40E_AQ_PHY_REG_ACCESS_EXTERNAL,\n+\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t I40E_PHY_LED_PROV_REG_1,\n+\t\t\t\t\t led_ctl, NULL);\n+\t} else {\n+\t\tstatus =\n+\t\t\ti40e_write_phy_register_clause45(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t\t (u16)led_ctl);\n+\t}\n \treturn status;\n }\n \ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h\nindex 4bb5914..8b0b9f8 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h\n@@ -610,6 +610,7 @@ struct i40e_hw {\n \tstruct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */\n \n #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)\n+#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)\n \tu64 flags;\n \n \t/* debug mask */\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h\nindex b53584e..48eacf5 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h\n@@ -568,6 +568,8 @@ struct i40e_hw {\n \t/* LLDP/DCBX Status */\n \tu16 dcbx_status;\n \n+#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)\n+\n \t/* DCBX info */\n \tstruct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */\n \tstruct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */\n", "prefixes": [ "next", "S78-V5", "03/12" ] }