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GET /api/patches/798828/?format=api
{ "id": 798828, "url": "http://patchwork.ozlabs.org/api/patches/798828/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1502132366-31918-1-git-send-email-agust@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1502132366-31918-1-git-send-email-agust@denx.de>", "list_archive_url": null, "date": "2017-08-07T18:59:26", "name": "[U-Boot,v4,2/3] rockchip: video: mipi: Split mipi driver into common and specific parts", "commit_ref": "36602eba803d13520a4980dd0ccb0e243214052e", "pull_url": null, "state": "accepted", "archived": false, "hash": "dd737af0fd861d42d863195fdaf2775d7f3da3e7", "submitter": { "id": 872, "url": "http://patchwork.ozlabs.org/api/people/872/?format=api", "name": "Anatolij Gustschin", "email": "agust@denx.de" }, "delegate": { "id": 1700, "url": "http://patchwork.ozlabs.org/api/users/1700/?format=api", "username": "ag", "first_name": "Anatolij", "last_name": "Gustschin", "email": "agust@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1502132366-31918-1-git-send-email-agust@denx.de/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/798828/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/798828/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xR6K56kvLz9sCZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 8 Aug 2017 04:59:37 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 9EF33C21D76; Mon, 7 Aug 2017 18:59:36 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4794AC21C40;\n\tMon, 7 Aug 2017 18:59:31 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid E9AAAC21C40; Mon, 7 Aug 2017 18:59:29 +0000 (UTC)", "from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9])\n\tby lists.denx.de (Postfix) with ESMTPS id 6EA23C21C3F\n\tfor <u-boot@lists.denx.de>; Mon, 7 Aug 2017 18:59:29 +0000 (UTC)", "from frontend01.mail.m-online.net (unknown [192.168.8.182])\n\tby mail-out.m-online.net (Postfix) with ESMTP id 3xR6Jw74QKz1qqkh;\n\tMon, 7 Aug 2017 20:59:28 +0200 (CEST)", "from localhost (dynscan1.mnet-online.de [192.168.6.70])\n\tby mail.m-online.net (Postfix) with ESMTP id 3xR6Jw6mLWz3jgYD;\n\tMon, 7 Aug 2017 20:59:28 +0200 (CEST)", "from mail.mnet-online.de ([192.168.8.182])\n\tby localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new,\n\tport 10024)\n\twith ESMTP id 36rwAf2ZWFT7; Mon, 7 Aug 2017 20:59:27 +0200 (CEST)", "from crub.agik.hopto.org (p4FCB52B3.dip0.t-ipconnect.de\n\t[79.203.82.179]) (using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 7 Aug 2017 20:59:27 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "X-Virus-Scanned": "amavisd-new at mnet-online.de", "X-Auth-Info": "cL+NCRQi8SV3xcpXXoiHvGvUz24on9dU9WOSQfNc3us=", "From": "Anatolij Gustschin <agust@denx.de>", "To": "u-boot@lists.denx.de", "Date": "Mon, 7 Aug 2017 20:59:26 +0200", "Message-Id": "<1502132366-31918-1-git-send-email-agust@denx.de>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1498015234-12919-3-git-send-email-eric.gao@rock-chips.com>", "References": "<1498015234-12919-3-git-send-email-eric.gao@rock-chips.com>", "MIME-Version": "1.0", "Cc": "\"eric.gao@rock-chips.com\" <eric.gao@rock-chips.com>", "Subject": "[U-Boot] [PATCH v4 2/3] rockchip: video: mipi: Split mipi driver\n\tinto common and specific parts", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: \"eric.gao@rock-chips.com\" <eric.gao@rock-chips.com>\n\nTo compatible with different rockchip soc, we split the mipi dirver into\ncommon and soc specific parts, and all the soc share the common\nfunctions from common driver part.\n\nSigned-off-by: Eric Gao <eric.gao@rock-chips.com>\nAcked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\n[agust: fix build breakage and warnings]\nSigned-off-by: Anatolij Gustschin <agust@denx.de>\n---\n drivers/video/rockchip/rk3399_mipi.c | 182 +++++++++++++++++++++++++++++++++++\n drivers/video/rockchip/rk_mipi.c | 170 ++------------------------------\n drivers/video/rockchip/rk_mipi.h | 32 ++++++\n 3 files changed, 220 insertions(+), 164 deletions(-)\n create mode 100644 drivers/video/rockchip/rk3399_mipi.c\n create mode 100644 drivers/video/rockchip/rk_mipi.h\n\nChanges in v4:\n- fix build warnings:\ndrivers/video/rockchip/rk_mipi.c: In function ?rk_mipi_dsi_enable?:\ndrivers/video/rockchip/rk_mipi.c:85:19: warning: initialization makes integer from pointer without a cast [-Wint-conversion]\ndrivers/video/rockchip/rk_mipi.c: In function ?rk_mipi_phy_enable?:\ndrivers/video/rockchip/rk_mipi.c:202:19: warning: initialization makes integer from pointer without a cast [-Wint-conversion]\n...\ndrivers/video/rockchip/rk3399_mipi.c: In function ‘rk_mipi_ofdata_to_platdata’:\ndrivers/video/rockchip/rk3399_mipi.c:136:13: warning: assignment makes pointer from integer without a cast [-Wint-conversion]\n\n- fix build breakage in debug();", "diff": "diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c\nnew file mode 100644\nindex 0000000..9ef202b\n--- /dev/null\n+++ b/drivers/video/rockchip/rk3399_mipi.c\n@@ -0,0 +1,182 @@\n+/*\n+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd\n+ * Author: Eric Gao <eric.gao@rock-chips.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <clk.h>\n+#include <display.h>\n+#include <dm.h>\n+#include <fdtdec.h>\n+#include <panel.h>\n+#include <regmap.h>\n+#include \"rk_mipi.h\"\n+#include <syscon.h>\n+#include <asm/gpio.h>\n+#include <asm/hardware.h>\n+#include <asm/io.h>\n+#include <dm/uclass-internal.h>\n+#include <linux/kernel.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/cru_rk3399.h>\n+#include <asm/arch/grf_rk3399.h>\n+#include <asm/arch/rockchip_mipi_dsi.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+/* Select mipi dsi source, big or little vop */\n+static int rk_mipi_dsi_source_select(struct udevice *dev)\n+{\n+\tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n+\tstruct rk3399_grf_regs *grf = priv->grf;\n+\tstruct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);\n+\n+\t/* Select the video source */\n+\tswitch (disp_uc_plat->source_id) {\n+\tcase VOP_B:\n+\t\trk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,\n+\t\t\t GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);\n+\t\tbreak;\n+\tcase VOP_L:\n+\t\trk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,\n+\t\t\t GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);\n+\t\tbreak;\n+\tdefault:\n+\t\tdebug(\"%s: Invalid VOP id\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Setup mipi dphy working mode */\n+static void rk_mipi_dphy_mode_set(struct udevice *dev)\n+{\n+\tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n+\tstruct rk3399_grf_regs *grf = priv->grf;\n+\tint val;\n+\n+\t/* Set Controller as TX mode */\n+\tval = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;\n+\trk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);\n+\n+\t/* Exit tx stop mode */\n+\tval |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;\n+\trk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);\n+\n+\t/* Disable turnequest */\n+\tval |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;\n+\trk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);\n+}\n+\n+/*\n+ * This function is called by rk_display_init() using rk_mipi_dsi_enable() and\n+ * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,\n+ * enable backlight.\n+ */\n+static int rk_display_enable(struct udevice *dev, int panel_bpp,\n+\t\t\t const struct display_timing *timing)\n+{\n+\tint ret;\n+\tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n+\n+\t/* Fill the mipi controller parameter */\n+\tpriv->ref_clk = 24 * MHz;\n+\tpriv->sys_clk = priv->ref_clk;\n+\tpriv->pix_clk = timing->pixelclock.typ;\n+\tpriv->phy_clk = priv->pix_clk * 6;\n+\tpriv->txbyte_clk = priv->phy_clk / 8;\n+\tpriv->txesc_clk = 20 * MHz;\n+\n+\t/* Select vop port, big or little */\n+\trk_mipi_dsi_source_select(dev);\n+\n+\t/* Set mipi dphy work mode */\n+\trk_mipi_dphy_mode_set(dev);\n+\n+\t/* Config and enable mipi dsi according to timing */\n+\tret = rk_mipi_dsi_enable(dev, timing);\n+\tif (ret) {\n+\t\tdebug(\"%s: rk_mipi_dsi_enable() failed (err=%d)\\n\",\n+\t\t __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Config and enable mipi phy */\n+\tret = rk_mipi_phy_enable(dev);\n+\tif (ret) {\n+\t\tdebug(\"%s: rk_mipi_phy_enable() failed (err=%d)\\n\",\n+\t\t __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Enable backlight */\n+\tret = panel_enable_backlight(priv->panel);\n+\tif (ret) {\n+\t\tdebug(\"%s: panel_enable_backlight() failed (err=%d)\\n\",\n+\t\t __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int rk_mipi_ofdata_to_platdata(struct udevice *dev)\n+{\n+\tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n+\tif (priv->grf <= 0) {\n+\t\tdebug(\"%s: Get syscon grf failed (ret=%p)\\n\",\n+\t\t __func__, priv->grf);\n+\t\treturn -ENXIO;\n+\t}\n+\tpriv->regs = dev_read_addr(dev);\n+\tif (priv->regs == FDT_ADDR_T_NONE) {\n+\t\tdebug(\"%s: Get MIPI dsi address failed\\n\", __func__);\n+\t\treturn -ENXIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Probe function: check panel existence and readingit's timing. Then config\n+ * mipi dsi controller and enable it according to the timing parameter.\n+ */\n+static int rk_mipi_probe(struct udevice *dev)\n+{\n+\tint ret;\n+\tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n+\n+\tret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, \"rockchip,panel\",\n+\t\t\t\t\t &priv->panel);\n+\tif (ret) {\n+\t\tdebug(\"%s: Can not find panel (err=%d)\\n\", __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_display_ops rk_mipi_dsi_ops = {\n+\t.read_timing = rk_mipi_read_timing,\n+\t.enable = rk_display_enable,\n+};\n+\n+static const struct udevice_id rk_mipi_dsi_ids[] = {\n+\t{ .compatible = \"rockchip,rk3399_mipi_dsi\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(rk_mipi_dsi) = {\n+\t.name\t= \"rk_mipi_dsi\",\n+\t.id\t= UCLASS_DISPLAY,\n+\t.of_match = rk_mipi_dsi_ids,\n+\t.ofdata_to_platdata = rk_mipi_ofdata_to_platdata,\n+\t.probe\t= rk_mipi_probe,\n+\t.ops\t= &rk_mipi_dsi_ops,\n+\t.priv_auto_alloc_size = sizeof(struct rk_mipi_priv),\n+};\ndiff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c\nindex 1199a30..d537755 100644\n--- a/drivers/video/rockchip/rk_mipi.c\n+++ b/drivers/video/rockchip/rk_mipi.c\n@@ -12,6 +12,7 @@\n #include <fdtdec.h>\n #include <panel.h>\n #include <regmap.h>\n+#include \"rk_mipi.h\"\n #include <syscon.h>\n #include <asm/gpio.h>\n #include <asm/hardware.h>\n@@ -22,38 +23,11 @@\n #include <asm/arch/cru_rk3399.h>\n #include <asm/arch/grf_rk3399.h>\n #include <asm/arch/rockchip_mipi_dsi.h>\n-#include <dt-bindings/clock/rk3288-cru.h>\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-/*\n- * Private information for rk mipi\n- *\n- * @regs: mipi controller address\n- * @grf: GRF register\n- * @panel: panel assined by device tree\n- * @ref_clk: reference clock for mipi dsi pll\n- * @sysclk: config clock for mipi dsi register\n- * @pix_clk: pixel clock for vop->dsi data transmission\n- * @phy_clk: mipi dphy output clock\n- * @txbyte_clk: clock for dsi->dphy high speed data transmission\n- * @txesc_clk: clock for tx esc mode\n- */\n-struct rk_mipi_priv {\n-\tuintptr_t regs;\n-\tstruct rk3399_grf_regs *grf;\n-\tstruct udevice *panel;\n-\tstruct mipi_dsi *dsi;\n-\tu32 ref_clk;\n-\tu32 sys_clk;\n-\tu32 pix_clk;\n-\tu32 phy_clk;\n-\tu32 txbyte_clk;\n-\tu32 txesc_clk;\n-};\n-\n-static int rk_mipi_read_timing(struct udevice *dev,\n-\t\t\t struct display_timing *timing)\n+int rk_mipi_read_timing(struct udevice *dev,\n+\t\t\tstruct display_timing *timing)\n {\n \tint ret;\n \n@@ -102,46 +76,18 @@ static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)\n \twritel(dat, addr);\n }\n \n-static int rk_mipi_dsi_enable(struct udevice *dev,\n-\t\t\t const struct display_timing *timing)\n+int rk_mipi_dsi_enable(struct udevice *dev,\n+\t\t const struct display_timing *timing)\n {\n \tint node, timing_node;\n \tint val;\n \tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n \tuintptr_t regs = priv->regs;\n-\tstruct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);\n \tu32 txbyte_clk = priv->txbyte_clk;\n \tu32 txesc_clk = priv->txesc_clk;\n \n \ttxesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);\n \n-\t/* Select the video source */\n-\tswitch (disp_uc_plat->source_id) {\n-\tcase VOP_B:\n-\t\trk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,\n-\t\t\t GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);\n-\t\t break;\n-\tcase VOP_L:\n-\t\trk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,\n-\t\t\t GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);\n-\t\t break;\n-\tdefault:\n-\t\t debug(\"%s: Invalid VOP id\\n\", __func__);\n-\t\t return -EINVAL;\n-\t}\n-\n-\t/* Set Controller as TX mode */\n-\tval = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;\n-\trk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);\n-\n-\t/* Exit tx stop mode */\n-\tval |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;\n-\trk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);\n-\n-\t/* Disable turnequest */\n-\tval |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;\n-\trk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);\n-\n \t/* Set Display timing parameter */\n \trk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);\n \trk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);\n@@ -249,7 +195,7 @@ static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code,\n * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,\n * and then enable phy.\n */\n-static int rk_mipi_phy_enable(struct udevice *dev)\n+int rk_mipi_phy_enable(struct udevice *dev)\n {\n \tint i;\n \tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n@@ -385,107 +331,3 @@ static int rk_mipi_phy_enable(struct udevice *dev)\n \treturn 0;\n }\n \n-/*\n- * This function is called by rk_display_init() using rk_mipi_dsi_enable() and\n- * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,\n- * enable backlight.\n- */\n-static int rk_display_enable(struct udevice *dev, int panel_bpp,\n-\t\t\t const struct display_timing *timing)\n-{\n-\tint ret;\n-\tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n-\n-\t/* Fill the mipi controller parameter */\n-\tpriv->ref_clk = 24 * MHz;\n-\tpriv->sys_clk = priv->ref_clk;\n-\tpriv->pix_clk = timing->pixelclock.typ;\n-\tpriv->phy_clk = priv->pix_clk * 6;\n-\tpriv->txbyte_clk = priv->phy_clk / 8;\n-\tpriv->txesc_clk = 20 * MHz;\n-\n-\t/* Config and enable mipi dsi according to timing */\n-\tret = rk_mipi_dsi_enable(dev, timing);\n-\tif (ret) {\n-\t\tdebug(\"%s: rk_mipi_dsi_enable() failed (err=%d)\\n\",\n-\t\t __func__, ret);\n-\t\treturn ret;\n-\t}\n-\n-\t/* Config and enable mipi phy */\n-\tret = rk_mipi_phy_enable(dev);\n-\tif (ret) {\n-\t\tdebug(\"%s: rk_mipi_phy_enable() failed (err=%d)\\n\",\n-\t\t __func__, ret);\n-\t\treturn ret;\n-\t}\n-\n-\t/* Enable backlight */\n-\tret = panel_enable_backlight(priv->panel);\n-\tif (ret) {\n-\t\tdebug(\"%s: panel_enable_backlight() failed (err=%d)\\n\",\n-\t\t __func__, ret);\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int rk_mipi_ofdata_to_platdata(struct udevice *dev)\n-{\n-\tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n-\n-\tpriv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n-\tif (priv->grf <= 0) {\n-\t\tdebug(\"%s: Get syscon grf failed (ret=%p)\\n\",\n-\t\t __func__, priv->grf);\n-\t\treturn -ENXIO;\n-\t}\n-\tpriv->regs = devfdt_get_addr(dev);\n-\tif (priv->regs <= 0) {\n-\t\tdebug(\"%s: Get MIPI dsi address failed (ret=%lu)\\n\", __func__,\n-\t\t priv->regs);\n-\t\treturn -ENXIO;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/*\n- * Probe function: check panel existence and readingit's timing. Then config\n- * mipi dsi controller and enable it according to the timing parameter.\n- */\n-static int rk_mipi_probe(struct udevice *dev)\n-{\n-\tint ret;\n-\tstruct rk_mipi_priv *priv = dev_get_priv(dev);\n-\n-\tret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, \"rockchip,panel\",\n-\t\t\t\t\t &priv->panel);\n-\tif (ret) {\n-\t\tdebug(\"%s: Can not find panel (err=%d)\\n\", __func__, ret);\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static const struct dm_display_ops rk_mipi_dsi_ops = {\n-\t.read_timing = rk_mipi_read_timing,\n-\t.enable = rk_display_enable,\n-};\n-\n-static const struct udevice_id rk_mipi_dsi_ids[] = {\n-\t{ .compatible = \"rockchip,rk3399_mipi_dsi\" },\n-\t{ }\n-};\n-\n-U_BOOT_DRIVER(rk_mipi_dsi) = {\n-\t.name\t= \"rk_mipi_dsi\",\n-\t.id\t= UCLASS_DISPLAY,\n-\t.of_match = rk_mipi_dsi_ids,\n-\t.ofdata_to_platdata = rk_mipi_ofdata_to_platdata,\n-\t.probe\t= rk_mipi_probe,\n-\t.ops\t= &rk_mipi_dsi_ops,\n-\t.priv_auto_alloc_size = sizeof(struct rk_mipi_priv),\n-};\ndiff --git a/drivers/video/rockchip/rk_mipi.h b/drivers/video/rockchip/rk_mipi.h\nnew file mode 100644\nindex 0000000..d8a7b80\n--- /dev/null\n+++ b/drivers/video/rockchip/rk_mipi.h\n@@ -0,0 +1,32 @@\n+/*\n+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd\n+ * Author: Eric Gao <eric.gao@rock-chips.com>\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#ifndef __RK_MIPI_H\n+#define __RK_MIPI_H\n+\n+struct rk_mipi_priv {\n+\tulong regs;\n+\tvoid *grf;\n+\tstruct udevice *panel;\n+\tstruct mipi_dsi *dsi;\n+\tu32 ref_clk;\n+\tu32 sys_clk;\n+\tu32 pix_clk;\n+\tu32 phy_clk;\n+\tu32 txbyte_clk;\n+\tu32 txesc_clk;\n+};\n+\n+int rk_mipi_read_timing(struct udevice *dev,\n+\t\t\t struct display_timing *timing);\n+\n+int rk_mipi_dsi_enable(struct udevice *dev,\n+\t\t\t const struct display_timing *timing);\n+\n+int rk_mipi_phy_enable(struct udevice *dev);\n+\n+\n+#endif\n", "prefixes": [ "U-Boot", "v4", "2/3" ] }