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GET /api/patches/798474/?format=api
{ "id": 798474, "url": "http://patchwork.ozlabs.org/api/patches/798474/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1502075236-24078-5-git-send-email-qiang.zhao@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1502075236-24078-5-git-send-email-qiang.zhao@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1502075236-24078-5-git-send-email-qiang.zhao@nxp.com/", "date": "2017-08-07T03:07:16", "name": "[v10,4/4] irqchip/qeic: remove PPCisms for QEIC", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "c667d16c42272b662272f40f621b8dbc83f75b3a", "submitter": { "id": 68014, "url": "http://patchwork.ozlabs.org/api/people/68014/?format=api", "name": "Qiang Zhao", "email": "qiang.zhao@nxp.com" }, "delegate": { "id": 1707, "url": "http://patchwork.ozlabs.org/api/users/1707/?format=api", "username": "scottwood", "first_name": "Scott", "last_name": "Wood", "email": "scottwood@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1502075236-24078-5-git-send-email-qiang.zhao@nxp.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/798474/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/798474/checks/", "tags": {}, "related": [], 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Frontend Transport; Mon, 7 Aug 2017 03:24:23 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv773NpO8014527; Sun, 6 Aug 2017 20:24:21 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Zhao Qiang <qiang.zhao@nxp.com>", "To": "<tglx@linutronix.de>", "Subject": "[PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC", "Date": "Mon, 7 Aug 2017 11:07:16 +0800", "Message-ID": "<1502075236-24078-5-git-send-email-qiang.zhao@nxp.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "In-Reply-To": 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"oss@buserror.net, Zhao Qiang <qiang.zhao@nxp.com>,\n\tlinuxppc-dev@lists.ozlabs.org, xiaobo.xie@nxp.com,\n\tlinux-kernel@vger.kernel.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "QEIC was supported on PowerPC, and dependent on PPC,\nNow it is supported on other platforms, so remove PPCisms.\n\nSigned-off-by: Zhao Qiang <qiang.zhao@nxp.com>\n---\n arch/powerpc/platforms/83xx/km83xx.c | 1 -\n arch/powerpc/platforms/83xx/misc.c | 1 -\n arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -\n arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -\n arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -\n arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -\n arch/powerpc/platforms/85xx/corenet_generic.c | 1 -\n arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -\n arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -\n arch/powerpc/platforms/85xx/twr_p102x.c | 1 -\n drivers/irqchip/irq-qeic.c | 188 +++++++++++---------------\n include/soc/fsl/qe/qe_ic.h | 132 ------------------\n 12 files changed, 80 insertions(+), 250 deletions(-)\n delete mode 100644 include/soc/fsl/qe/qe_ic.h", "diff": "diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c\nindex d8642a4..b1cef0a 100644\n--- a/arch/powerpc/platforms/83xx/km83xx.c\n+++ b/arch/powerpc/platforms/83xx/km83xx.c\n@@ -38,7 +38,6 @@\n #include <sysdev/fsl_soc.h>\n #include <sysdev/fsl_pci.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n \n #include \"mpc83xx.h\"\n \ndiff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c\nindex c09a135..07a0e61 100644\n--- a/arch/powerpc/platforms/83xx/misc.c\n+++ b/arch/powerpc/platforms/83xx/misc.c\n@@ -17,7 +17,6 @@\n #include <asm/io.h>\n #include <asm/hw_irq.h>\n #include <asm/ipic.h>\n-#include <soc/fsl/qe/qe_ic.h>\n #include <sysdev/fsl_soc.h>\n #include <sysdev/fsl_pci.h>\n \ndiff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c\nindex bb7b25a..a1cadf4 100644\n--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c\n+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c\n@@ -37,7 +37,6 @@\n #include <sysdev/fsl_soc.h>\n #include <sysdev/fsl_pci.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n \n #include \"mpc83xx.h\"\n \ndiff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c\nindex d7c9b18..6c66527 100644\n--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c\n+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c\n@@ -26,7 +26,6 @@\n #include <asm/ipic.h>\n #include <asm/udbg.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n #include <sysdev/fsl_soc.h>\n #include <sysdev/fsl_pci.h>\n \ndiff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c\nindex 4fc3051..9234d63 100644\n--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c\n+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c\n@@ -45,7 +45,6 @@\n #include <sysdev/fsl_pci.h>\n #include <sysdev/simple_gpio.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n \n #include \"mpc83xx.h\"\n \ndiff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c\nindex 93f024f..82fa344 100644\n--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c\n+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c\n@@ -21,7 +21,6 @@\n #include <asm/ipic.h>\n #include <asm/udbg.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n #include <sysdev/fsl_soc.h>\n #include <sysdev/fsl_pci.h>\n \ndiff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c\nindex 1b385ac..9ca27b1 100644\n--- a/arch/powerpc/platforms/85xx/corenet_generic.c\n+++ b/arch/powerpc/platforms/85xx/corenet_generic.c\n@@ -27,7 +27,6 @@\n #include <asm/udbg.h>\n #include <asm/mpic.h>\n #include <asm/ehv_pic.h>\n-#include <soc/fsl/qe/qe_ic.h>\n \n #include <linux/of_platform.h>\n #include <sysdev/fsl_soc.h>\ndiff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c\nindex 06f34a9..8102e5f 100644\n--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c\n+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c\n@@ -49,7 +49,6 @@\n #include <sysdev/fsl_pci.h>\n #include <sysdev/simple_gpio.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n #include <asm/mpic.h>\n #include <asm/swiotlb.h>\n #include \"smp.h\"\ndiff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c\nindex 000d385..f806b6b 100644\n--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c\n+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c\n@@ -27,7 +27,6 @@\n #include <asm/udbg.h>\n #include <asm/mpic.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n \n #include <sysdev/fsl_soc.h>\n #include <sysdev/fsl_pci.h>\ndiff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c\nindex 6be9b33..4f620f2 100644\n--- a/arch/powerpc/platforms/85xx/twr_p102x.c\n+++ b/arch/powerpc/platforms/85xx/twr_p102x.c\n@@ -23,7 +23,6 @@\n #include <asm/udbg.h>\n #include <asm/mpic.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n \n #include <sysdev/fsl_soc.h>\n #include <sysdev/fsl_pci.h>\ndiff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c\nindex a2d8084..26bfcbd 100644\n--- a/drivers/irqchip/irq-qeic.c\n+++ b/drivers/irqchip/irq-qeic.c\n@@ -18,8 +18,11 @@\n #include <linux/of_address.h>\n #include <linux/kernel.h>\n #include <linux/init.h>\n+#include <linux/irqdomain.h>\n #include <linux/irqchip.h>\n #include <linux/errno.h>\n+#include <linux/of_address.h>\n+#include <linux/of_irq.h>\n #include <linux/reboot.h>\n #include <linux/slab.h>\n #include <linux/stddef.h>\n@@ -27,9 +30,8 @@\n #include <linux/signal.h>\n #include <linux/device.h>\n #include <linux/spinlock.h>\n-#include <asm/irq.h>\n+#include <linux/irq.h>\n #include <asm/io.h>\n-#include <soc/fsl/qe/qe_ic.h>\n \n #define NR_QE_IC_INTS\t\t64\n \n@@ -87,6 +89,43 @@\n #define SIGNAL_HIGH\t\t2\n #define SIGNAL_LOW\t\t0\n \n+#define NUM_OF_QE_IC_GROUPS\t6\n+\n+/* Flags when we init the QE IC */\n+#define QE_IC_SPREADMODE_GRP_W\t\t\t0x00000001\n+#define QE_IC_SPREADMODE_GRP_X\t\t\t0x00000002\n+#define QE_IC_SPREADMODE_GRP_Y\t\t\t0x00000004\n+#define QE_IC_SPREADMODE_GRP_Z\t\t\t0x00000008\n+#define QE_IC_SPREADMODE_GRP_RISCA\t\t0x00000010\n+#define QE_IC_SPREADMODE_GRP_RISCB\t\t0x00000020\n+\n+#define QE_IC_LOW_SIGNAL\t\t\t0x00000100\n+#define QE_IC_HIGH_SIGNAL\t\t\t0x00000200\n+\n+#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH\t0x00001000\n+#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH\t0x00002000\n+#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH\t0x00004000\n+#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH\t0x00008000\n+#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH\t0x00010000\n+#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH\t0x00020000\n+#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH\t0x00040000\n+#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH\t0x00080000\n+#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH\t0x00100000\n+#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH\t0x00200000\n+#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH\t0x00400000\n+#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH\t0x00800000\n+#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT\t\t(12)\n+\n+/* QE interrupt sources groups */\n+enum qe_ic_grp_id {\n+\tQE_IC_GRP_W = 0,\t/* QE interrupt controller group W */\n+\tQE_IC_GRP_X,\t\t/* QE interrupt controller group X */\n+\tQE_IC_GRP_Y,\t\t/* QE interrupt controller group Y */\n+\tQE_IC_GRP_Z,\t\t/* QE interrupt controller group Z */\n+\tQE_IC_GRP_RISCA,\t/* QE interrupt controller RISC group A */\n+\tQE_IC_GRP_RISCB\t\t/* QE interrupt controller RISC group B */\n+};\n+\n struct qe_ic {\n \t/* Control registers offset */\n \tu32 __iomem *regs;\n@@ -265,15 +304,15 @@ static struct qe_ic_info qe_ic_info[] = {\n \t\t},\n };\n \n-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)\n+static u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)\n {\n-\treturn in_be32(base + (reg >> 2));\n+\treturn ioread32be(base + (reg >> 2));\n }\n \n-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,\n+static void qe_ic_write(__be32 __iomem *base, unsigned int reg,\n \t\t\t u32 value)\n {\n-\tout_be32(base + (reg >> 2), value);\n+\tiowrite32be(value, base + (reg >> 2));\n }\n \n static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)\n@@ -375,8 +414,8 @@ static const struct irq_domain_ops qe_ic_host_ops = {\n \t.xlate = irq_domain_xlate_onetwocell,\n };\n \n-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */\n-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)\n+/* Return an interrupt vector or 0 if no interrupt is pending. */\n+static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)\n {\n \tint irq;\n \n@@ -386,13 +425,13 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)\n \tirq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;\n \n \tif (irq == 0)\n-\t\treturn NO_IRQ;\n+\t\treturn 0;\n \n \treturn irq_linear_revmap(qe_ic->irqhost, irq);\n }\n \n-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */\n-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)\n+/* Return an interrupt vector or 0 if no interrupt is pending. */\n+static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)\n {\n \tint irq;\n \n@@ -402,11 +441,38 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)\n \tirq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;\n \n \tif (irq == 0)\n-\t\treturn NO_IRQ;\n+\t\treturn 0;\n \n \treturn irq_linear_revmap(qe_ic->irqhost, irq);\n }\n \n+static void qe_ic_cascade_mpic(struct irq_desc *desc, int is_high)\n+{\n+\tstruct qe_ic *qe_ic = irq_desc_get_handler_data(desc);\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tunsigned int cascade_irq;\n+\n+\tif (is_high)\n+\t\tcascade_irq = qe_ic_get_high_irq(qe_ic);\n+\telse\n+\t\tcascade_irq = qe_ic_get_low_irq(qe_ic);\n+\n+\tif (cascade_irq != 0)\n+\t\tgeneric_handle_irq(cascade_irq);\n+\n+\tchip->irq_eoi(&desc->irq_data);\n+}\n+\n+static void qe_ic_cascade_low_mpic(struct irq_desc *desc)\n+{\n+\tqe_ic_cascade_mpic(desc, 0);\n+}\n+\n+static void qe_ic_cascade_high_mpic(struct irq_desc *desc)\n+{\n+\tqe_ic_cascade_mpic(desc, 1);\n+}\n+\n static int __init qe_ic_init(struct device_node *node, unsigned int flags)\n {\n \tstruct qe_ic *qe_ic;\n@@ -443,7 +509,7 @@ static int __init qe_ic_init(struct device_node *node, unsigned int flags)\n \tqe_ic->virq_high = irq_of_parse_and_map(node, 0);\n \tqe_ic->virq_low = irq_of_parse_and_map(node, 1);\n \n-\tif (qe_ic->virq_low == NO_IRQ) {\n+\tif (qe_ic->virq_low == 0) {\n \t\tpr_err(\"Failed to map QE_IC low IRQ\\n\");\n \t\tret = -ENOMEM;\n \t\tgoto err_domain_remove;\n@@ -475,7 +541,7 @@ static int __init qe_ic_init(struct device_node *node, unsigned int flags)\n \tirq_set_handler_data(qe_ic->virq_low, qe_ic);\n \tirq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);\n \n-\tif (qe_ic->virq_high != NO_IRQ &&\n+\tif (qe_ic->virq_high != 0 &&\n \t\t\tqe_ic->virq_high != qe_ic->virq_low) {\n \t\tirq_set_handler_data(qe_ic->virq_high, qe_ic);\n \t\tirq_set_chained_handler(qe_ic->virq_high,\n@@ -493,100 +559,6 @@ static int __init qe_ic_init(struct device_node *node, unsigned int flags)\n \treturn ret;\n }\n \n-void qe_ic_set_highest_priority(unsigned int virq, int high)\n-{\n-\tstruct qe_ic *qe_ic = qe_ic_from_irq(virq);\n-\tunsigned int src = virq_to_hw(virq);\n-\tu32 temp = 0;\n-\n-\ttemp = qe_ic_read(qe_ic->regs, QEIC_CICR);\n-\n-\ttemp &= ~CICR_HP_MASK;\n-\ttemp |= src << CICR_HP_SHIFT;\n-\n-\ttemp &= ~CICR_HPIT_MASK;\n-\ttemp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;\n-\n-\tqe_ic_write(qe_ic->regs, QEIC_CICR, temp);\n-}\n-\n-/* Set Priority level within its group, from 1 to 8 */\n-int qe_ic_set_priority(unsigned int virq, unsigned int priority)\n-{\n-\tstruct qe_ic *qe_ic = qe_ic_from_irq(virq);\n-\tunsigned int src = virq_to_hw(virq);\n-\tu32 temp;\n-\n-\tif (priority > 8 || priority == 0)\n-\t\treturn -EINVAL;\n-\tif (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),\n-\t\t \"%s: Invalid hw irq number for QEIC\\n\", __func__))\n-\t\treturn -EINVAL;\n-\tif (qe_ic_info[src].pri_reg == 0)\n-\t\treturn -EINVAL;\n-\n-\ttemp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);\n-\n-\tif (priority < 4) {\n-\t\ttemp &= ~(0x7 << (32 - priority * 3));\n-\t\ttemp |= qe_ic_info[src].pri_code << (32 - priority * 3);\n-\t} else {\n-\t\ttemp &= ~(0x7 << (24 - priority * 3));\n-\t\ttemp |= qe_ic_info[src].pri_code << (24 - priority * 3);\n-\t}\n-\n-\tqe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);\n-\n-\treturn 0;\n-}\n-\n-/* Set a QE priority to use high irq, only priority 1~2 can use high irq */\n-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)\n-{\n-\tstruct qe_ic *qe_ic = qe_ic_from_irq(virq);\n-\tunsigned int src = virq_to_hw(virq);\n-\tu32 temp, control_reg = QEIC_CICNR, shift = 0;\n-\n-\tif (priority > 2 || priority == 0)\n-\t\treturn -EINVAL;\n-\tif (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),\n-\t\t \"%s: Invalid hw irq number for QEIC\\n\", __func__))\n-\t\treturn -EINVAL;\n-\n-\tswitch (qe_ic_info[src].pri_reg) {\n-\tcase QEIC_CIPZCC:\n-\t\tshift = CICNR_ZCC1T_SHIFT;\n-\t\tbreak;\n-\tcase QEIC_CIPWCC:\n-\t\tshift = CICNR_WCC1T_SHIFT;\n-\t\tbreak;\n-\tcase QEIC_CIPYCC:\n-\t\tshift = CICNR_YCC1T_SHIFT;\n-\t\tbreak;\n-\tcase QEIC_CIPXCC:\n-\t\tshift = CICNR_XCC1T_SHIFT;\n-\t\tbreak;\n-\tcase QEIC_CIPRTA:\n-\t\tshift = CRICR_RTA1T_SHIFT;\n-\t\tcontrol_reg = QEIC_CRICR;\n-\t\tbreak;\n-\tcase QEIC_CIPRTB:\n-\t\tshift = CRICR_RTB1T_SHIFT;\n-\t\tcontrol_reg = QEIC_CRICR;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tshift += (2 - priority) * 2;\n-\ttemp = qe_ic_read(qe_ic->regs, control_reg);\n-\ttemp &= ~(SIGNAL_MASK << shift);\n-\ttemp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;\n-\tqe_ic_write(qe_ic->regs, control_reg, temp);\n-\n-\treturn 0;\n-}\n-\n static int __init init_qe_ic(struct device_node *node,\n \t\t\t struct device_node *parent)\n {\ndiff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h\ndeleted file mode 100644\nindex 6113699..0000000\n--- a/include/soc/fsl/qe/qe_ic.h\n+++ /dev/null\n@@ -1,132 +0,0 @@\n-/*\n- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.\n- *\n- * Authors: \tShlomi Gridish <gridish@freescale.com>\n- * \t\tLi Yang <leoli@freescale.com>\n- *\n- * Description:\n- * QE IC external definitions and structure.\n- *\n- * This program is free software; you can redistribute it and/or modify it\n- * under the terms of the GNU General Public License as published by the\n- * Free Software Foundation; either version 2 of the License, or (at your\n- * option) any later version.\n- */\n-#ifndef _ASM_POWERPC_QE_IC_H\n-#define _ASM_POWERPC_QE_IC_H\n-\n-#include <linux/irq.h>\n-\n-struct device_node;\n-struct qe_ic;\n-\n-#define NUM_OF_QE_IC_GROUPS\t6\n-\n-/* Flags when we init the QE IC */\n-#define QE_IC_SPREADMODE_GRP_W\t\t\t0x00000001\n-#define QE_IC_SPREADMODE_GRP_X\t\t\t0x00000002\n-#define QE_IC_SPREADMODE_GRP_Y\t\t\t0x00000004\n-#define QE_IC_SPREADMODE_GRP_Z\t\t\t0x00000008\n-#define QE_IC_SPREADMODE_GRP_RISCA\t\t0x00000010\n-#define QE_IC_SPREADMODE_GRP_RISCB\t\t0x00000020\n-\n-#define QE_IC_LOW_SIGNAL\t\t\t0x00000100\n-#define QE_IC_HIGH_SIGNAL\t\t\t0x00000200\n-\n-#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH\t0x00001000\n-#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH\t0x00002000\n-#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH\t0x00004000\n-#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH\t0x00008000\n-#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH\t0x00010000\n-#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH\t0x00020000\n-#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH\t0x00040000\n-#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH\t0x00080000\n-#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH\t0x00100000\n-#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH\t0x00200000\n-#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH\t0x00400000\n-#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH\t0x00800000\n-#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT\t\t(12)\n-\n-/* QE interrupt sources groups */\n-enum qe_ic_grp_id {\n-\tQE_IC_GRP_W = 0,\t/* QE interrupt controller group W */\n-\tQE_IC_GRP_X,\t\t/* QE interrupt controller group X */\n-\tQE_IC_GRP_Y,\t\t/* QE interrupt controller group Y */\n-\tQE_IC_GRP_Z,\t\t/* QE interrupt controller group Z */\n-\tQE_IC_GRP_RISCA,\t/* QE interrupt controller RISC group A */\n-\tQE_IC_GRP_RISCB\t\t/* QE interrupt controller RISC group B */\n-};\n-\n-#ifdef CONFIG_QUICC_ENGINE\n-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);\n-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);\n-#else\n-static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)\n-{ return 0; }\n-static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)\n-{ return 0; }\n-#endif /* CONFIG_QUICC_ENGINE */\n-\n-void qe_ic_set_highest_priority(unsigned int virq, int high);\n-int qe_ic_set_priority(unsigned int virq, unsigned int priority);\n-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);\n-\n-static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)\n-{\n-\tstruct qe_ic *qe_ic = irq_desc_get_handler_data(desc);\n-\tunsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);\n-\n-\tif (cascade_irq != NO_IRQ)\n-\t\tgeneric_handle_irq(cascade_irq);\n-}\n-\n-static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)\n-{\n-\tstruct qe_ic *qe_ic = irq_desc_get_handler_data(desc);\n-\tunsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);\n-\n-\tif (cascade_irq != NO_IRQ)\n-\t\tgeneric_handle_irq(cascade_irq);\n-}\n-\n-static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)\n-{\n-\tstruct qe_ic *qe_ic = irq_desc_get_handler_data(desc);\n-\tunsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);\n-\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\n-\tif (cascade_irq != NO_IRQ)\n-\t\tgeneric_handle_irq(cascade_irq);\n-\n-\tchip->irq_eoi(&desc->irq_data);\n-}\n-\n-static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)\n-{\n-\tstruct qe_ic *qe_ic = irq_desc_get_handler_data(desc);\n-\tunsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);\n-\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\n-\tif (cascade_irq != NO_IRQ)\n-\t\tgeneric_handle_irq(cascade_irq);\n-\n-\tchip->irq_eoi(&desc->irq_data);\n-}\n-\n-static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)\n-{\n-\tstruct qe_ic *qe_ic = irq_desc_get_handler_data(desc);\n-\tunsigned int cascade_irq;\n-\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\n-\tcascade_irq = qe_ic_get_high_irq(qe_ic);\n-\tif (cascade_irq == NO_IRQ)\n-\t\tcascade_irq = qe_ic_get_low_irq(qe_ic);\n-\n-\tif (cascade_irq != NO_IRQ)\n-\t\tgeneric_handle_irq(cascade_irq);\n-\n-\tchip->irq_eoi(&desc->irq_data);\n-}\n-\n-#endif /* _ASM_POWERPC_QE_IC_H */\n", "prefixes": [ "v10", "4/4" ] }