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GET /api/patches/798471/?format=api
{ "id": 798471, "url": "http://patchwork.ozlabs.org/api/patches/798471/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1502075236-24078-2-git-send-email-qiang.zhao@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1502075236-24078-2-git-send-email-qiang.zhao@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1502075236-24078-2-git-send-email-qiang.zhao@nxp.com/", "date": "2017-08-07T03:07:13", "name": "[v10,1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "3bafd7d9970c852dc023c080bbfdf18b94875a31", "submitter": { "id": 68014, "url": "http://patchwork.ozlabs.org/api/people/68014/?format=api", "name": "Qiang Zhao", "email": "qiang.zhao@nxp.com" }, "delegate": { "id": 1707, "url": "http://patchwork.ozlabs.org/api/users/1707/?format=api", "username": "scottwood", "first_name": "Scott", "last_name": "Wood", "email": "scottwood@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1502075236-24078-2-git-send-email-qiang.zhao@nxp.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/798471/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/798471/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xQjcr0JZ2z9s7g\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 7 Aug 2017 13:26:52 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xQjcq6XfQzDqty\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 7 Aug 2017 13:26:51 +1000 (AEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0049.outbound.protection.outlook.com [104.47.41.49])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xQjYq5VB9zDqp0\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tMon, 7 Aug 2017 13:24:15 +1000 (AEST)", "from BN6PR03CA0015.namprd03.prod.outlook.com (10.168.230.153) by\n\tCY1PR0301MB0906.namprd03.prod.outlook.com (10.160.165.17) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.1.1304.22; Mon, 7 Aug 2017 03:24:07 +0000", "from BY2FFO11FD012.protection.gbl (2a01:111:f400:7c0c::159) by\n\tBN6PR03CA0015.outlook.office365.com (2603:10b6:404:23::25) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1320.16\n\tvia Frontend Transport; Mon, 7 Aug 2017 03:24:06 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11FD012.mail.protection.outlook.com (10.1.14.130) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1304.16\n\tvia Frontend Transport; Mon, 7 Aug 2017 03:24:06 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv773NpO5014527; Sun, 6 Aug 2017 20:24:03 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Zhao Qiang <qiang.zhao@nxp.com>", "To": "<tglx@linutronix.de>", "Subject": "[PATCH v10 1/4] irqchip/qeic: move qeic driver from\n\tdrivers/soc/fsl/qe", "Date": "Mon, 7 Aug 2017 11:07:13 +0800", "Message-ID": "<1502075236-24078-2-git-send-email-qiang.zhao@nxp.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "In-Reply-To": "<1502075236-24078-1-git-send-email-qiang.zhao@nxp.com>", "References": "<1502075236-24078-1-git-send-email-qiang.zhao@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131465498463583285;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(336005)(39860400002)(39450400003)(39840400002)(39380400002)(39850400002)(39400400002)(39410400002)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(97736004)(48376002)(626005)(8676002)(189998001)(50226002)(81166006)(81156014)(8936002)(5003940100001)(47776003)(86362001)(575784001)(104016004)(2906002)(68736007)(2950100002)(76176999)(50986999)(53936002)(6666003)(54906002)(356003)(106466001)(77096006)(2351001)(6916009)(110136004)(38730400002)(33646002)(36756003)(50466002)(8656003)(5660300001)(4326008)(305945005)(85426001)(105606002)(498600001)(2004002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR0301MB0906;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; ", "X-Microsoft-Exchange-Diagnostics": [ "=?us-ascii?Q?1; BY2FFO11FD012;\n\t1:7kHzIrWN8vAbTar6U+xb17rTWZNTpBs8ukp+lqR9Z9?=\n\t=?us-ascii?Q?mB1oSc6CfXPcce+c5Zoc2GwGp1H51JOEi93rKSD/nXqdwl5hzM2Ka/Al9HfL?=\n\t=?us-ascii?Q?V5fwESIFDziTNoQWTNox+Q19vdsHZFWgq4RSCf69LezRSBFxjgUuzDi2zaWh?=\n\t=?us-ascii?Q?s0KIdw2YoROM35iMRPKU217QPt3tKrEgLnjPdmQ0SGNcK7HY5t9OI3+7+qIQ?=\n\t=?us-ascii?Q?fwo0a44zzaDkoOmUOamB48mIK6Hs8e7B+P1G8nvxHyFXN7P6mdVq+zT1A8St?=\n\t=?us-ascii?Q?j/2k1/r2EJh4yut+E4u+qoIP0eMwvGyynu67ZCZWMl/H6hFecLKNbBf4iswe?=\n\t=?us-ascii?Q?SdKRGoziEk/WmsbSWJqHIGj/XcNR4BnlOJiw9PvQwBi52usX7A1l7EVk0GHz?=\n\t=?us-ascii?Q?/UmXUhyIrjTdR6psaljWLZ3PGee2o96lLkHoNOUi1SZG585ABni3jJCcqsGI?=\n\t=?us-ascii?Q?Gi/GZtTCDbRMog9jjra+Pvd38S2Eqsl84ufTbbYC9bsOu2GuIYjJdGBOUO+S?=\n\t=?us-ascii?Q?pOzY6U36qzkIboxbfKvrDOTDpboabi+ONvckh+UKYqRZbF7EQCcJinPGZQdD?=\n\t=?us-ascii?Q?bkqhFY9A1qxCrf5N2eI9KejnDelgZ0HEykeY3UvFku9j1mJHkZNH8ucRGCZ8?=\n\t=?us-ascii?Q?jNbSKNRzHLYCOIFA/w31bya4vsV4T7ppmZVFeVC/U2RQzrMrNNC6j45j4o26?=\n\t=?us-ascii?Q?nFvCHYvBgr9rNjm7ZGny/PDlZ6untSiCaP7wHpqYseOTlmalnplvNY1KL9Sj?=\n\t=?us-ascii?Q?Qiimy4hX4lA+/KhfQOqwqK1vidIY9lhKTmap/Cmu2TbSf9+KRyN6d52T5C/L?=\n\t=?us-ascii?Q?zEq0T8KyEZd5soEF+4GvLj8lRwt7nmbwPdm5rV1QMjMrpZmQX8vSOhe8hGdO?=\n\t=?us-ascii?Q?vz1r2g4y1l4uMUmLklufEyO7v+vxwpTo1QfYbsXJtuf5o5Ow4uFkvq4E7NqC?=\n\t=?us-ascii?Q?VVoFAGuzQtwL90e9KhN9akx1TD/5ZaY0fbZGPfBw=3D=3D?=", "1; CY1PR0301MB0906;\n\t3:QDQzDFpodPrKnPmbnVUL84rAFYqPLclZe1BAMgZd6GBS+9aCdUyPz9NEJQcyq4cT8rlZeIDaIT7WsZ7iNaFhtuqU6dl1Bovx0F2T19WDqiLU0zKA2/gxCocjfrxUZwjqu5MVCKWvP6u4dZNHUqFfef3D9Dbd0JkDqQacziS0z1iWLWRnvyjX3j0S2Sbi8YiLdWAgXk+Kk/nPwME2zQ66oRFJyG7s+sf4g2R2yarxmGZ6vV2MgQRlmXzHOCdVSUFSK6WkTqpEwknYMKFqoIcBhJgcBUIAy+xqJLPUX+lokkx9CIZDbLqWP9ZZSJa6OdAeJA2JszPBzYgUZ9YmBXWklEXRGqP00tA7whGzx69kEe8=;\n\t25:W+ZeCkMGomdEBTLeZGSZFmqh6sbDORVjQFC3XFWyKwVwP/VaFzRs4+nYrH/7bKMfCabi38PHLHiXk8BLRahU9AwyZnzi9u6O11hvUjV7jbh6MdG0SgpWou5Nxs7XEhMtysS+CzJ7MepVQPozFHs8dkslDPG2jEuqWfNbIbIEEWitRLHfB+ZrBmflHzg1QeXy0qoFWpAN3v36CtKlwtO4eonOfE0Fj60U7YZ3OaDgjw1yAnIaF6Ic/XW1NOprMXjyofkeo1zcTFsYO6A2p+u09Hc0GrLOMWO42C/4kS7DAuW9sTBAjaAgElk4qVZ17VZ+iNAML92qvWZtV58FxR2oBg==", "1; CY1PR0301MB0906;\n\t31:RyuY3H4l4OtQP7AT48njcp374cl1DgIlvMBDM/HRaisrqIhyJ5Lcug8GH4AarXVxs4+r9x/hCLlx8CJRcQDV5RuFgdtI4yhbwHPgVRLg/LuD2owbO4lFKS6gMxa31s30xYb+Shmlj149JYJFbv2Nfy/LJ5lCsu9R5ezpc3hucyEiaTwJtce9gxK5f/hgQBzwHfhjDoWJp2MznNMBADIjSqMPu6PVn5n42XCXPvXKg1U=;\n\t4:mp4qXlYFTrukYvzP8zqdaDpADirDCPFZdN7wUT32LBbuMaXxqaTJe9fV4aZWOJxj3kaSmy4OrQVPJyZHKwU2Pn1LVRgAAdmKaVxohJWCF+dPn3+r5kKlmeBBbJSR+hVllc4mPOGlUjVKzrwYoGWHtoDVRgbCC7N/gpN8Lu4tYV3yjkVDwg0DF0UREGw6lT9Ues6zK8RQjXbLiWxw/Y32ao2/Zq3fhDm5OPV+P91/cNeU7Cn0/Iml5JbNbedw09xTsApUG59lAo2qiNn/5boF5b2pAW4jm3HlGDtD19w7EdyKqHFpbxrNhYUU+Sw6gevFJPOBuPW912kL7hj/CA2S1z5ySIjtN1FdqImGrn7cuX4=", "=?us-ascii?Q?1; CY1PR0301MB0906;\n\t23:tYimXSU6+xuG3MrH3/cagxEdElz097VLSf8+Peo?=\n\t=?us-ascii?Q?X8tbKzr9h0UsJvA8VVq9ux+vh3nloQK7uS27BpuAdqgzFG8/WUpQmICPHbr/?=\n\t=?us-ascii?Q?fm3dh8FulZTeiEy0Q5kO9Eo3/dtdk2+x+4Y2HFa+UNFawm8OrhKUIlRyvyER?=\n\t=?us-ascii?Q?iid88mmQlfmVnP0CRzcUjpaGW3m9zj33kp9YFJJHgILk4LTeeGNxRp0Krenc?=\n\t=?us-ascii?Q?7GWDwZj8HA9iuqta1IDshZ6ED2FICFRmiunOg41kSv8Z3XGvFi95lw0bZKxk?=\n\t=?us-ascii?Q?NORtl6mtAROU4phdxH1Lju7Lwxgsxol7z2TWC0mDoY1ky3VwomP233WErkGW?=\n\t=?us-ascii?Q?kJgndGJ6RsAsG2sVFsWdklZYsOWI++XppU4AMvWcLLxCpDw5Wy26PE8sABRv?=\n\t=?us-ascii?Q?7CzQcl6BwmY6k7ECbgrhJDgv+lXjR2pZB1j2k1HMgzscPwLRp2smLW63xCNd?=\n\t=?us-ascii?Q?rC2iitc9xkTLhfDZ3iXhpJLgkFq575XcDY7BFhr8A5VM5bj7mxW0oiI5AVGp?=\n\t=?us-ascii?Q?r6G46NbIfUn2Zu9ZLENSZ2D5TXD6UC1peTZbOzSyNLrLAIDr6y7vbBxgqNTB?=\n\t=?us-ascii?Q?9fRrapZqMzDAFlH3pE8jlCXPSFqpL493uny7si1/860bIhBcS26tXYRPo26Q?=\n\t=?us-ascii?Q?FTqhsTRzUqISVk+GT1LOcilw9JuXq0aKvSJiaVHA8kyJb4gjCkebL/FeYNlw?=\n\t=?us-ascii?Q?sGDqUBNB5l1MvjwZQJ+RpIYJbpYVWnN1riye9mpg/JYR/MVL3PllXp6mdRHS?=\n\t=?us-ascii?Q?QxYBvCTwdBt+19bpAQv6eujbuuBpmtnW2iVMhshd2skLFdAGnAAKKJU03H/O?=\n\t=?us-ascii?Q?rCy74tJTJc32kgeD8fHUKXWJSo5R+6rQGOlCfIGxJoyAN8Xirqn+2cJGWR0q?=\n\t=?us-ascii?Q?pDtSFEX7KcvYrAQAfNpWgThWUApOusbjknlaKEkQtjVmqjTpEgCBdpSFykPV?=\n\t=?us-ascii?Q?B5IzSY5GfIjeZMz/jlvMO/os/idI05f4d4qUA3eWZMynOvwESaSYyBPRMM1B?=\n\t=?us-ascii?Q?Frbq4Tq8xp7MbCuMRU5YXCmIimHNLZD/S7MZsyhPDlelAZ4BP24+Cbq/EqOm?=\n\t=?us-ascii?Q?MumI7t7XsAg23rWF+j9onBOMWfG4OCkoYc8LgVRHkeKh1VFvmBtr81apGsgM?=\n\t=?us-ascii?Q?DlQCFdUHWg19Lmg7DpGXKLzR9pcIVXChcLFKx32h/f0T5q94Fi9YKwCcJt17?=\n\t=?us-ascii?Q?N5bRTYqN6UHD0FQ4qQQHguJzNAJe9D54Wcyfr1qyxN+S/TPuT0TzuHLc8Izl?=\n\t=?us-ascii?Q?9m9K/ihWaGwFHCszbhP1B0li4cn97pub8cq+RhjcmSyrTIKXUD6bTL3RV5cB?=\n\t=?us-ascii?Q?dZXy5ha39DgxMhrLHshypktsjox4c5NywzT0bnYEDfHrS?=", "1; CY1PR0301MB0906;\n\t6:i0TCDceCTXdv4sG/Vxq/dzxVwV0ZJbKZX2miykKNhnGHaCVetFsC12S+Syz60UtCB8KUlkaOkI0J60DNkkZM3Jt6imsR26JsckFH+uutkBORbeqX/ce4bJyB12wiS5nFK6xdCpso7O/En3ifiZe3SqL1gVrSt4j5zqBjYjxED2DZzN/wilpvNSVCPkgeu4wWjmqyWiL5K4duZF9s9yRtvlaMN3bPy2SaISynivn73+JWTTx7QYfKu0njyJjKS1hmhVNaJaABsjDKf4fpCYZFNb+IMM+/M21m1JUu9l8v66xaYECUTU6RXKLKB6GynzmOpaxHwxVyefHEHJb02LCOhw==;\n\t5:EqRAZYON03CScQlKte2Sb8w6A+JsvqaXlU0x4chqE6RmfLeT4C5B3JNThr3pidclXm7xdn4WcrFPxWUC5BITddhecP/FuLaHQ9fdO4L3TV81pEqcvVduKwbsFx1Oxk4EATnUFevP1sJV1kU57QxBmA==;\n\t24:IMUOckYHh/HhjqK1KocFXaZKZbB9evifzSw5z+alJuGhQSOCZuT+FMMiTIdnTvzqf9nF56QTP9UYCV22rzRqvrL+wBweRbaXgrwSb52lsk0=;\n\t7:VQ63DZPAN6D8mFyAUs824kAnpTFa6V6LB+IFXn/t39dkCzPR+EsilAiOux4wog4qOYJe2PYduBynLWPaKS1uA4d4pGoD5viBp+pfQU7Z09O7Ak8WQvBaHWdcprVDP24IyzIVjsoHLmKUlnHDjhjMgvDyvpvxicqep/lnBGDsfqryaSiNIfJPlPm0dh2sK2gfhqjMx7RzkJRVwB+gSTNkMedrejsVZVr5f7wqZzONT1w=" ], "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b5a61361-4ba2-4438-3c35-08d4dd43c29b", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(2017052603031)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:CY1PR0301MB0906; ", "X-MS-TrafficTypeDiagnostic": "CY1PR0301MB0906:", "X-Exchange-Antispam-Report-Test": "UriScan:(9452136761055)(185117386973197)(101931422205132); ", "X-Microsoft-Antispam-PRVS": "<CY1PR0301MB09068A53B483EEA56497339391B50@CY1PR0301MB0906.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(601004)(2401047)(5005006)(13016025)(8121501046)(13018025)(93006095)(93001095)(10201501046)(3002001)(100000703101)(100105400095)(6055026)(6096035)(20161123563025)(20161123559100)(201703131430075)(201703131448075)(201703131433075)(201703161259150)(201703151042153)(20161123565025)(20161123556025)(20161123561025)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:CY1PR0301MB0906; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY1PR0301MB0906; ", "X-Forefront-PRVS": "0392679D18", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Aug 2017 03:24:06.1555\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR0301MB0906", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "oss@buserror.net, Zhao Qiang <qiang.zhao@nxp.com>,\n\tlinuxppc-dev@lists.ozlabs.org, xiaobo.xie@nxp.com,\n\tlinux-kernel@vger.kernel.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "move the driver from drivers/soc/fsl/qe to drivers/irqchip,\nmerge qe_ic.h and qe_ic.c into irq-qeic.c.\n\nSigned-off-by: Zhao Qiang <qiang.zhao@nxp.com>\n---\n MAINTAINERS | 6 ++\n drivers/irqchip/Makefile | 1 +\n drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 95 ++++++++++++++++++-\n drivers/soc/fsl/qe/Makefile | 2 +-\n drivers/soc/fsl/qe/qe_ic.h | 103 ---------------------\n 5 files changed, 100 insertions(+), 107 deletions(-)\n rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (85%)\n delete mode 100644 drivers/soc/fsl/qe/qe_ic.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 567343b..1288329 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -5462,6 +5462,12 @@ F:\tdrivers/soc/fsl/qe/\n F:\tinclude/soc/fsl/*qe*.h\n F:\tinclude/soc/fsl/*ucc*.h\n \n+FREESCALE QEIC DRIVERS\n+M:\tQiang Zhao <qiang.zhao@nxp.com>\n+L:\tlinux-kernel@vger.kernel.org\n+S:\tMaintained\n+F:\tdrivers/irqchip/irq-qeic.c\n+\n FREESCALE QUICC ENGINE UCC ETHERNET DRIVER\n M:\tLi Yang <leoyang.li@nxp.com>\n L:\tnetdev@vger.kernel.org\ndiff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile\nindex e88d856..b8eae87 100644\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC)\t\t\t+= irq-eznps.o\n obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o irq-aspeed-i2c-ic.o\n obj-$(CONFIG_STM32_EXTI) \t\t+= irq-stm32-exti.o\n obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\n+obj-$(CONFIG_QUICC_ENGINE)\t\t+= irq-qeic.o\ndiff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c\nsimilarity index 85%\nrename from drivers/soc/fsl/qe/qe_ic.c\nrename to drivers/irqchip/irq-qeic.c\nindex ec2ca86..9b4660c 100644\n--- a/drivers/soc/fsl/qe/qe_ic.c\n+++ b/drivers/irqchip/irq-qeic.c\n@@ -1,7 +1,7 @@\n /*\n- * arch/powerpc/sysdev/qe_lib/qe_ic.c\n+ * drivers/irqchip/irq-qeic.c\n *\n- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.\n *\n * Author: Li Yang <leoli@freescale.com>\n * Based on code from Shlomi Gridish <gridish@freescale.com>\n@@ -30,7 +30,96 @@\n #include <asm/io.h>\n #include <soc/fsl/qe/qe_ic.h>\n \n-#include \"qe_ic.h\"\n+#define NR_QE_IC_INTS\t\t64\n+\n+/* QE IC registers offset */\n+#define QEIC_CICR\t\t0x00\n+#define QEIC_CIVEC\t\t0x04\n+#define QEIC_CRIPNR\t\t0x08\n+#define QEIC_CIPNR\t\t0x0c\n+#define QEIC_CIPXCC\t\t0x10\n+#define QEIC_CIPYCC\t\t0x14\n+#define QEIC_CIPWCC\t\t0x18\n+#define QEIC_CIPZCC\t\t0x1c\n+#define QEIC_CIMR\t\t0x20\n+#define QEIC_CRIMR\t\t0x24\n+#define QEIC_CICNR\t\t0x28\n+#define QEIC_CIPRTA\t\t0x30\n+#define QEIC_CIPRTB\t\t0x34\n+#define QEIC_CRICR\t\t0x3c\n+#define QEIC_CHIVEC\t\t0x60\n+\n+/* Interrupt priority registers */\n+#define CIPCC_SHIFT_PRI0\t29\n+#define CIPCC_SHIFT_PRI1\t26\n+#define CIPCC_SHIFT_PRI2\t23\n+#define CIPCC_SHIFT_PRI3\t20\n+#define CIPCC_SHIFT_PRI4\t13\n+#define CIPCC_SHIFT_PRI5\t10\n+#define CIPCC_SHIFT_PRI6\t7\n+#define CIPCC_SHIFT_PRI7\t4\n+\n+/* CICR priority modes */\n+#define CICR_GWCC\t\t0x00040000\n+#define CICR_GXCC\t\t0x00020000\n+#define CICR_GYCC\t\t0x00010000\n+#define CICR_GZCC\t\t0x00080000\n+#define CICR_GRTA\t\t0x00200000\n+#define CICR_GRTB\t\t0x00400000\n+#define CICR_HPIT_SHIFT\t\t8\n+#define CICR_HPIT_MASK\t\t0x00000300\n+#define CICR_HP_SHIFT\t\t24\n+#define CICR_HP_MASK\t\t0x3f000000\n+\n+/* CICNR */\n+#define CICNR_WCC1T_SHIFT\t20\n+#define CICNR_ZCC1T_SHIFT\t28\n+#define CICNR_YCC1T_SHIFT\t12\n+#define CICNR_XCC1T_SHIFT\t4\n+\n+/* CRICR */\n+#define CRICR_RTA1T_SHIFT\t20\n+#define CRICR_RTB1T_SHIFT\t28\n+\n+/* Signal indicator */\n+#define SIGNAL_MASK\t\t3\n+#define SIGNAL_HIGH\t\t2\n+#define SIGNAL_LOW\t\t0\n+\n+struct qe_ic {\n+\t/* Control registers offset */\n+\tu32 __iomem *regs;\n+\n+\t/* The remapper for this QEIC */\n+\tstruct irq_domain *irqhost;\n+\n+\t/* The \"linux\" controller struct */\n+\tstruct irq_chip hc_irq;\n+\n+\t/* VIRQ numbers of QE high/low irqs */\n+\tunsigned int virq_high;\n+\tunsigned int virq_low;\n+};\n+\n+/*\n+ * QE interrupt controller internal structure\n+ */\n+struct qe_ic_info {\n+\t/* location of this source at the QIMR register. */\n+\tu32\tmask;\n+\n+\t/* Mask register offset */\n+\tu32\tmask_reg;\n+\n+\t/*\n+\t * for grouped interrupts sources - the interrupt\n+\t * code as appears at the group priority register\n+\t */\n+\tu8\tpri_code;\n+\n+\t/* Group priority register offset */\n+\tu32\tpri_reg;\n+};\n \n static DEFINE_RAW_SPINLOCK(qe_ic_lock);\n \ndiff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile\nindex 2031d38..51e4726 100644\n--- a/drivers/soc/fsl/qe/Makefile\n+++ b/drivers/soc/fsl/qe/Makefile\n@@ -1,7 +1,7 @@\n #\n # Makefile for the linux ppc-specific parts of QE\n #\n-obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o\n+obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_io.o\n obj-$(CONFIG_CPM)\t+= qe_common.o\n obj-$(CONFIG_UCC)\t+= ucc.o\n obj-$(CONFIG_UCC_SLOW)\t+= ucc_slow.o\ndiff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h\ndeleted file mode 100644\nindex 926a2ed..0000000\n--- a/drivers/soc/fsl/qe/qe_ic.h\n+++ /dev/null\n@@ -1,103 +0,0 @@\n-/*\n- * drivers/soc/fsl/qe/qe_ic.h\n- *\n- * QUICC ENGINE Interrupt Controller Header\n- *\n- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.\n- *\n- * Author: Li Yang <leoli@freescale.com>\n- * Based on code from Shlomi Gridish <gridish@freescale.com>\n- *\n- * This program is free software; you can redistribute it and/or modify it\n- * under the terms of the GNU General Public License as published by the\n- * Free Software Foundation; either version 2 of the License, or (at your\n- * option) any later version.\n- */\n-#ifndef _POWERPC_SYSDEV_QE_IC_H\n-#define _POWERPC_SYSDEV_QE_IC_H\n-\n-#include <soc/fsl/qe/qe_ic.h>\n-\n-#define NR_QE_IC_INTS\t\t64\n-\n-/* QE IC registers offset */\n-#define QEIC_CICR\t\t0x00\n-#define QEIC_CIVEC\t\t0x04\n-#define QEIC_CRIPNR\t\t0x08\n-#define QEIC_CIPNR\t\t0x0c\n-#define QEIC_CIPXCC\t\t0x10\n-#define QEIC_CIPYCC\t\t0x14\n-#define QEIC_CIPWCC\t\t0x18\n-#define QEIC_CIPZCC\t\t0x1c\n-#define QEIC_CIMR\t\t0x20\n-#define QEIC_CRIMR\t\t0x24\n-#define QEIC_CICNR\t\t0x28\n-#define QEIC_CIPRTA\t\t0x30\n-#define QEIC_CIPRTB\t\t0x34\n-#define QEIC_CRICR\t\t0x3c\n-#define QEIC_CHIVEC\t\t0x60\n-\n-/* Interrupt priority registers */\n-#define CIPCC_SHIFT_PRI0\t29\n-#define CIPCC_SHIFT_PRI1\t26\n-#define CIPCC_SHIFT_PRI2\t23\n-#define CIPCC_SHIFT_PRI3\t20\n-#define CIPCC_SHIFT_PRI4\t13\n-#define CIPCC_SHIFT_PRI5\t10\n-#define CIPCC_SHIFT_PRI6\t7\n-#define CIPCC_SHIFT_PRI7\t4\n-\n-/* CICR priority modes */\n-#define CICR_GWCC\t\t0x00040000\n-#define CICR_GXCC\t\t0x00020000\n-#define CICR_GYCC\t\t0x00010000\n-#define CICR_GZCC\t\t0x00080000\n-#define CICR_GRTA\t\t0x00200000\n-#define CICR_GRTB\t\t0x00400000\n-#define CICR_HPIT_SHIFT\t\t8\n-#define CICR_HPIT_MASK\t\t0x00000300\n-#define CICR_HP_SHIFT\t\t24\n-#define CICR_HP_MASK\t\t0x3f000000\n-\n-/* CICNR */\n-#define CICNR_WCC1T_SHIFT\t20\n-#define CICNR_ZCC1T_SHIFT\t28\n-#define CICNR_YCC1T_SHIFT\t12\n-#define CICNR_XCC1T_SHIFT\t4\n-\n-/* CRICR */\n-#define CRICR_RTA1T_SHIFT\t20\n-#define CRICR_RTB1T_SHIFT\t28\n-\n-/* Signal indicator */\n-#define SIGNAL_MASK\t\t3\n-#define SIGNAL_HIGH\t\t2\n-#define SIGNAL_LOW\t\t0\n-\n-struct qe_ic {\n-\t/* Control registers offset */\n-\tvolatile u32 __iomem *regs;\n-\n-\t/* The remapper for this QEIC */\n-\tstruct irq_domain *irqhost;\n-\n-\t/* The \"linux\" controller struct */\n-\tstruct irq_chip hc_irq;\n-\n-\t/* VIRQ numbers of QE high/low irqs */\n-\tunsigned int virq_high;\n-\tunsigned int virq_low;\n-};\n-\n-/*\n- * QE interrupt controller internal structure\n- */\n-struct qe_ic_info {\n-\tu32\tmask;\t /* location of this source at the QIMR register. */\n-\tu32\tmask_reg; /* Mask register offset */\n-\tu8\tpri_code; /* for grouped interrupts sources - the interrupt\n-\t\t\t code as appears at the group priority register */\n-\tu32\tpri_reg; /* Group priority register offset */\n-};\n-\n-#endif /* _POWERPC_SYSDEV_QE_IC_H */\n", "prefixes": [ "v10", "1/4" ] }