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GET /api/patches/796038/?format=api
{ "id": 796038, "url": "http://patchwork.ozlabs.org/api/patches/796038/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/patch/20170801010425.25778-1-andrew@aj.id.au/", "project": { "id": 56, "url": "http://patchwork.ozlabs.org/api/projects/56/?format=api", "name": "OpenBMC development", "link_name": "openbmc", "list_id": "openbmc.lists.ozlabs.org", "list_email": "openbmc@lists.ozlabs.org", "web_url": "http://github.com/openbmc/", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170801010425.25778-1-andrew@aj.id.au>", "list_archive_url": null, "date": "2017-08-01T01:04:25", "name": "watchdog: wdt_aspeed: Add support for the reset width register", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ff5d9dd120340f66f207b51e5c4f2aa0c051fdf7", "submitter": { "id": 68332, "url": "http://patchwork.ozlabs.org/api/people/68332/?format=api", "name": "Andrew Jeffery", "email": "andrew@aj.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openbmc/patch/20170801010425.25778-1-andrew@aj.id.au/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/796038/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/796038/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xLym90BD8z9tWj\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 1 Aug 2017 11:05:13 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xLym83m4TzDrHT\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 1 Aug 2017 11:05:12 +1000 (AEST)", "from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com\n\t[66.111.4.25])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xLylx2f6KzDr2y\n\tfor <openbmc@lists.ozlabs.org>; Tue, 1 Aug 2017 11:05:01 +1000 (AEST)", "from compute4.internal (compute4.nyi.internal [10.202.2.44])\n\tby mailout.nyi.internal (Postfix) with ESMTP id EE88820774;\n\tMon, 31 Jul 2017 21:04:58 -0400 (EDT)", "from frontend2 ([10.202.2.161])\n\tby compute4.internal (MEProxy); Mon, 31 Jul 2017 21:04:58 -0400", "from keelia.au.ibm.com\n\t(ppp118-210-176-216.bras2.adl6.internode.on.net [118.210.176.216])\n\tby mail.messagingengine.com (Postfix) with ESMTPA id 18F4624604;\n\tMon, 31 Jul 2017 21:04:55 -0400 (EDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=aj.id.au header.i=@aj.id.au header.b=\"NGbswFBk\";\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com header.b=\"KOdZRttc\"; \n\tdkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=aj.id.au header.i=@aj.id.au header.b=\"NGbswFBk\";\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com header.b=\"KOdZRttc\"; \n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=aj.id.au header.i=@aj.id.au header.b=\"NGbswFBk\";\n\tdkim=pass (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com\n\theader.b=\"KOdZRttc\"; dkim-atps=neutral" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc\n\t:date:from:message-id:subject:to:x-me-sender:x-me-sender\n\t:x-sasl-enc:x-sasl-enc; s=fm1; bh=I1691WBr92xTPpnV9ROVgEHnl2VH5e\n\tpIO4BQtBbcP70=; b=NGbswFBkj4ktUx3msNwJAOb2SHNWiIIhPzF7026H1lQ1wx\n\t3TnaoN7+iEQ7431sNjF1UPZpjV3ds5ZtClNxkdn2AlheE5uekZsYuySllJLMfIgy\n\tNK1RCZUPB9TfV7s98RsorJcGQFQwOEwUqZsslXlKC+ojQ++UZHl6GVmjhnDq/dL0\n\tEcDbsazIyWLdIdCiQMemXP0g29PSv7bLsp4RYIWAKXwbZ5O5AWqQZvGVX0Zt/z61\n\thfAiYQkUHzfvLtED29B2G59rwFOnqfAiMhcFwqhwUxbrDl2+TJ9jnlk1m8q9RN+f\n\t6LRyp1P3FgJlLs1dvuWLB4LWWBudCAg34tShD6cQ==", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=\n\tmessagingengine.com; h=cc:date:from:message-id:subject:to\n\t:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=I1691W\n\tBr92xTPpnV9ROVgEHnl2VH5epIO4BQtBbcP70=; b=KOdZRttcgVuLi++CnMTJt4\n\tJ5VjZL6l74kwKrFwadivTSGhZHPoGO8N1ut5lHrTGJLBG2WTZQAO4NsU22u5WxU7\n\tbfkY4zeUqbfzcSrpPCteOtZKtc5fdg078Mw9FwQLa/XM722TkRxCzE60zBFaRlsE\n\tKel/5Hgd5P2QWBKDtFTQhR8GKQ3mUcMso3Nrs2DUj3WjX85xvZUJZW6iDBJ7BcbV\n\tEfltp2fwTPLy05yCv6OnwSCWnDkgrdgrMbCoYTh75MDh3r/hhhbg80X/3STWsJxK\n\tPieDekpdjr91MXWpM7GcesegsjGA2kSpLpBvnNLX/madboG3Cit0DpIHuo7vG82A\n\t==" ], "X-ME-Sender": "<xms:utN_WdZoUuCYpZB2tvHDfmrvxUTNxhR_Szn6fSqltD3iYhEJ2WZdUg>", "X-Sasl-enc": "1Jk5tillm/lewo4YH0LXbJShF+dYi0nccB97rrsx6Ay5 1501549498", "From": "Andrew Jeffery <andrew@aj.id.au>", "To": "qemu-arm@nongnu.org", "Subject": "[PATCH] watchdog: wdt_aspeed: Add support for the reset width\n\tregister", "Date": "Tue, 1 Aug 2017 10:34:25 +0930", "Message-Id": "<20170801010425.25778-1-andrew@aj.id.au>", "X-Mailer": "git-send-email 2.11.0", "X-BeenThere": "openbmc@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Development list for OpenBMC <openbmc.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/openbmc/>", "List-Post": "<mailto:openbmc@lists.ozlabs.org>", "List-Help": "<mailto:openbmc-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Andrew Jeffery <andrew@aj.id.au>,\n\topenbmc@lists.ozlabs.org, qemu-devel@nongnu.org, clg@kaod.org", "Errors-To": "openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"openbmc\"\n\t<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "The reset width register controls how the pulse on the SoC's WDTRST{1,2}\npins behaves. A pulse is emitted if the external reset bit is set in\nWDT_CTRL. WDT_RESET_WIDTH requires magic bit patterns to configure both\npush-pull/open-drain and active-high/active-low behaviours and thus\nneeds some special handling in the write path.\n\nSigned-off-by: Andrew Jeffery <andrew@aj.id.au>\n---\nI understand that we're in stabilisation mode, but I thought I'd send this out\nto provoke any feedback. Happy to resend after the 2.10 release if required.\n\n hw/watchdog/wdt_aspeed.c | 47 +++++++++++++++++++++++++++++++++++++----------\n 1 file changed, 37 insertions(+), 10 deletions(-)", "diff": "diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c\nindex 8bbe579b6b66..4ef1412e99fc 100644\n--- a/hw/watchdog/wdt_aspeed.c\n+++ b/hw/watchdog/wdt_aspeed.c\n@@ -14,10 +14,10 @@\n #include \"qemu/timer.h\"\n #include \"hw/watchdog/wdt_aspeed.h\"\n \n-#define WDT_STATUS (0x00 / 4)\n-#define WDT_RELOAD_VALUE (0x04 / 4)\n-#define WDT_RESTART (0x08 / 4)\n-#define WDT_CTRL (0x0C / 4)\n+#define WDT_STATUS (0x00 / 4)\n+#define WDT_RELOAD_VALUE (0x04 / 4)\n+#define WDT_RESTART (0x08 / 4)\n+#define WDT_CTRL (0x0C / 4)\n #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)\n #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)\n #define WDT_CTRL_1MHZ_CLK BIT(4)\n@@ -25,12 +25,21 @@\n #define WDT_CTRL_WDT_INTR BIT(2)\n #define WDT_CTRL_RESET_SYSTEM BIT(1)\n #define WDT_CTRL_ENABLE BIT(0)\n+#define WDT_RESET_WIDTH (0x18 / 4)\n+#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)\n+#define WDT_POLARITY_MASK (0xFF << 24)\n+#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)\n+#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)\n+#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)\n+#define WDT_DRIVE_TYPE_MASK (0xFF << 24)\n+#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)\n+#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)\n+#define WDT_RESET_WIDTH_DURATION 0xFFF;\n \n-#define WDT_TIMEOUT_STATUS (0x10 / 4)\n-#define WDT_TIMEOUT_CLEAR (0x14 / 4)\n-#define WDT_RESET_WDITH (0x18 / 4)\n+#define WDT_TIMEOUT_STATUS (0x10 / 4)\n+#define WDT_TIMEOUT_CLEAR (0x14 / 4)\n \n-#define WDT_RESTART_MAGIC 0x4755\n+#define WDT_RESTART_MAGIC 0x4755\n \n static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)\n {\n@@ -55,9 +64,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)\n return 0;\n case WDT_CTRL:\n return s->regs[WDT_CTRL];\n+ case WDT_RESET_WIDTH:\n+ return s->regs[WDT_RESET_WIDTH];\n case WDT_TIMEOUT_STATUS:\n case WDT_TIMEOUT_CLEAR:\n- case WDT_RESET_WDITH:\n qemu_log_mask(LOG_UNIMP,\n \"%s: uninmplemented read at offset 0x%\" HWADDR_PRIx \"\\n\",\n __func__, offset);\n@@ -119,9 +129,25 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,\n timer_del(s->timer);\n }\n break;\n+ case WDT_RESET_WIDTH:\n+ {\n+ uint32_t property = data & WDT_POLARITY_MASK;\n+\n+ if (property == WDT_ACTIVE_HIGH_MAGIC) {\n+ s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;\n+ } else if (property == WDT_ACTIVE_LOW_MAGIC) {\n+ s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;\n+ } else if (property == WDT_PUSH_PULL_MAGIC) {\n+ s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;\n+ } else if (property == WDT_OPEN_DRAIN_MAGIC) {\n+ s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;\n+ }\n+ s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_DURATION;\n+ s->regs[WDT_RESET_WIDTH] |= data & WDT_RESET_WIDTH_DURATION;\n+ break;\n+ }\n case WDT_TIMEOUT_STATUS:\n case WDT_TIMEOUT_CLEAR:\n- case WDT_RESET_WDITH:\n qemu_log_mask(LOG_UNIMP,\n \"%s: uninmplemented write at offset 0x%\" HWADDR_PRIx \"\\n\",\n __func__, offset);\n@@ -167,6 +193,7 @@ static void aspeed_wdt_reset(DeviceState *dev)\n s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;\n s->regs[WDT_RESTART] = 0;\n s->regs[WDT_CTRL] = 0;\n+ s->regs[WDT_RESET_WIDTH] = 0XFF;\n \n timer_del(s->timer);\n }\n", "prefixes": [] }