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GET /api/patches/783382/?format=api
{ "id": 783382, "url": "http://patchwork.ozlabs.org/api/patches/783382/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1499074673-30576-5-git-send-email-anju@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1499074673-30576-5-git-send-email-anju@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1499074673-30576-5-git-send-email-anju@linux.vnet.ibm.com/", "date": "2017-07-03T09:37:50", "name": "[v12,04/10] powerpc/perf: Add generic IMC pmu group and event functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cf87e4a7c964324ec277856aa94a66def7598d3c", "submitter": { "id": 67491, "url": "http://patchwork.ozlabs.org/api/people/67491/?format=api", "name": "Anju T Sudhakar", "email": "anju@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1499074673-30576-5-git-send-email-anju@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/783382/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/783382/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3x1Mg51vc4z9rxl\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 3 Jul 2017 19:44:49 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3x1Mg518p2zDrLV\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 3 Jul 2017 19:44:49 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3x1MWb2BNHzDr4L\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tMon, 3 Jul 2017 19:38:19 +1000 (AEST)", "from pps.filterd (m0098419.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id\n\tv639XeWh132623\n\tfor <linuxppc-dev@lists.ozlabs.org>; Mon, 3 Jul 2017 05:38:17 -0400", "from e23smtp01.au.ibm.com (e23smtp01.au.ibm.com [202.81.31.143])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2bfk9vrby8-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Mon, 03 Jul 2017 05:38:16 -0400", "from localhost\n\tby e23smtp01.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from <anju@linux.vnet.ibm.com>;\n\tMon, 3 Jul 2017 19:38:14 +1000", "from d23relay09.au.ibm.com (202.81.31.228)\n\tby e23smtp01.au.ibm.com (202.81.31.207) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tMon, 3 Jul 2017 19:38:11 +1000", "from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97])\n\tby d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv639cBXd56557612\n\tfor <linuxppc-dev@lists.ozlabs.org>; Mon, 3 Jul 2017 19:38:11 +1000", "from d23av03.au.ibm.com (localhost [127.0.0.1])\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv639c2Fs028061\n\tfor <linuxppc-dev@lists.ozlabs.org>; Mon, 3 Jul 2017 19:38:03 +1000", "from xenial-xerus.in.ibm.com (xenial-xerus.in.ibm.com [9.124.35.20]\n\t(may be forged))\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tv639bkFR027271; Mon, 3 Jul 2017 19:37:59 +1000" ], "From": "Anju T Sudhakar <anju@linux.vnet.ibm.com>", "To": "mpe@ellerman.id.au", "Subject": "[PATCH v12 04/10] powerpc/perf: Add generic IMC pmu group and event\n\tfunctions", "Date": "Mon, 3 Jul 2017 15:07:50 +0530", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1499074673-30576-1-git-send-email-anju@linux.vnet.ibm.com>", "References": "<1499074673-30576-1-git-send-email-anju@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "x-cbid": "17070309-1617-0000-0000-000001F0CF14", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17070309-1618-0000-0000-00004838159E", "Message-Id": "<1499074673-30576-5-git-send-email-anju@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-07-03_06:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=4\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000\n\tdefinitions=main-1707030160", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "stewart@linux.vnet.ibm.com, ego@linux.vnet.ibm.com, mikey@neuling.org,\n\tmaddy@linux.vnet.ibm.com, hemant@linux.vnet.ibm.com,\n\tlinux-kernel@vger.kernel.org, eranian@google.com,\n\tanju@linux.vnet.ibm.com, anton@samba.org, sukadev@linux.vnet.ibm.com,\n\tlinuxppc-dev@lists.ozlabs.org, dja@axtens.net", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Device tree IMC driver code parses the IMC units and their events. It\npasses the information to IMC pmu code which is placed in powerpc/perf\nas \"imc-pmu.c\".\n\nPatch adds a set of generic imc pmu related event functions to be\nused by each imc pmu unit. Add code to setup format attribute and to\nregister imc pmus. Add a event_init function for nest_imc events.\n\nSince, the IMC counters' data are periodically fed to a memory location,\nthe functions to read/update, start/stop, add/del can be generic and can\nbe used by all IMC PMU units.\n\nSigned-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>\nSigned-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com>\nSigned-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>\n---\n arch/powerpc/include/asm/imc-pmu.h | 5 +\n arch/powerpc/perf/Makefile | 3 +\n arch/powerpc/perf/imc-pmu.c | 283 ++++++++++++++++++++++++++++++\n arch/powerpc/platforms/powernv/opal-imc.c | 11 +-\n 4 files changed, 300 insertions(+), 2 deletions(-)\n create mode 100644 arch/powerpc/perf/imc-pmu.c", "diff": "diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h\nindex 2a0239e2590d..25d0c57d14fe 100644\n--- a/arch/powerpc/include/asm/imc-pmu.h\n+++ b/arch/powerpc/include/asm/imc-pmu.h\n@@ -63,6 +63,9 @@ struct imc_events {\n #define IMC_CPUMASK_ATTR\t1\n #define IMC_EVENT_ATTR\t\t2\n #define IMC_NULL_ATTR\t\t3\n+#define IMC_EVENT_OFFSET_MASK\t0xffffffffULL\n+#define IMC_EVENT_RVALUE_MASK\t0x100000000ULL\n+#define IMC_NEST_EVENT_MODE\t0x1fe00000000ULL\n \n /*\n * Device tree parser code detects IMC pmu support and\n@@ -101,4 +104,6 @@ enum {\n */\n #define IMC_DOMAIN_NEST\t\t1\n \n+extern struct imc_pmu *per_nest_pmu_arr[IMC_MAX_PMUS];\n+extern int init_imc_pmu(struct imc_events *events, int idx, struct imc_pmu *pmu_ptr);\n #endif /* PPC_POWERNV_IMC_PMU_DEF_H */\ndiff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile\nindex 4d606b99a5cb..b29d918814d3 100644\n--- a/arch/powerpc/perf/Makefile\n+++ b/arch/powerpc/perf/Makefile\n@@ -6,6 +6,9 @@ obj-$(CONFIG_PPC_PERF_CTRS)\t+= core-book3s.o bhrb.o\n obj64-$(CONFIG_PPC_PERF_CTRS)\t+= power4-pmu.o ppc970-pmu.o power5-pmu.o \\\n \t\t\t\t power5+-pmu.o power6-pmu.o power7-pmu.o \\\n \t\t\t\t isa207-common.o power8-pmu.o power9-pmu.o\n+\n+obj-$(CONFIG_HV_PERF_IMC_CTRS)\t+= imc-pmu.o\n+\n obj32-$(CONFIG_PPC_PERF_CTRS)\t+= mpc7450-pmu.o\n \n obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o\ndiff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c\nnew file mode 100644\nindex 000000000000..4e2f837b8bb7\n--- /dev/null\n+++ b/arch/powerpc/perf/imc-pmu.c\n@@ -0,0 +1,283 @@\n+/*\n+ * Nest Performance Monitor counter support.\n+ *\n+ * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.\n+ * (C) 2017 Anju T Sudhakar, IBM Corporation.\n+ * (C) 2017 Hemant K Shaw, IBM Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version\n+ * 2 of the License, or later version.\n+ */\n+#include <linux/perf_event.h>\n+#include <linux/slab.h>\n+#include <asm/opal.h>\n+#include <asm/imc-pmu.h>\n+#include <asm/cputhreads.h>\n+#include <asm/smp.h>\n+#include <linux/string.h>\n+\n+/* Needed for sanity check */\n+struct imc_pmu *per_nest_pmu_arr[IMC_MAX_PMUS];\n+\n+struct imc_pmu *imc_event_to_pmu(struct perf_event *event)\n+{\n+\treturn container_of(event->pmu, struct imc_pmu, pmu);\n+}\n+\n+PMU_FORMAT_ATTR(event, \"config:0-47\");\n+PMU_FORMAT_ATTR(offset, \"config:0-31\");\n+PMU_FORMAT_ATTR(rvalue, \"config:32\");\n+PMU_FORMAT_ATTR(mode, \"config:33-40\");\n+static struct attribute *nest_imc_format_attrs[] = {\n+\t&format_attr_event.attr,\n+\t&format_attr_offset.attr,\n+\t&format_attr_rvalue.attr,\n+\t&format_attr_mode.attr,\n+\tNULL,\n+};\n+\n+static struct attribute_group imc_format_group = {\n+\t.name = \"format\",\n+\t.attrs = nest_imc_format_attrs,\n+};\n+\n+static int nest_imc_event_init(struct perf_event *event)\n+{\n+\tint chip_id;\n+\tu32 l_config, config = event->attr.config;\n+\tstruct imc_mem_info *pcni;\n+\tstruct imc_pmu *pmu;\n+\tbool flag = false;\n+\n+\tif (event->attr.type != event->pmu->type)\n+\t\treturn -ENOENT;\n+\n+\t/* Sampling not supported */\n+\tif (event->hw.sample_period)\n+\t\treturn -EINVAL;\n+\n+\t/* unsupported modes and filters */\n+\tif (event->attr.exclude_user ||\n+\t event->attr.exclude_kernel ||\n+\t event->attr.exclude_hv ||\n+\t event->attr.exclude_idle ||\n+\t event->attr.exclude_host ||\n+\t event->attr.exclude_guest)\n+\t\treturn -EINVAL;\n+\n+\tif (event->cpu < 0)\n+\t\treturn -EINVAL;\n+\n+\tpmu = imc_event_to_pmu(event);\n+\n+\t/*\n+\t * Sanity check for config (event offset, mode and rvalue).\n+\t * mode and rvalue should be zero, if not just return.\n+\t */\n+\tif (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size) ||\n+\t ((config & IMC_EVENT_RVALUE_MASK) != 0) ||\n+\t ((config & IMC_NEST_EVENT_MODE) != 0))\n+\t\treturn -EINVAL;\n+\n+\tchip_id = topology_physical_package_id(event->cpu);\n+\tpcni = pmu->mem_info;\n+\tdo {\n+\t\tif (pcni->id == chip_id) {\n+\t\t\tflag = true;\n+\t\t\tbreak;\n+\t\t}\n+\t\tpcni++;\n+\t} while (pcni);\n+\n+\tif (!flag)\n+\t\treturn -ENODEV;\n+\n+\t/*\n+\t * Memory for Nest HW counter data could be in multiple pages.\n+\t * Hence check and pick the right event base page for chip with\n+\t * \"chip_id\" and add \"config\" to it\".\n+\t */\n+\tl_config = config & IMC_EVENT_OFFSET_MASK;\n+\tevent->hw.event_base = (u64)pcni->vbase[l_config/PAGE_SIZE] +\n+\t\t\t (l_config & ~PAGE_MASK);\n+\treturn 0;\n+}\n+\n+static void imc_read_counter(struct perf_event *event)\n+{\n+\tu64 *addr, data;\n+\n+\t/*\n+\t * In-Memory Collection (IMC) counters are free flowing counters.\n+\t * So we take a snapshot of the counter value on enable and save it\n+\t * to calculate the delta at later stage to present the event counter\n+\t * value.\n+\t */\n+\taddr = (u64 *)event->hw.event_base;\n+\tdata = __be64_to_cpu(READ_ONCE(*addr));\n+\tlocal64_set(&event->hw.prev_count, data);\n+}\n+\n+static void imc_perf_event_update(struct perf_event *event)\n+{\n+\tu64 counter_prev, counter_new, final_count, *addr;\n+\n+\taddr = (u64 *)event->hw.event_base;\n+\tcounter_prev = local64_read(&event->hw.prev_count);\n+\tcounter_new = __be64_to_cpu(READ_ONCE(*addr));\n+\tfinal_count = counter_new - counter_prev;\n+\n+\t/*\n+\t * Need to update prev_count is that, counter could be\n+\t * read in a periodic interval from the tool side.\n+\t */\n+\tlocal64_set(&event->hw.prev_count, counter_new);\n+\t/* Update the delta to the event count */\n+\tlocal64_add(final_count, &event->count);\n+}\n+\n+static void imc_event_start(struct perf_event *event, int flags)\n+{\n+\t/*\n+\t * In Memory Counters are free flowing counters. HW or the microcode\n+\t * keeps adding to the counter offset in memory. To get event\n+\t * counter value, we snapshot the value here and we calculate\n+\t * delta at later point.\n+\t */\n+\timc_read_counter(event);\n+}\n+\n+static void imc_event_stop(struct perf_event *event, int flags)\n+{\n+\t/*\n+\t * Take a snapshot and calculate the delta and update\n+\t * the event counter values.\n+\t */\n+\timc_perf_event_update(event);\n+}\n+\n+static int imc_event_add(struct perf_event *event, int flags)\n+{\n+\tif (flags & PERF_EF_START)\n+\t\timc_event_start(event, flags);\n+\n+\treturn 0;\n+}\n+\n+/* update_pmu_ops : Populate the appropriate operations for \"pmu\" */\n+static int update_pmu_ops(struct imc_pmu *pmu)\n+{\n+\tif (!pmu)\n+\t\treturn -EINVAL;\n+\n+\tpmu->pmu.task_ctx_nr = perf_invalid_context;\n+\tpmu->pmu.event_init = nest_imc_event_init;\n+\tpmu->pmu.add = imc_event_add;\n+\tpmu->pmu.del = imc_event_stop;\n+\tpmu->pmu.start = imc_event_start;\n+\tpmu->pmu.stop = imc_event_stop;\n+\tpmu->pmu.read = imc_perf_event_update;\n+\tpmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;\n+\tpmu->pmu.attr_groups = pmu->attr_groups;\n+\n+\treturn 0;\n+}\n+\n+/* dev_str_attr : Populate event \"name\" and string \"str\" in attribute */\n+static struct attribute *dev_str_attr(const char *name, const char *str)\n+{\n+\tstruct perf_pmu_events_attr *attr;\n+\n+\tattr = kzalloc(sizeof(*attr), GFP_KERNEL);\n+\tif (!attr)\n+\t\treturn NULL;\n+\tsysfs_attr_init(&attr->attr.attr);\n+\n+\tattr->event_str = str;\n+\tattr->attr.attr.name = name;\n+\tattr->attr.attr.mode = 0444;\n+\tattr->attr.show = perf_event_sysfs_show;\n+\n+\treturn &attr->attr.attr;\n+}\n+\n+/*\n+ * update_events_in_group: Update the \"events\" information in an attr_group\n+ * and assign the attr_group to the pmu \"pmu\".\n+ */\n+static int update_events_in_group(struct imc_events *events,\n+\t\t\t\t int idx, struct imc_pmu *pmu)\n+{\n+\tstruct attribute_group *attr_group;\n+\tstruct attribute **attrs;\n+\tint i;\n+\n+\t/* If there is no events for this pmu, just return zero */\n+\tif (!events)\n+\t\treturn 0;\n+\n+\t/* Allocate memory for attribute group */\n+\tattr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);\n+\tif (!attr_group)\n+\t\treturn -ENOMEM;\n+\n+\t/* Allocate memory for attributes */\n+\tattrs = kzalloc((sizeof(struct attribute *) * (idx + 1)), GFP_KERNEL);\n+\tif (!attrs) {\n+\t\tkfree(attr_group);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tattr_group->name = \"events\";\n+\tattr_group->attrs = attrs;\n+\tfor (i = 0; i < idx; i++, events++) {\n+\t\tattrs[i] = dev_str_attr((char *)events->ev_name,\n+\t\t\t\t\t(char *)events->ev_value);\n+\t}\n+\n+\t/* Save the event attribute */\n+\tpmu->attr_groups[IMC_EVENT_ATTR] = attr_group;\n+\treturn 0;\n+}\n+\n+/*\n+ * init_imc_pmu : Setup and register the IMC pmu device.\n+ *\n+ * @events:\tevents memory for this pmu.\n+ * @idx:\tnumber of event entries created.\n+ * @pmu_ptr:\tmemory allocated for this pmu.\n+ */\n+int init_imc_pmu(struct imc_events *events, int idx,\n+\t\t struct imc_pmu *pmu_ptr)\n+{\n+\tint ret;\n+\n+\tret = update_events_in_group(events, idx, pmu_ptr);\n+\tif (ret)\n+\t\tgoto err_free;\n+\n+\tret = update_pmu_ops(pmu_ptr);\n+\tif (ret)\n+\t\tgoto err_free;\n+\n+\tret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);\n+\tif (ret)\n+\t\tgoto err_free;\n+\n+\tpr_info(\"%s performance monitor hardware support registered\\n\",\n+\t\tpmu_ptr->pmu.name);\n+\n+\treturn 0;\n+\n+err_free:\n+\t/* Only free the attr_groups which are dynamically allocated */\n+\tif (pmu_ptr->attr_groups[IMC_EVENT_ATTR]) {\n+\t\tif (pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs)\n+\t\t\tkfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);\n+\t\tkfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);\n+\t}\n+\n+\treturn ret;\n+}\ndiff --git a/arch/powerpc/platforms/powernv/opal-imc.c b/arch/powerpc/platforms/powernv/opal-imc.c\nindex 839c25718110..a68d66d1ddb1 100644\n--- a/arch/powerpc/platforms/powernv/opal-imc.c\n+++ b/arch/powerpc/platforms/powernv/opal-imc.c\n@@ -34,8 +34,6 @@\n #include <asm/cputable.h>\n #include <asm/imc-pmu.h>\n \n-struct imc_pmu *per_nest_pmu_arr[IMC_MAX_PMUS];\n-\n static int imc_event_prop_update(char *name, struct imc_events *events)\n {\n \tchar *buf;\n@@ -452,8 +450,17 @@ static int imc_pmu_create(struct device_node *parent, int pmu_index, int domain)\n \t\tif (prop)\n \t\t\timc_events_setup(parent, pmu_index, pmu_ptr, prop, &idx);\n \t}\n+\t/* Function to register IMC pmu */\n+\tret = init_imc_pmu(pmu_ptr->events, idx, pmu_ptr);\n+\tif (ret) {\n+\t\tpr_err(\"IMC PMU %s Register failed\\n\", pmu_ptr->pmu.name);\n+\t\tgoto free_events;\n+\t}\n \treturn 0;\n \n+free_events:\n+\tif (pmu_ptr->events)\n+\t\timc_free_events(pmu_ptr->events, idx);\n free_pmu:\n \tif (pmu_ptr)\n \t\tkfree(pmu_ptr);\n", "prefixes": [ "v12", "04/10" ] }