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GET /api/patches/782084/?format=api
{ "id": 782084, "url": "http://patchwork.ozlabs.org/api/patches/782084/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170629071256.8159-4-oohall@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170629071256.8159-4-oohall@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170629071256.8159-4-oohall@gmail.com/", "date": "2017-06-29T07:12:55", "name": "[3/4] powerpc/smp: Add cpu_l2_cache_map", "commit_ref": "2a636a56d2d39676fe85190dec102c7440e24977", "pull_url": null, "state": "accepted", "archived": false, "hash": "9ac9dcea62579c65dc7cea90cb08b3234b6b75ff", "submitter": { "id": 68108, "url": "http://patchwork.ozlabs.org/api/people/68108/?format=api", "name": "Oliver O'Halloran", "email": "oohall@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170629071256.8159-4-oohall@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/782084/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/782084/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3wyrfQ13JKz9s75\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 29 Jun 2017 17:20:30 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3wyrfP6w51zDr5k\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 29 Jun 2017 17:20:29 +1000 (AEST)", "from mail-pf0-x242.google.com (mail-pf0-x242.google.com\n\t[IPv6:2607:f8b0:400e:c00::242])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3wyrV75XDczDr4s\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 29 Jun 2017 17:13:19 +1000 (AEST)", "by mail-pf0-x242.google.com with SMTP id z6so11985096pfk.3\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 29 Jun 2017 00:13:19 -0700 (PDT)", "from flat-canetoad.ozlabs.ibm.com ([122.99.82.10])\n\tby smtp.gmail.com with ESMTPSA id\n\ta29sm9821658pfg.30.2017.06.29.00.13.16\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 29 Jun 2017 00:13:17 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"VBxuWGpg\"; dkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"VBxuWGpg\"; dkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"VBxuWGpg\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=Ce9TVvYAaskb2WX9B0LJ33sOSFN7MmEEV4vKW88s43c=;\n\tb=VBxuWGpgT8VaDz99sILH2nxPIo+mTIH6wSrnrcVlQv+bYoWuVKHz5vr5kDcYUrpoqc\n\ta3Y6jp99nnYL79nqASgxB4pZwQtAwf7LK7g6978W6w+pIw8jRpdinmBSK0PmtRgUcNGc\n\tTa/lkTqZeiM1LBmJ6o7wcM2XiwFUR6nI1dHjDRAIPCugOVXSFYN8gfqXrkZoiIAG/T1B\n\tsJssrq3arwuGZjjofEePzu3kD70x4S/RslmFM62xRpCkyuyfpgpMSV/+qRyNSZ6Ia6yb\n\tWPsodWu8Ge7LP+ENVBu/YU5A0l+QZqPH+9LqkJdQIzPgvOeg+ftxxvX3rhyVeIzb0r1R\n\tuxhw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=Ce9TVvYAaskb2WX9B0LJ33sOSFN7MmEEV4vKW88s43c=;\n\tb=Z7TkFRofYRz7nEN2HEie59FsoRH0m42IiWQFpdXrXUu5ONqDqglSJ3Y0cT4cRfMt13\n\tumAs0hedTBKdz5LHYpyJsCiybCwS2cddh2Xhy+yvdmim5NCHZUVrTt2Zeafp8qdOD9aq\n\tOONL2MiKL+6RT9gBJlgZmid4RzR8bGXdfasYs7CffCWz1ryPsWejZs8vsWKsJa8s7mi8\n\ttoz8a+xF1wAufpXY8dsi7Y1t+SSG0vkHSEVY3g0RAx2SNFFD+uRJ/IMncSzgEs15z649\n\tJA4WJQ2B9j4zUzF2qUONZXiy96tErmSXeSi/uENM8sTI7N00wUINendgm5X7OoWZ1NXp\n\tKkog==", "X-Gm-Message-State": "AKS2vOzozYiSX8nHFBO2/bjCPA9q0u0zwAJ0nznZcl/Le+4QEaiF7vRr\n\t5+kH3kv7QEoeuRky", "X-Received": "by 10.99.117.11 with SMTP id q11mr14152486pgc.179.1498720398016; \n\tThu, 29 Jun 2017 00:13:18 -0700 (PDT)", "From": "Oliver O'Halloran <oohall@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 3/4] powerpc/smp: Add cpu_l2_cache_map", "Date": "Thu, 29 Jun 2017 17:12:55 +1000", "Message-Id": "<20170629071256.8159-4-oohall@gmail.com>", "X-Mailer": "git-send-email 2.9.4", "In-Reply-To": "<20170629071256.8159-1-oohall@gmail.com>", "References": "<20170629071256.8159-1-oohall@gmail.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "mikey@neuling.org, Oliver O'Halloran <oohall@gmail.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "We want to add an extra level to the CPU scheduler topology to account\nfor cores which share a cache. To do this we need to build a cpumask\nfor each CPU that indicates which CPUs share this cache to use as an\ninput to the scheduler.\n\nSigned-off-by: Oliver O'Halloran <oohall@gmail.com>\n---\n arch/powerpc/include/asm/smp.h | 6 ++++++\n arch/powerpc/kernel/smp.c | 23 +++++++++++++++++------\n 2 files changed, 23 insertions(+), 6 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h\nindex 8ea98504f900..fac963e10d39 100644\n--- a/arch/powerpc/include/asm/smp.h\n+++ b/arch/powerpc/include/asm/smp.h\n@@ -97,6 +97,7 @@ static inline void set_hard_smp_processor_id(int cpu, int phys)\n #endif\n \n DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);\n+DECLARE_PER_CPU(cpumask_var_t, cpu_l2_cache_map);\n DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);\n \n static inline struct cpumask *cpu_sibling_mask(int cpu)\n@@ -109,6 +110,11 @@ static inline struct cpumask *cpu_core_mask(int cpu)\n \treturn per_cpu(cpu_core_map, cpu);\n }\n \n+static inline struct cpumask *cpu_l2_cache_mask(int cpu)\n+{\n+\treturn per_cpu(cpu_l2_cache_map, cpu);\n+}\n+\n extern int cpu_to_core_id(int cpu);\n \n /* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.\ndiff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c\nindex 4c50f5fe5366..46f071cedf31 100644\n--- a/arch/powerpc/kernel/smp.c\n+++ b/arch/powerpc/kernel/smp.c\n@@ -74,9 +74,11 @@ static DEFINE_PER_CPU(int, cpu_state) = { 0 };\n struct thread_info *secondary_ti;\n \n DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);\n+DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map);\n DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);\n \n EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);\n+EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map);\n EXPORT_PER_CPU_SYMBOL(cpu_core_map);\n \n /* SMP operations for this machine */\n@@ -606,6 +608,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)\n \tfor_each_possible_cpu(cpu) {\n \t\tzalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu),\n \t\t\t\t\tGFP_KERNEL, cpu_to_node(cpu));\n+\t\tzalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu),\n+\t\t\t\t\tGFP_KERNEL, cpu_to_node(cpu));\n \t\tzalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu),\n \t\t\t\t\tGFP_KERNEL, cpu_to_node(cpu));\n \t\t/*\n@@ -620,6 +624,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)\n \n \t/* Init the cpumasks so the boot CPU is related to itself */\n \tcpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid));\n+\tcpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid));\n \tcpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid));\n \n \tif (smp_ops && smp_ops->probe)\n@@ -903,6 +908,7 @@ static void remove_cpu_from_masks(int cpu)\n \t/* NB: cpu_core_mask is a superset of the others */\n \tfor_each_cpu(i, cpu_core_mask(cpu)) {\n \t\tset_cpus_unrelated(cpu, i, cpu_core_mask);\n+\t\tset_cpus_unrelated(cpu, i, cpu_l2_cache_mask);\n \t\tset_cpus_unrelated(cpu, i, cpu_sibling_mask);\n \t}\n }\n@@ -924,17 +930,22 @@ static void add_cpu_to_masks(int cpu)\n \t\t\tset_cpus_related(i, cpu, cpu_sibling_mask);\n \n \t/*\n-\t * Copy the thread sibling into core sibling mask, and\n-\t * add CPUs that share a chip or an L2 to the core sibling\n-\t * mask.\n+\t * Copy the thread sibling mask into the cache sibling mask\n+\t * and mark any CPUs that share an L2 with this CPU.\n \t */\n \tfor_each_cpu(i, cpu_sibling_mask(cpu))\n+\t\tset_cpus_related(cpu, i, cpu_l2_cache_mask);\n+\tupdate_mask_by_l2(cpu, cpu_l2_cache_mask);\n+\n+\t/*\n+\t * Copy the cache sibling mask into core sibling mask and mark\n+\t * any CPUs on the same chip as this CPU.\n+\t */\n+\tfor_each_cpu(i, cpu_l2_cache_mask(cpu))\n \t\tset_cpus_related(cpu, i, cpu_core_mask);\n \n-\tif (chipid == -1) {\n-\t\tupdate_mask_by_l2(cpu, cpu_core_mask);\n+\tif (chipid == -1)\n \t\treturn;\n-\t}\n \n \tfor_each_cpu(i, cpu_online_mask)\n \t\tif (cpu_to_chip_id(i) == chipid)\n", "prefixes": [ "3/4" ] }