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GET /api/patches/781763/?format=api
{ "id": 781763, "url": "http://patchwork.ozlabs.org/api/patches/781763/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1498666469-28454-1-git-send-email-matthew.weber@rockwellcollins.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1498666469-28454-1-git-send-email-matthew.weber@rockwellcollins.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1498666469-28454-1-git-send-email-matthew.weber@rockwellcollins.com/", "date": "2017-06-28T16:14:29", "name": "[v2] powerpc/traps : Updated MC for E6500 L1D cache err", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "23c636f34579459aa2843dfd607da4c9e9178706", "submitter": { "id": 64259, "url": "http://patchwork.ozlabs.org/api/people/64259/?format=api", "name": "Matt Weber", "email": "matthew.weber@rockwellcollins.com" }, "delegate": { "id": 1707, "url": "http://patchwork.ozlabs.org/api/users/1707/?format=api", "username": "scottwood", "first_name": "Scott", "last_name": "Wood", "email": "scottwood@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1498666469-28454-1-git-send-email-matthew.weber@rockwellcollins.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/781763/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/781763/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3wySpr38mKz9s7f\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 29 Jun 2017 02:26:28 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3wySpr2N8yzDr5g\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 29 Jun 2017 02:26:28 +1000 (AEST)", "from ch3vs01.rockwellcollins.com (smtpimr.rockwellcollins.com\n\t[205.175.226.27])\n\t(using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3wySnh1MZNzDr3r\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 29 Jun 2017 02:25:26 +1000 (AEST)", "from ofwch3n02.rockwellcollins.com (HELO\n\tcrulimr01.rockwellcollins.com) ([205.175.226.14])\n\tby ch3vs01.rockwellcollins.com with ESMTP; 28 Jun 2017 11:14:30 -0500" ], "X-Greylist": "delayed 653 seconds by postgrey-1.36 at bilbo;\n\tThu, 29 Jun 2017 02:25:28 AEST", "X-Received": "from largo.rockwellcollins.com (unknown [192.168.140.76])\n\tby crulimr01.rockwellcollins.com (Postfix) with ESMTP id 5A11C600BE; \n\tWed, 28 Jun 2017 11:14:30 -0500 (CDT)", "From": "Matt Weber <matthew.weber@rockwellcollins.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH v2] powerpc/traps : Updated MC for E6500 L1D cache err", "Date": "Wed, 28 Jun 2017 11:14:29 -0500", "Message-Id": "<1498666469-28454-1-git-send-email-matthew.weber@rockwellcollins.com>", "X-Mailer": "git-send-email 1.9.1", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Matt Weber <matthew.weber@rockwellcollins.com>,\n\tRonak Desai <ronak.desai@rockwellcollins.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This patch updates the machine check handler of Linux kernel to\nhandle the e6500 architecture case. In e6500 core, L1 Data Cache Write\nShadow Mode (DCWS) register is not implemented but L1 data cache always\nruns in write shadow mode. So, on L1 data cache parity errors, hardware\nwill automatically invalidate the data cache but will still log a\nmachine check interrupt.\n\nSigned-off-by: Ronak Desai <ronak.desai@rockwellcollins.com>\nSigned-off-by: Matthew Weber <matthew.weber@rockwellcollins.com>\n---\n\nChanges \nv1 -> v2\n[Scott Wood\n - Used existing header define for SPRN_PVR\n - Fixed line wrapping\n\n---\n arch/powerpc/kernel/traps.c | 12 ++++++++++--\n 1 file changed, 10 insertions(+), 2 deletions(-)", "diff": "diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c\nindex 76f6045..f656277 100644\n--- a/arch/powerpc/kernel/traps.c\n+++ b/arch/powerpc/kernel/traps.c\n@@ -504,6 +504,7 @@ int machine_check_47x(struct pt_regs *regs)\n int machine_check_e500mc(struct pt_regs *regs)\n {\n \tunsigned long mcsr = mfspr(SPRN_MCSR);\n+\tunsigned long pvr = mfspr(SPRN_PVR);\n \tunsigned long reason = mcsr;\n \tint recoverable = 1;\n \n@@ -545,8 +546,15 @@ int machine_check_e500mc(struct pt_regs *regs)\n \t\t * may still get logged and cause a machine check. We should\n \t\t * only treat the non-write shadow case as non-recoverable.\n \t\t */\n-\t\tif (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))\n-\t\t\trecoverable = 0;\n+\t\t/* On e6500 core, L1 DCWS (Data cache write shadow mode) bit\n+\t\t * is not implemented but L1 data cache always runs in write\n+\t\t * shadow mode. Hence on data cache parity errors HW will\n+\t\t * automatically invalidate the L1 Data Cache.\n+\t\t */\n+\t\tif (PVR_VER(pvr) != PVR_VER_E6500) {\n+\t\t\tif (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))\n+\t\t\t\trecoverable = 0;\n+\t\t}\n \t}\n \n \tif (reason & MCSR_L2MMU_MHIT) {\n", "prefixes": [ "v2" ] }