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GET /api/patches/765818/?format=api
{ "id": 765818, "url": "http://patchwork.ozlabs.org/api/patches/765818/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1495526310-5543-18-git-send-email-jteki@openedev.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1495526310-5543-18-git-send-email-jteki@openedev.com>", "list_archive_url": null, "date": "2017-05-23T07:58:30", "name": "[U-Boot,v7,17/17] i.MX6: SabreSD: Cleanup board code", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "188673486ab111dea62a975d52dd7a43df0becaf", "submitter": { "id": 20045, "url": "http://patchwork.ozlabs.org/api/people/20045/?format=api", "name": "Jagan Teki", "email": "jagannadh.teki@gmail.com" }, "delegate": { "id": 1693, "url": "http://patchwork.ozlabs.org/api/users/1693/?format=api", "username": "sbabic", "first_name": "Stefano", "last_name": "Babic", "email": "sbabic@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1495526310-5543-18-git-send-email-jteki@openedev.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/765818/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/765818/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3wX7bW5rHYz9sP3\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 23 May 2017 18:14:15 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8FCA2C21D0D; Tue, 23 May 2017 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header.i=@gmail.com\n\theader.b=\"YSr77EeI\"; dkim-atps=neutral", "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.8 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,T_DKIM_INVALID,UPPERCASE_50_75\n\tautolearn=no autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=xljRCKpZOnRotvfoYYFvdWeWW1uUe6WMKV2StQ7kVIU=;\n\tb=YSr77EeI37cq77IH0pkKdRBWmqBM4uEVjGwE2BEyszfQ2i2FhFhdsr5jlYXbjmJOIz\n\t76M2VstUIqCjkLrQWgJMvHRhTWkUJD383aBJlumMHHhK+cTX4CCSnT6aCn7pyYhl9Y9S\n\tU3h/D51E660Ocu4/D9Nrrh6i2U9js+igSLI86JWn+qqid12phyVx/ubbQZt9vc4plCC7\n\tCUE+qRhUqYavIrvIowiJtov/DBPQ6QkOaJn05lTkauTbscsHdcvNNwOMaaTazzylsGiK\n\tg9jRl2XIJbCf8SzSM2klcd0BUDkdYTgHi2BBtzgr9QkXlvm0uyN2nUxD/BtxiWXFFJUS\n\t22OA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=xljRCKpZOnRotvfoYYFvdWeWW1uUe6WMKV2StQ7kVIU=;\n\tb=a8IjVBq/PM1dUKA20np6gtK6M9sa34xt3ddCIJLkm0tkSN9ucrgi4lLDIs6pX3zD0b\n\tZu3IWqSO4E3ZRnqbbZYW7rdeoM8TNST3uQ6qh+GtHUor73GvjKCwatBJExQqO7rbAQp5\n\tOhSxD/stEkHtnRXCpTWF4n65tWz1ETtDj5Gnk/LO06tcK/1NItJ99N6qTvXUQxFBSG75\n\tBx4G6HWG9TNcuFrwc+PHZKz2Rfja9eM79JMMWfkhGLyH/aELLeFoZIQxZxlI2L124xte\n\tRwD78KBHgJ6VaaLv51Me2or6hxYG8uzIPbQjLw+NxDJBVX5RXTw8INX4pJdQjnbM/6Ef\n\tM/5g==", "X-Gm-Message-State": "AODbwcCn6R09PCGK7HZ+mOpwcqQLXDmMKvENenLl1HIyMAvOykJHekn8\n\tPgIKhKITTTQBXg==", "X-Received": "by 10.98.22.9 with SMTP id 9mr30129687pfw.125.1495526508200;\n\tTue, 23 May 2017 01:01:48 -0700 (PDT)", "From": "Jagan Teki <jagannadh.teki@gmail.com>", "X-Google-Original-From": "Jagan Teki <jteki@openedev.com>", "To": "Stefano Babic <sbabic@denx.de>", "Date": "Tue, 23 May 2017 13:28:30 +0530", "Message-Id": "<1495526310-5543-18-git-send-email-jteki@openedev.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1495526310-5543-1-git-send-email-jteki@openedev.com>", "References": "<1495526310-5543-1-git-send-email-jteki@openedev.com>", "Cc": "Fabio Estevam <fabio.estevam@nxp.com>, u-boot@lists.denx.de,\n\tJagan Teki <jagan@openedev.com>", "Subject": "[U-Boot] [PATCH v7 17/17] i.MX6: SabreSD: Cleanup board code", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Jagan Teki <jagan@openedev.com>\n\n- Give proper tab alignment for display_info_t structure\n- Add tab spaces UART_PAD_CTRL and SPI_PAD_CTRL\n- Give proper alignment of reg init values on setup_display\n- Add space and newline on board_init_f\n- Add static qualifier for file scope structures\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nReviewed-by: Fabio Estevam <fabio.estevam@nxp.com>\n---\n board/freescale/mx6sabresd/mx6sabresd.c | 195 ++++++++++++++++----------------\n board/freescale/mx6sabresd/spl.c | 30 ++---\n include/configs/mx6sabresd.h | 2 +-\n 3 files changed, 114 insertions(+), 113 deletions(-)", "diff": "diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c\nindex 7179883..609cf30 100644\n--- a/board/freescale/mx6sabresd/mx6sabresd.c\n+++ b/board/freescale/mx6sabresd/mx6sabresd.c\n@@ -28,21 +28,15 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP |\t\t\t\\\n-\tPAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |\t\t\t\\\n-\tPAD_CTL_SRE_FAST | PAD_CTL_HYS)\n-\n-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \\\n-\t\t PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)\n-\n-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP |\t\t\t\\\n-\tPAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |\t\\\n-\tPAD_CTL_ODE | PAD_CTL_SRE_FAST)\n-\n+#define UART_PAD_CTRL\t(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \\\n+\t\t\tPAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)\n+#define SPI_PAD_CTRL\t(PAD_CTL_HYS | PAD_CTL_SPEED_MED | \\\n+\t\t\tPAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)\n+#define I2C_PAD_CTRL\t(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \\\n+\t\t\tPAD_CTL_DSE_40ohm | PAD_CTL_HYS | \\\n+\t\t\tPAD_CTL_ODE | PAD_CTL_SRE_FAST)\n+#define I2C_PAD\t\tMUX_PAD_CTRL(I2C_PAD_CTRL)\n #define I2C_PMIC\t1\n-\n-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)\n-\n #define DISP0_PWR_EN\tIMX_GPIO_NR(1, 21)\n \n int dram_init(void)\n@@ -147,7 +141,7 @@ static void setup_spi(void)\n \tSETUP_IOMUX_PADS(ecspi1_pads);\n }\n \n-iomux_v3_cfg_t const pcie_pads[] = {\n+static iomux_v3_cfg_t const pcie_pads[] = {\n \tIOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),\t/* POWER */\n \tIOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),\t/* RESET */\n };\n@@ -157,7 +151,7 @@ static void setup_pcie(void)\n \tSETUP_IOMUX_PADS(pcie_pads);\n }\n \n-iomux_v3_cfg_t const di0_pads[] = {\n+static iomux_v3_cfg_t const di0_pads[] = {\n \tIOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),\t/* DISP0_CLK */\n \tIOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),\t\t/* DISP0_HSYNC */\n \tIOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),\t\t/* DISP0_VSYNC */\n@@ -220,67 +214,72 @@ static void do_enable_hdmi(struct display_info_t const *dev)\n \timx_enable_hdmi_phy();\n }\n \n-struct display_info_t const displays[] = {{\n-\t.bus\t= -1,\n-\t.addr\t= 0,\n-\t.pixfmt\t= IPU_PIX_FMT_RGB666,\n-\t.detect\t= NULL,\n-\t.enable\t= enable_lvds,\n-\t.mode\t= {\n-\t\t.name = \"Hannstar-XGA\",\n-\t\t.refresh = 60,\n-\t\t.xres = 1024,\n-\t\t.yres = 768,\n-\t\t.pixclock = 15384,\n-\t\t.left_margin = 160,\n-\t\t.right_margin = 24,\n-\t\t.upper_margin = 29,\n-\t\t.lower_margin = 3,\n-\t\t.hsync_len = 136,\n-\t\t.vsync_len = 6,\n-\t\t.sync = FB_SYNC_EXT,\n-\t\t.vmode = FB_VMODE_NONINTERLACED\n-} }, {\n-\t.bus\t= -1,\n-\t.addr\t= 0,\n-\t.pixfmt\t= IPU_PIX_FMT_RGB24,\n-\t.detect\t= detect_hdmi,\n-\t.enable\t= do_enable_hdmi,\n-\t.mode\t= {\n-\t\t.name = \"HDMI\",\n-\t\t.refresh = 60,\n-\t\t.xres = 1024,\n-\t\t.yres = 768,\n-\t\t.pixclock = 15384,\n-\t\t.left_margin = 160,\n-\t\t.right_margin = 24,\n-\t\t.upper_margin = 29,\n-\t\t.lower_margin = 3,\n-\t\t.hsync_len = 136,\n-\t\t.vsync_len = 6,\n-\t\t.sync = FB_SYNC_EXT,\n-\t\t.vmode = FB_VMODE_NONINTERLACED\n-} }, {\n-\t.bus\t= 0,\n-\t.addr\t= 0,\n-\t.pixfmt\t= IPU_PIX_FMT_RGB24,\n-\t.detect\t= NULL,\n-\t.enable\t= enable_rgb,\n-\t.mode\t= {\n-\t\t.name = \"SEIKO-WVGA\",\n-\t\t.refresh = 60,\n-\t\t.xres = 800,\n-\t\t.yres = 480,\n-\t\t.pixclock = 29850,\n-\t\t.left_margin = 89,\n-\t\t.right_margin = 164,\n-\t\t.upper_margin = 23,\n-\t\t.lower_margin = 10,\n-\t\t.hsync_len = 10,\n-\t\t.vsync_len = 10,\n-\t\t.sync = 0,\n-\t\t.vmode = FB_VMODE_NONINTERLACED\n-} } };\n+struct display_info_t const displays[] = {\n+\t{\n+\t\t.bus\t= -1,\n+\t\t.addr\t= 0,\n+\t\t.pixfmt\t= IPU_PIX_FMT_RGB666,\n+\t\t.detect\t= NULL,\n+\t\t.enable\t= enable_lvds,\n+\t\t.mode\t= {\n+\t\t\t.name = \"Hannstar-XGA\",\n+\t\t\t.refresh = 60,\n+\t\t\t.xres = 1024,\n+\t\t\t.yres = 768,\n+\t\t\t.pixclock = 15384,\n+\t\t\t.left_margin = 160,\n+\t\t\t.right_margin = 24,\n+\t\t\t.upper_margin = 29,\n+\t\t\t.lower_margin = 3,\n+\t\t\t.hsync_len = 136,\n+\t\t\t.vsync_len = 6,\n+\t\t\t.sync = FB_SYNC_EXT,\n+\t\t\t.vmode = FB_VMODE_NONINTERLACED\n+\t\t}\n+\t}, {\n+\t\t.bus\t= -1,\n+\t\t.addr\t= 0,\n+\t\t.pixfmt\t= IPU_PIX_FMT_RGB24,\n+\t\t.detect\t= detect_hdmi,\n+\t\t.enable\t= do_enable_hdmi,\n+\t\t.mode\t= {\n+\t\t\t.name = \"HDMI\",\n+\t\t\t.refresh = 60,\n+\t\t\t.xres = 1024,\n+\t\t\t.yres = 768,\n+\t\t\t.pixclock = 15384,\n+\t\t\t.left_margin = 160,\n+\t\t\t.right_margin = 24,\n+\t\t\t.upper_margin = 29,\n+\t\t\t.lower_margin = 3,\n+\t\t\t.hsync_len = 136,\n+\t\t\t.vsync_len = 6,\n+\t\t\t.sync = FB_SYNC_EXT,\n+\t\t\t.vmode = FB_VMODE_NONINTERLACED\n+\t\t}\n+\t}, {\n+\t\t.bus\t= 0,\n+\t\t.addr\t= 0,\n+\t\t.pixfmt\t= IPU_PIX_FMT_RGB24,\n+\t\t.detect\t= NULL,\n+\t\t.enable\t= enable_rgb,\n+\t\t.mode\t= {\n+\t\t\t.name = \"SEIKO-WVGA\",\n+\t\t\t.refresh = 60,\n+\t\t\t.xres = 800,\n+\t\t\t.yres = 480,\n+\t\t\t.pixclock = 29850,\n+\t\t\t.left_margin = 89,\n+\t\t\t.right_margin = 164,\n+\t\t\t.upper_margin = 23,\n+\t\t\t.lower_margin = 10,\n+\t\t\t.hsync_len = 10,\n+\t\t\t.vsync_len = 10,\n+\t\t\t.sync = 0,\n+\t\t\t.vmode = FB_VMODE_NONINTERLACED\n+\t\t}\n+\t}\n+};\n size_t display_count = ARRAY_SIZE(displays);\n \n static void setup_display(void)\n@@ -302,10 +301,10 @@ static void setup_display(void)\n \n \t/* set LDB0, LDB1 clk select to 011/011 */\n \treg = readl(&mxc_ccm->cs2cdr);\n-\treg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK\n-\t\t | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);\n-\treg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)\n-\t | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);\n+\treg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |\n+\t\tMXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);\n+\treg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |\n+\t\t(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);\n \twritel(reg, &mxc_ccm->cs2cdr);\n \n \treg = readl(&mxc_ccm->cscmr2);\n@@ -313,28 +312,28 @@ static void setup_display(void)\n \twritel(reg, &mxc_ccm->cscmr2);\n \n \treg = readl(&mxc_ccm->chsccdr);\n-\treg |= (CHSCCDR_CLK_SEL_LDB_DI0\n-\t\t<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);\n-\treg |= (CHSCCDR_CLK_SEL_LDB_DI0\n-\t\t<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);\n+\treg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<\n+\t\tMXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);\n+\treg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<\n+\t\tMXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);\n \twritel(reg, &mxc_ccm->chsccdr);\n \n-\treg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES\n-\t | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW\n-\t | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW\n-\t | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG\n-\t | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT\n-\t | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG\n-\t | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT\n-\t | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED\n-\t | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;\n+\treg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |\n+\t\tIOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |\n+\t\tIOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |\n+\t\tIOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |\n+\t\tIOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |\n+\t\tIOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |\n+\t\tIOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |\n+\t\tIOMUXC_GPR2_LVDS_CH0_MODE_DISABLED |\n+\t\tIOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;\n \twritel(reg, &iomux->gpr[2]);\n \n \treg = readl(&iomux->gpr[3]);\n-\treg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK\n-\t\t\t| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))\n-\t | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0\n-\t << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);\n+\treg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |\n+\t\tIOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |\n+\t\t(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<\n+\t\tIOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);\n \twritel(reg, &iomux->gpr[3]);\n }\n #endif /* CONFIG_VIDEO_IPUV3 */\ndiff --git a/board/freescale/mx6sabresd/spl.c b/board/freescale/mx6sabresd/spl.c\nindex 2488cb5..77b650f 100644\n--- a/board/freescale/mx6sabresd/spl.c\n+++ b/board/freescale/mx6sabresd/spl.c\n@@ -37,20 +37,20 @@ DECLARE_GLOBAL_DATA_PTR;\n static iomux_v3_cfg_t const usdhc2_pads[] = {\n \tIOMUX_PADS(PAD_SD2_CLK__SD2_CLK\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD2_CMD__SD2_CMD\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D4__SD2_DATA4\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D5__SD2_DATA5\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D6__SD2_DATA6\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D7__SD2_DATA7\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02\t| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n+\tIOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n };\n \n static iomux_v3_cfg_t const usdhc3_pads[] = {\n-\tIOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n@@ -59,12 +59,12 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {\n \tIOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n+\tIOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n };\n \n static iomux_v3_cfg_t const usdhc4_pads[] = {\n-\tIOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n \tIOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n@@ -113,6 +113,7 @@ int board_mmc_init(bd_t *bis)\n {\n \tstruct src *psrc = (struct src *)SRC_BASE_ADDR;\n \tunsigned reg = readl(&psrc->sbmr1) >> 11;\n+\n \t/*\n \t * Upon reading BOOT_CFG register the following map is done:\n \t * Bit 11 and 12 of BOOT_CFG register can determine the current\n@@ -496,6 +497,7 @@ void board_init_f(ulong dummy)\n \tarch_cpu_init();\n \n \tccgr_init();\n+\n \tgpr_init();\n \n \t/* iomux and setup of i2c */\ndiff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h\nindex 44c7cf6..4b48347 100644\n--- a/include/configs/mx6sabresd.h\n+++ b/include/configs/mx6sabresd.h\n@@ -20,7 +20,7 @@\n #define CONFIG_MACH_TYPE\t3980\n #define CONFIG_MXC_UART_BASE\tUART1_BASE\n #define CONSOLE_DEV\t\t\"ttymxc0\"\n-#define CONFIG_MMCROOT\t\t\t\"/dev/mmcblk1p2\"\n+#define CONFIG_MMCROOT\t\t\"/dev/mmcblk1p2\"\n \n #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */\n \n", "prefixes": [ "U-Boot", "v7", "17/17" ] }