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{
    "id": 765812,
    "url": "http://patchwork.ozlabs.org/api/patches/765812/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1495526310-5543-8-git-send-email-jteki@openedev.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1495526310-5543-8-git-send-email-jteki@openedev.com>",
    "list_archive_url": null,
    "date": "2017-05-23T07:58:20",
    "name": "[U-Boot,v7,07/17] sabresd: i.MX6Q: Add initial dts support",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "72292d857f4de61d577058fa4d8ad8ca497e55f1",
    "submitter": {
        "id": 20045,
        "url": "http://patchwork.ozlabs.org/api/people/20045/?format=api",
        "name": "Jagan Teki",
        "email": "jagannadh.teki@gmail.com"
    },
    "delegate": {
        "id": 1693,
        "url": "http://patchwork.ozlabs.org/api/users/1693/?format=api",
        "username": "sbabic",
        "first_name": "Stefano",
        "last_name": "Babic",
        "email": "sbabic@denx.de"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1495526310-5543-8-git-send-email-jteki@openedev.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/765812/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/765812/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Jagan Teki <jagannadh.teki@gmail.com>",
        "X-Google-Original-From": "Jagan Teki <jteki@openedev.com>",
        "To": "Stefano Babic <sbabic@denx.de>",
        "Date": "Tue, 23 May 2017 13:28:20 +0530",
        "Message-Id": "<1495526310-5543-8-git-send-email-jteki@openedev.com>",
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        "References": "<1495526310-5543-1-git-send-email-jteki@openedev.com>",
        "Cc": "Fabio Estevam <fabio.estevam@nxp.com>, u-boot@lists.denx.de",
        "Subject": "[U-Boot] [PATCH v7 07/17] sabresd: i.MX6Q: Add initial dts support",
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    },
    "content": "From: Jagan Teki <jagan@amarulasolutions.com>\n\nAdd initial devicetree support for i.MX6 Quad Sabresd board.\n\n(1) Added config options\n    CONFIG_OF_CONTROL=y\n    CONFIG_DM_GPIO=y\n    CONFIG_DM_MMC=y\n    CONFIG_BLK is not set\n    CONFIG_DM_MMC_OPS is not set\n    CONFIG_PINCTRL=y\n    CONFIG_PINCTRL_IMX6=y\n(2) Moved spl code to board/freescale/mx6sabresd/spl.c\n(3) Removed U-Boot proper board_mmc_init code, since mmc\n    support through dtb\n(4) DM_GPIO and GM_MMC are undef for SPL, till SPL_OF_CONTROL\n    support.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n arch/arm/cpu/armv7/mx6/Kconfig          |   9 +-\n board/freescale/mx6sabresd/Makefile     |   1 +\n board/freescale/mx6sabresd/mx6sabresd.c | 523 --------------------------------\n board/freescale/mx6sabresd/spl.c        | 501 ++++++++++++++++++++++++++++++\n configs/mx6sabresd_spl_defconfig        |   3 +\n include/configs/mx6sabresd.h            |   5 +-\n 6 files changed, 516 insertions(+), 526 deletions(-)\n create mode 100644 board/freescale/mx6sabresd/spl.c",
    "diff": "diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig\nindex 0ff9045..0497fe0 100644\n--- a/arch/arm/cpu/armv7/mx6/Kconfig\n+++ b/arch/arm/cpu/armv7/mx6/Kconfig\n@@ -210,11 +210,16 @@ config TARGET_MX6QSABREAUTO\n \n config TARGET_MX6SABRESD\n \tbool \"mx6sabresd\"\n+\tselect BOARD_EARLY_INIT_F\n \tselect BOARD_LATE_INIT\n-\tselect SUPPORT_SPL\n+\tselect OF_CONTROL\n \tselect DM\n+\tselect DM_GPIO\n+\tselect DM_MMC\n \tselect DM_THERMAL\n-\tselect BOARD_EARLY_INIT_F\n+\tselect PINCTRL\n+\tselect PINCTRL_IMX6\n+\tselect SUPPORT_SPL\n \n config TARGET_MX6SLEVK\n \tbool \"mx6slevk\"\ndiff --git a/board/freescale/mx6sabresd/Makefile b/board/freescale/mx6sabresd/Makefile\nindex cfca2ef..3ae32ab 100644\n--- a/board/freescale/mx6sabresd/Makefile\n+++ b/board/freescale/mx6sabresd/Makefile\n@@ -7,3 +7,4 @@\n #\n \n obj-y  := mx6sabresd.o\n+obj-$(CONFIG_SPL_BUILD) += spl.o\ndiff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c\nindex f4a5d9c..7af263d 100644\n--- a/board/freescale/mx6sabresd/mx6sabresd.c\n+++ b/board/freescale/mx6sabresd/mx6sabresd.c\n@@ -16,8 +16,6 @@\n #include <asm/imx-common/iomux-v3.h>\n #include <asm/imx-common/boot_mode.h>\n #include <asm/imx-common/video.h>\n-#include <mmc.h>\n-#include <fsl_esdhc.h>\n #include <miiphy.h>\n #include <netdev.h>\n #include <asm/arch/mxc_hdmi.h>\n@@ -36,10 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;\n \tPAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |\t\t\t\\\n \tPAD_CTL_SRE_FAST  | PAD_CTL_HYS)\n \n-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |\t\t\t\\\n-\tPAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |\t\t\t\\\n-\tPAD_CTL_SRE_FAST  | PAD_CTL_HYS)\n-\n #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |\t\t\t\\\n \tPAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)\n \n@@ -56,8 +50,6 @@ DECLARE_GLOBAL_DATA_PTR;\n \n #define DISP0_PWR_EN\tIMX_GPIO_NR(1, 21)\n \n-#define KEY_VOL_UP\tIMX_GPIO_NR(1, 4)\n-\n int dram_init(void)\n {\n \tgd->ram_size = imx_ddr_size();\n@@ -100,47 +92,6 @@ static void setup_iomux_enet(void)\n \tudelay(100);\n }\n \n-static iomux_v3_cfg_t const usdhc2_pads[] = {\n-\tIOMUX_PADS(PAD_SD2_CLK__SD2_CLK\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_CMD__SD2_CMD\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D4__SD2_DATA4\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D5__SD2_DATA5\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D6__SD2_DATA6\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D7__SD2_DATA7\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02\t| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n-};\n-\n-static iomux_v3_cfg_t const usdhc3_pads[] = {\n-\tIOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n-};\n-\n-static iomux_v3_cfg_t const usdhc4_pads[] = {\n-\tIOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-\tIOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n-};\n-\n static iomux_v3_cfg_t const ecspi1_pads[] = {\n \tIOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),\n \tIOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),\n@@ -253,121 +204,6 @@ static void setup_iomux_uart(void)\n \tSETUP_IOMUX_PADS(uart1_pads);\n }\n \n-#ifdef CONFIG_FSL_ESDHC\n-struct fsl_esdhc_cfg usdhc_cfg[3] = {\n-\t{USDHC2_BASE_ADDR},\n-\t{USDHC3_BASE_ADDR},\n-\t{USDHC4_BASE_ADDR},\n-};\n-\n-#define USDHC2_CD_GPIO\tIMX_GPIO_NR(2, 2)\n-#define USDHC3_CD_GPIO\tIMX_GPIO_NR(2, 0)\n-\n-int board_mmc_get_env_dev(int devno)\n-{\n-\treturn devno - 1;\n-}\n-\n-int board_mmc_getcd(struct mmc *mmc)\n-{\n-\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n-\tint ret = 0;\n-\n-\tswitch (cfg->esdhc_base) {\n-\tcase USDHC2_BASE_ADDR:\n-\t\tret = !gpio_get_value(USDHC2_CD_GPIO);\n-\t\tbreak;\n-\tcase USDHC3_BASE_ADDR:\n-\t\tret = !gpio_get_value(USDHC3_CD_GPIO);\n-\t\tbreak;\n-\tcase USDHC4_BASE_ADDR:\n-\t\tret = 1; /* eMMC/uSDHC4 is always present */\n-\t\tbreak;\n-\t}\n-\n-\treturn ret;\n-}\n-\n-int board_mmc_init(bd_t *bis)\n-{\n-#ifndef CONFIG_SPL_BUILD\n-\tint ret;\n-\tint i;\n-\n-\t/*\n-\t * According to the board_mmc_init() the following map is done:\n-\t * (U-Boot device node)    (Physical Port)\n-\t * mmc0                    SD2\n-\t * mmc1                    SD3\n-\t * mmc2                    eMMC\n-\t */\n-\tfor (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {\n-\t\tswitch (i) {\n-\t\tcase 0:\n-\t\t\tSETUP_IOMUX_PADS(usdhc2_pads);\n-\t\t\tgpio_direction_input(USDHC2_CD_GPIO);\n-\t\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);\n-\t\t\tbreak;\n-\t\tcase 1:\n-\t\t\tSETUP_IOMUX_PADS(usdhc3_pads);\n-\t\t\tgpio_direction_input(USDHC3_CD_GPIO);\n-\t\t\tusdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);\n-\t\t\tbreak;\n-\t\tcase 2:\n-\t\t\tSETUP_IOMUX_PADS(usdhc4_pads);\n-\t\t\tusdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Warning: you configured more USDHC controllers\"\n-\t\t\t       \"(%d) then supported by the board (%d)\\n\",\n-\t\t\t       i + 1, CONFIG_SYS_FSL_USDHC_NUM);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-#else\n-\tstruct src *psrc = (struct src *)SRC_BASE_ADDR;\n-\tunsigned reg = readl(&psrc->sbmr1) >> 11;\n-\t/*\n-\t * Upon reading BOOT_CFG register the following map is done:\n-\t * Bit 11 and 12 of BOOT_CFG register can determine the current\n-\t * mmc port\n-\t * 0x1                  SD1\n-\t * 0x2                  SD2\n-\t * 0x3                  SD4\n-\t */\n-\n-\tswitch (reg & 0x3) {\n-\tcase 0x1:\n-\t\tSETUP_IOMUX_PADS(usdhc2_pads);\n-\t\tusdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;\n-\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);\n-\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n-\t\tbreak;\n-\tcase 0x2:\n-\t\tSETUP_IOMUX_PADS(usdhc3_pads);\n-\t\tusdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;\n-\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);\n-\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n-\t\tbreak;\n-\tcase 0x3:\n-\t\tSETUP_IOMUX_PADS(usdhc4_pads);\n-\t\tusdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;\n-\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);\n-\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n-\t\tbreak;\n-\t}\n-\n-\treturn fsl_esdhc_initialize(bis, &usdhc_cfg[0]);\n-#endif\n-}\n-#endif\n-\n static int ar8031_phy_fixup(struct phy_device *phydev)\n {\n \tunsigned short val;\n@@ -718,362 +554,3 @@ int checkboard(void)\n \tputs(\"Board: MX6-SabreSD\\n\");\n \treturn 0;\n }\n-\n-#ifdef CONFIG_SPL_BUILD\n-#include <asm/arch/mx6-ddr.h>\n-#include <spl.h>\n-#include <libfdt.h>\n-\n-#ifdef CONFIG_SPL_OS_BOOT\n-int spl_start_uboot(void)\n-{\n-\tgpio_direction_input(KEY_VOL_UP);\n-\n-\t/* Only enter in Falcon mode if KEY_VOL_UP is pressed */\n-\treturn gpio_get_value(KEY_VOL_UP);\n-}\n-#endif\n-\n-static void ccgr_init(void)\n-{\n-\tstruct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;\n-\n-\twritel(0x00C03F3F, &ccm->CCGR0);\n-\twritel(0x0030FC03, &ccm->CCGR1);\n-\twritel(0x0FFFC000, &ccm->CCGR2);\n-\twritel(0x3FF00000, &ccm->CCGR3);\n-\twritel(0x00FFF300, &ccm->CCGR4);\n-\twritel(0x0F0000C3, &ccm->CCGR5);\n-\twritel(0x000003FF, &ccm->CCGR6);\n-}\n-\n-static void gpr_init(void)\n-{\n-\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* enable AXI cache for VDOA/VPU/IPU */\n-\twritel(0xF00000CF, &iomux->gpr[4]);\n-\tif (is_mx6dqp()) {\n-\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n-\t\twritel(0x007F007F, &iomux->gpr[6]);\n-\t\twritel(0x007F007F, &iomux->gpr[7]);\n-\t} else {\n-\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n-\t\twritel(0x007F007F, &iomux->gpr[6]);\n-\t\twritel(0x007F007F, &iomux->gpr[7]);\n-\t}\n-}\n-\n-static int mx6q_dcd_table[] = {\n-\t0x020e0798, 0x000C0000,\n-\t0x020e0758, 0x00000000,\n-\t0x020e0588, 0x00000030,\n-\t0x020e0594, 0x00000030,\n-\t0x020e056c, 0x00000030,\n-\t0x020e0578, 0x00000030,\n-\t0x020e074c, 0x00000030,\n-\t0x020e057c, 0x00000030,\n-\t0x020e058c, 0x00000000,\n-\t0x020e059c, 0x00000030,\n-\t0x020e05a0, 0x00000030,\n-\t0x020e078c, 0x00000030,\n-\t0x020e0750, 0x00020000,\n-\t0x020e05a8, 0x00000030,\n-\t0x020e05b0, 0x00000030,\n-\t0x020e0524, 0x00000030,\n-\t0x020e051c, 0x00000030,\n-\t0x020e0518, 0x00000030,\n-\t0x020e050c, 0x00000030,\n-\t0x020e05b8, 0x00000030,\n-\t0x020e05c0, 0x00000030,\n-\t0x020e0774, 0x00020000,\n-\t0x020e0784, 0x00000030,\n-\t0x020e0788, 0x00000030,\n-\t0x020e0794, 0x00000030,\n-\t0x020e079c, 0x00000030,\n-\t0x020e07a0, 0x00000030,\n-\t0x020e07a4, 0x00000030,\n-\t0x020e07a8, 0x00000030,\n-\t0x020e0748, 0x00000030,\n-\t0x020e05ac, 0x00000030,\n-\t0x020e05b4, 0x00000030,\n-\t0x020e0528, 0x00000030,\n-\t0x020e0520, 0x00000030,\n-\t0x020e0514, 0x00000030,\n-\t0x020e0510, 0x00000030,\n-\t0x020e05bc, 0x00000030,\n-\t0x020e05c4, 0x00000030,\n-\t0x021b0800, 0xa1390003,\n-\t0x021b080c, 0x001F001F,\n-\t0x021b0810, 0x001F001F,\n-\t0x021b480c, 0x001F001F,\n-\t0x021b4810, 0x001F001F,\n-\t0x021b083c, 0x43270338,\n-\t0x021b0840, 0x03200314,\n-\t0x021b483c, 0x431A032F,\n-\t0x021b4840, 0x03200263,\n-\t0x021b0848, 0x4B434748,\n-\t0x021b4848, 0x4445404C,\n-\t0x021b0850, 0x38444542,\n-\t0x021b4850, 0x4935493A,\n-\t0x021b081c, 0x33333333,\n-\t0x021b0820, 0x33333333,\n-\t0x021b0824, 0x33333333,\n-\t0x021b0828, 0x33333333,\n-\t0x021b481c, 0x33333333,\n-\t0x021b4820, 0x33333333,\n-\t0x021b4824, 0x33333333,\n-\t0x021b4828, 0x33333333,\n-\t0x021b08b8, 0x00000800,\n-\t0x021b48b8, 0x00000800,\n-\t0x021b0004, 0x00020036,\n-\t0x021b0008, 0x09444040,\n-\t0x021b000c, 0x555A7975,\n-\t0x021b0010, 0xFF538F64,\n-\t0x021b0014, 0x01FF00DB,\n-\t0x021b0018, 0x00001740,\n-\t0x021b001c, 0x00008000,\n-\t0x021b002c, 0x000026d2,\n-\t0x021b0030, 0x005A1023,\n-\t0x021b0040, 0x00000027,\n-\t0x021b0000, 0x831A0000,\n-\t0x021b001c, 0x04088032,\n-\t0x021b001c, 0x00008033,\n-\t0x021b001c, 0x00048031,\n-\t0x021b001c, 0x09408030,\n-\t0x021b001c, 0x04008040,\n-\t0x021b0020, 0x00005800,\n-\t0x021b0818, 0x00011117,\n-\t0x021b4818, 0x00011117,\n-\t0x021b0004, 0x00025576,\n-\t0x021b0404, 0x00011006,\n-\t0x021b001c, 0x00000000,\n-};\n-\n-static int mx6qp_dcd_table[] = {\n-\t0x020e0798, 0x000c0000,\n-\t0x020e0758, 0x00000000,\n-\t0x020e0588, 0x00000030,\n-\t0x020e0594, 0x00000030,\n-\t0x020e056c, 0x00000030,\n-\t0x020e0578, 0x00000030,\n-\t0x020e074c, 0x00000030,\n-\t0x020e057c, 0x00000030,\n-\t0x020e058c, 0x00000000,\n-\t0x020e059c, 0x00000030,\n-\t0x020e05a0, 0x00000030,\n-\t0x020e078c, 0x00000030,\n-\t0x020e0750, 0x00020000,\n-\t0x020e05a8, 0x00000030,\n-\t0x020e05b0, 0x00000030,\n-\t0x020e0524, 0x00000030,\n-\t0x020e051c, 0x00000030,\n-\t0x020e0518, 0x00000030,\n-\t0x020e050c, 0x00000030,\n-\t0x020e05b8, 0x00000030,\n-\t0x020e05c0, 0x00000030,\n-\t0x020e0774, 0x00020000,\n-\t0x020e0784, 0x00000030,\n-\t0x020e0788, 0x00000030,\n-\t0x020e0794, 0x00000030,\n-\t0x020e079c, 0x00000030,\n-\t0x020e07a0, 0x00000030,\n-\t0x020e07a4, 0x00000030,\n-\t0x020e07a8, 0x00000030,\n-\t0x020e0748, 0x00000030,\n-\t0x020e05ac, 0x00000030,\n-\t0x020e05b4, 0x00000030,\n-\t0x020e0528, 0x00000030,\n-\t0x020e0520, 0x00000030,\n-\t0x020e0514, 0x00000030,\n-\t0x020e0510, 0x00000030,\n-\t0x020e05bc, 0x00000030,\n-\t0x020e05c4, 0x00000030,\n-\t0x021b0800, 0xa1390003,\n-\t0x021b080c, 0x001b001e,\n-\t0x021b0810, 0x002e0029,\n-\t0x021b480c, 0x001b002a,\n-\t0x021b4810, 0x0019002c,\n-\t0x021b083c, 0x43240334,\n-\t0x021b0840, 0x0324031a,\n-\t0x021b483c, 0x43340344,\n-\t0x021b4840, 0x03280276,\n-\t0x021b0848, 0x44383A3E,\n-\t0x021b4848, 0x3C3C3846,\n-\t0x021b0850, 0x2e303230,\n-\t0x021b4850, 0x38283E34,\n-\t0x021b081c, 0x33333333,\n-\t0x021b0820, 0x33333333,\n-\t0x021b0824, 0x33333333,\n-\t0x021b0828, 0x33333333,\n-\t0x021b481c, 0x33333333,\n-\t0x021b4820, 0x33333333,\n-\t0x021b4824, 0x33333333,\n-\t0x021b4828, 0x33333333,\n-\t0x021b08c0, 0x24912249,\n-\t0x021b48c0, 0x24914289,\n-\t0x021b08b8, 0x00000800,\n-\t0x021b48b8, 0x00000800,\n-\t0x021b0004, 0x00020036,\n-\t0x021b0008, 0x24444040,\n-\t0x021b000c, 0x555A7955,\n-\t0x021b0010, 0xFF320F64,\n-\t0x021b0014, 0x01ff00db,\n-\t0x021b0018, 0x00001740,\n-\t0x021b001c, 0x00008000,\n-\t0x021b002c, 0x000026d2,\n-\t0x021b0030, 0x005A1023,\n-\t0x021b0040, 0x00000027,\n-\t0x021b0400, 0x14420000,\n-\t0x021b0000, 0x831A0000,\n-\t0x021b0890, 0x00400C58,\n-\t0x00bb0008, 0x00000000,\n-\t0x00bb000c, 0x2891E41A,\n-\t0x00bb0038, 0x00000564,\n-\t0x00bb0014, 0x00000040,\n-\t0x00bb0028, 0x00000020,\n-\t0x00bb002c, 0x00000020,\n-\t0x021b001c, 0x04088032,\n-\t0x021b001c, 0x00008033,\n-\t0x021b001c, 0x00048031,\n-\t0x021b001c, 0x09408030,\n-\t0x021b001c, 0x04008040,\n-\t0x021b0020, 0x00005800,\n-\t0x021b0818, 0x00011117,\n-\t0x021b4818, 0x00011117,\n-\t0x021b0004, 0x00025576,\n-\t0x021b0404, 0x00011006,\n-\t0x021b001c, 0x00000000,\n-};\n-\n-static int mx6dl_dcd_table[] = {\n-\t0x020e0774, 0x000C0000,\n-\t0x020e0754, 0x00000000,\n-\t0x020e04ac, 0x00000030,\n-\t0x020e04b0, 0x00000030,\n-\t0x020e0464, 0x00000030,\n-\t0x020e0490, 0x00000030,\n-\t0x020e074c, 0x00000030,\n-\t0x020e0494, 0x00000030,\n-\t0x020e04a0, 0x00000000,\n-\t0x020e04b4, 0x00000030,\n-\t0x020e04b8, 0x00000030,\n-\t0x020e076c, 0x00000030,\n-\t0x020e0750, 0x00020000,\n-\t0x020e04bc, 0x00000030,\n-\t0x020e04c0, 0x00000030,\n-\t0x020e04c4, 0x00000030,\n-\t0x020e04c8, 0x00000030,\n-\t0x020e04cc, 0x00000030,\n-\t0x020e04d0, 0x00000030,\n-\t0x020e04d4, 0x00000030,\n-\t0x020e04d8, 0x00000030,\n-\t0x020e0760, 0x00020000,\n-\t0x020e0764, 0x00000030,\n-\t0x020e0770, 0x00000030,\n-\t0x020e0778, 0x00000030,\n-\t0x020e077c, 0x00000030,\n-\t0x020e0780, 0x00000030,\n-\t0x020e0784, 0x00000030,\n-\t0x020e078c, 0x00000030,\n-\t0x020e0748, 0x00000030,\n-\t0x020e0470, 0x00000030,\n-\t0x020e0474, 0x00000030,\n-\t0x020e0478, 0x00000030,\n-\t0x020e047c, 0x00000030,\n-\t0x020e0480, 0x00000030,\n-\t0x020e0484, 0x00000030,\n-\t0x020e0488, 0x00000030,\n-\t0x020e048c, 0x00000030,\n-\t0x021b0800, 0xa1390003,\n-\t0x021b080c, 0x001F001F,\n-\t0x021b0810, 0x001F001F,\n-\t0x021b480c, 0x001F001F,\n-\t0x021b4810, 0x001F001F,\n-\t0x021b083c, 0x4220021F,\n-\t0x021b0840, 0x0207017E,\n-\t0x021b483c, 0x4201020C,\n-\t0x021b4840, 0x01660172,\n-\t0x021b0848, 0x4A4D4E4D,\n-\t0x021b4848, 0x4A4F5049,\n-\t0x021b0850, 0x3F3C3D31,\n-\t0x021b4850, 0x3238372B,\n-\t0x021b081c, 0x33333333,\n-\t0x021b0820, 0x33333333,\n-\t0x021b0824, 0x33333333,\n-\t0x021b0828, 0x33333333,\n-\t0x021b481c, 0x33333333,\n-\t0x021b4820, 0x33333333,\n-\t0x021b4824, 0x33333333,\n-\t0x021b4828, 0x33333333,\n-\t0x021b08b8, 0x00000800,\n-\t0x021b48b8, 0x00000800,\n-\t0x021b0004, 0x0002002D,\n-\t0x021b0008, 0x00333030,\n-\t0x021b000c, 0x3F435313,\n-\t0x021b0010, 0xB66E8B63,\n-\t0x021b0014, 0x01FF00DB,\n-\t0x021b0018, 0x00001740,\n-\t0x021b001c, 0x00008000,\n-\t0x021b002c, 0x000026d2,\n-\t0x021b0030, 0x00431023,\n-\t0x021b0040, 0x00000027,\n-\t0x021b0000, 0x831A0000,\n-\t0x021b001c, 0x04008032,\n-\t0x021b001c, 0x00008033,\n-\t0x021b001c, 0x00048031,\n-\t0x021b001c, 0x05208030,\n-\t0x021b001c, 0x04008040,\n-\t0x021b0020, 0x00005800,\n-\t0x021b0818, 0x00011117,\n-\t0x021b4818, 0x00011117,\n-\t0x021b0004, 0x0002556D,\n-\t0x021b0404, 0x00011006,\n-\t0x021b001c, 0x00000000,\n-};\n-\n-static void ddr_init(int *table, int size)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < size / 2 ; i++)\n-\t\twritel(table[2 * i + 1], table[2 * i]);\n-}\n-\n-static void spl_dram_init(void)\n-{\n-\tif (is_mx6dq())\n-\t\tddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));\n-\telse if (is_mx6dqp())\n-\t\tddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));\n-\telse if (is_mx6sdl())\n-\t\tddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));\n-}\n-\n-void board_init_f(ulong dummy)\n-{\n-\t/* DDR initialization */\n-\tspl_dram_init();\n-\n-\t/* setup AIPS and disable watchdog */\n-\tarch_cpu_init();\n-\n-\tccgr_init();\n-\tgpr_init();\n-\n-\t/* iomux and setup of i2c */\n-\tboard_early_init_f();\n-\n-\t/* setup GP timer */\n-\ttimer_init();\n-\n-\t/* UART clocks enabled and gd valid - init serial console */\n-\tpreloader_console_init();\n-\n-\t/* Clear the BSS. */\n-\tmemset(__bss_start, 0, __bss_end - __bss_start);\n-\n-\t/* load/boot image from boot device */\n-\tboard_init_r(NULL, 0);\n-}\n-#endif\ndiff --git a/board/freescale/mx6sabresd/spl.c b/board/freescale/mx6sabresd/spl.c\nnew file mode 100644\nindex 0000000..01d45ce\n--- /dev/null\n+++ b/board/freescale/mx6sabresd/spl.c\n@@ -0,0 +1,501 @@\n+/*\n+ * Copyright (C) 2012 Freescale Semiconductor, Inc.\n+ *\n+ * Author: Fabio Estevam <fabio.estevam@freescale.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <libfdt.h>\n+#include <mmc.h>\n+#include <fsl_esdhc.h>\n+#include <spl.h>\n+\n+#include <linux/errno.h>\n+#include <asm/gpio.h>\n+#include <asm/io.h>\n+\n+#include <asm/arch/clock.h>\n+#include <asm/arch/crm_regs.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/iomux.h>\n+#include <asm/arch/mx6-ddr.h>\n+#include <asm/arch/mx6-pins.h>\n+#include <asm/arch/sys_proto.h>\n+\n+#include <asm/imx-common/iomux-v3.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#ifdef CONFIG_FSL_ESDHC\n+#define USDHC_PAD_CTRL\t\t(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \\\n+\t\t\t\tPAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST  | \\\n+\t\t\t\tPAD_CTL_HYS)\n+#define KEY_VOL_UP\t\tIMX_GPIO_NR(1, 4)\n+\n+static iomux_v3_cfg_t const usdhc2_pads[] = {\n+\tIOMUX_PADS(PAD_SD2_CLK__SD2_CLK\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_CMD__SD2_CMD\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D4__SD2_DATA4\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D5__SD2_DATA5\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D6__SD2_DATA6\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D7__SD2_DATA7\t| MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02\t| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n+};\n+\n+static iomux_v3_cfg_t const usdhc3_pads[] = {\n+\tIOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */\n+};\n+\n+static iomux_v3_cfg_t const usdhc4_pads[] = {\n+\tIOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+\tIOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),\n+};\n+\n+struct fsl_esdhc_cfg usdhc_cfg[3] = {\n+\t{USDHC2_BASE_ADDR},\n+\t{USDHC3_BASE_ADDR},\n+\t{USDHC4_BASE_ADDR},\n+};\n+\n+#define USDHC2_CD_GPIO\tIMX_GPIO_NR(2, 2)\n+#define USDHC3_CD_GPIO\tIMX_GPIO_NR(2, 0)\n+\n+int board_mmc_get_env_dev(int devno)\n+{\n+\treturn devno - 1;\n+}\n+\n+int board_mmc_getcd(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tswitch (cfg->esdhc_base) {\n+\tcase USDHC2_BASE_ADDR:\n+\t\tret = !gpio_get_value(USDHC2_CD_GPIO);\n+\t\tbreak;\n+\tcase USDHC3_BASE_ADDR:\n+\t\tret = !gpio_get_value(USDHC3_CD_GPIO);\n+\t\tbreak;\n+\tcase USDHC4_BASE_ADDR:\n+\t\tret = 1; /* eMMC/uSDHC4 is always present */\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+int board_mmc_init(bd_t *bis)\n+{\n+\tstruct src *psrc = (struct src *)SRC_BASE_ADDR;\n+\tunsigned reg = readl(&psrc->sbmr1) >> 11;\n+\t/*\n+\t * Upon reading BOOT_CFG register the following map is done:\n+\t * Bit 11 and 12 of BOOT_CFG register can determine the current\n+\t * mmc port\n+\t * 0x1                  SD1\n+\t * 0x2                  SD2\n+\t * 0x3                  SD4\n+\t */\n+\n+\tswitch (reg & 0x3) {\n+\tcase 0x1:\n+\t\tSETUP_IOMUX_PADS(usdhc2_pads);\n+\t\tusdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;\n+\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);\n+\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n+\t\tbreak;\n+\tcase 0x2:\n+\t\tSETUP_IOMUX_PADS(usdhc3_pads);\n+\t\tusdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;\n+\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);\n+\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n+\t\tbreak;\n+\tcase 0x3:\n+\t\tSETUP_IOMUX_PADS(usdhc4_pads);\n+\t\tusdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;\n+\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);\n+\t\tgd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;\n+\t\tbreak;\n+\t}\n+\n+\treturn fsl_esdhc_initialize(bis, &usdhc_cfg[0]);\n+}\n+#endif /* CONFIG_FSL_ESDHC */\n+\n+#ifdef CONFIG_SPL_OS_BOOT\n+int spl_start_uboot(void)\n+{\n+\tgpio_direction_input(KEY_VOL_UP);\n+\n+\t/* Only enter in Falcon mode if KEY_VOL_UP is pressed */\n+\treturn gpio_get_value(KEY_VOL_UP);\n+}\n+#endif\n+\n+static void ccgr_init(void)\n+{\n+\tstruct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;\n+\n+\twritel(0x00C03F3F, &ccm->CCGR0);\n+\twritel(0x0030FC03, &ccm->CCGR1);\n+\twritel(0x0FFFC000, &ccm->CCGR2);\n+\twritel(0x3FF00000, &ccm->CCGR3);\n+\twritel(0x00FFF300, &ccm->CCGR4);\n+\twritel(0x0F0000C3, &ccm->CCGR5);\n+\twritel(0x000003FF, &ccm->CCGR6);\n+}\n+\n+static void gpr_init(void)\n+{\n+\tstruct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;\n+\n+\t/* enable AXI cache for VDOA/VPU/IPU */\n+\twritel(0xF00000CF, &iomux->gpr[4]);\n+\tif (is_mx6dqp()) {\n+\t\t/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */\n+\t\twritel(0x007F007F, &iomux->gpr[6]);\n+\t\twritel(0x007F007F, &iomux->gpr[7]);\n+\t} else {\n+\t\t/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */\n+\t\twritel(0x007F007F, &iomux->gpr[6]);\n+\t\twritel(0x007F007F, &iomux->gpr[7]);\n+\t}\n+}\n+\n+static int mx6q_dcd_table[] = {\n+\t0x020e0798, 0x000C0000,\n+\t0x020e0758, 0x00000000,\n+\t0x020e0588, 0x00000030,\n+\t0x020e0594, 0x00000030,\n+\t0x020e056c, 0x00000030,\n+\t0x020e0578, 0x00000030,\n+\t0x020e074c, 0x00000030,\n+\t0x020e057c, 0x00000030,\n+\t0x020e058c, 0x00000000,\n+\t0x020e059c, 0x00000030,\n+\t0x020e05a0, 0x00000030,\n+\t0x020e078c, 0x00000030,\n+\t0x020e0750, 0x00020000,\n+\t0x020e05a8, 0x00000030,\n+\t0x020e05b0, 0x00000030,\n+\t0x020e0524, 0x00000030,\n+\t0x020e051c, 0x00000030,\n+\t0x020e0518, 0x00000030,\n+\t0x020e050c, 0x00000030,\n+\t0x020e05b8, 0x00000030,\n+\t0x020e05c0, 0x00000030,\n+\t0x020e0774, 0x00020000,\n+\t0x020e0784, 0x00000030,\n+\t0x020e0788, 0x00000030,\n+\t0x020e0794, 0x00000030,\n+\t0x020e079c, 0x00000030,\n+\t0x020e07a0, 0x00000030,\n+\t0x020e07a4, 0x00000030,\n+\t0x020e07a8, 0x00000030,\n+\t0x020e0748, 0x00000030,\n+\t0x020e05ac, 0x00000030,\n+\t0x020e05b4, 0x00000030,\n+\t0x020e0528, 0x00000030,\n+\t0x020e0520, 0x00000030,\n+\t0x020e0514, 0x00000030,\n+\t0x020e0510, 0x00000030,\n+\t0x020e05bc, 0x00000030,\n+\t0x020e05c4, 0x00000030,\n+\t0x021b0800, 0xa1390003,\n+\t0x021b080c, 0x001F001F,\n+\t0x021b0810, 0x001F001F,\n+\t0x021b480c, 0x001F001F,\n+\t0x021b4810, 0x001F001F,\n+\t0x021b083c, 0x43270338,\n+\t0x021b0840, 0x03200314,\n+\t0x021b483c, 0x431A032F,\n+\t0x021b4840, 0x03200263,\n+\t0x021b0848, 0x4B434748,\n+\t0x021b4848, 0x4445404C,\n+\t0x021b0850, 0x38444542,\n+\t0x021b4850, 0x4935493A,\n+\t0x021b081c, 0x33333333,\n+\t0x021b0820, 0x33333333,\n+\t0x021b0824, 0x33333333,\n+\t0x021b0828, 0x33333333,\n+\t0x021b481c, 0x33333333,\n+\t0x021b4820, 0x33333333,\n+\t0x021b4824, 0x33333333,\n+\t0x021b4828, 0x33333333,\n+\t0x021b08b8, 0x00000800,\n+\t0x021b48b8, 0x00000800,\n+\t0x021b0004, 0x00020036,\n+\t0x021b0008, 0x09444040,\n+\t0x021b000c, 0x555A7975,\n+\t0x021b0010, 0xFF538F64,\n+\t0x021b0014, 0x01FF00DB,\n+\t0x021b0018, 0x00001740,\n+\t0x021b001c, 0x00008000,\n+\t0x021b002c, 0x000026d2,\n+\t0x021b0030, 0x005A1023,\n+\t0x021b0040, 0x00000027,\n+\t0x021b0000, 0x831A0000,\n+\t0x021b001c, 0x04088032,\n+\t0x021b001c, 0x00008033,\n+\t0x021b001c, 0x00048031,\n+\t0x021b001c, 0x09408030,\n+\t0x021b001c, 0x04008040,\n+\t0x021b0020, 0x00005800,\n+\t0x021b0818, 0x00011117,\n+\t0x021b4818, 0x00011117,\n+\t0x021b0004, 0x00025576,\n+\t0x021b0404, 0x00011006,\n+\t0x021b001c, 0x00000000,\n+};\n+\n+static int mx6qp_dcd_table[] = {\n+\t0x020e0798, 0x000c0000,\n+\t0x020e0758, 0x00000000,\n+\t0x020e0588, 0x00000030,\n+\t0x020e0594, 0x00000030,\n+\t0x020e056c, 0x00000030,\n+\t0x020e0578, 0x00000030,\n+\t0x020e074c, 0x00000030,\n+\t0x020e057c, 0x00000030,\n+\t0x020e058c, 0x00000000,\n+\t0x020e059c, 0x00000030,\n+\t0x020e05a0, 0x00000030,\n+\t0x020e078c, 0x00000030,\n+\t0x020e0750, 0x00020000,\n+\t0x020e05a8, 0x00000030,\n+\t0x020e05b0, 0x00000030,\n+\t0x020e0524, 0x00000030,\n+\t0x020e051c, 0x00000030,\n+\t0x020e0518, 0x00000030,\n+\t0x020e050c, 0x00000030,\n+\t0x020e05b8, 0x00000030,\n+\t0x020e05c0, 0x00000030,\n+\t0x020e0774, 0x00020000,\n+\t0x020e0784, 0x00000030,\n+\t0x020e0788, 0x00000030,\n+\t0x020e0794, 0x00000030,\n+\t0x020e079c, 0x00000030,\n+\t0x020e07a0, 0x00000030,\n+\t0x020e07a4, 0x00000030,\n+\t0x020e07a8, 0x00000030,\n+\t0x020e0748, 0x00000030,\n+\t0x020e05ac, 0x00000030,\n+\t0x020e05b4, 0x00000030,\n+\t0x020e0528, 0x00000030,\n+\t0x020e0520, 0x00000030,\n+\t0x020e0514, 0x00000030,\n+\t0x020e0510, 0x00000030,\n+\t0x020e05bc, 0x00000030,\n+\t0x020e05c4, 0x00000030,\n+\t0x021b0800, 0xa1390003,\n+\t0x021b080c, 0x001b001e,\n+\t0x021b0810, 0x002e0029,\n+\t0x021b480c, 0x001b002a,\n+\t0x021b4810, 0x0019002c,\n+\t0x021b083c, 0x43240334,\n+\t0x021b0840, 0x0324031a,\n+\t0x021b483c, 0x43340344,\n+\t0x021b4840, 0x03280276,\n+\t0x021b0848, 0x44383A3E,\n+\t0x021b4848, 0x3C3C3846,\n+\t0x021b0850, 0x2e303230,\n+\t0x021b4850, 0x38283E34,\n+\t0x021b081c, 0x33333333,\n+\t0x021b0820, 0x33333333,\n+\t0x021b0824, 0x33333333,\n+\t0x021b0828, 0x33333333,\n+\t0x021b481c, 0x33333333,\n+\t0x021b4820, 0x33333333,\n+\t0x021b4824, 0x33333333,\n+\t0x021b4828, 0x33333333,\n+\t0x021b08c0, 0x24912249,\n+\t0x021b48c0, 0x24914289,\n+\t0x021b08b8, 0x00000800,\n+\t0x021b48b8, 0x00000800,\n+\t0x021b0004, 0x00020036,\n+\t0x021b0008, 0x24444040,\n+\t0x021b000c, 0x555A7955,\n+\t0x021b0010, 0xFF320F64,\n+\t0x021b0014, 0x01ff00db,\n+\t0x021b0018, 0x00001740,\n+\t0x021b001c, 0x00008000,\n+\t0x021b002c, 0x000026d2,\n+\t0x021b0030, 0x005A1023,\n+\t0x021b0040, 0x00000027,\n+\t0x021b0400, 0x14420000,\n+\t0x021b0000, 0x831A0000,\n+\t0x021b0890, 0x00400C58,\n+\t0x00bb0008, 0x00000000,\n+\t0x00bb000c, 0x2891E41A,\n+\t0x00bb0038, 0x00000564,\n+\t0x00bb0014, 0x00000040,\n+\t0x00bb0028, 0x00000020,\n+\t0x00bb002c, 0x00000020,\n+\t0x021b001c, 0x04088032,\n+\t0x021b001c, 0x00008033,\n+\t0x021b001c, 0x00048031,\n+\t0x021b001c, 0x09408030,\n+\t0x021b001c, 0x04008040,\n+\t0x021b0020, 0x00005800,\n+\t0x021b0818, 0x00011117,\n+\t0x021b4818, 0x00011117,\n+\t0x021b0004, 0x00025576,\n+\t0x021b0404, 0x00011006,\n+\t0x021b001c, 0x00000000,\n+};\n+\n+static int mx6dl_dcd_table[] = {\n+\t0x020e0774, 0x000C0000,\n+\t0x020e0754, 0x00000000,\n+\t0x020e04ac, 0x00000030,\n+\t0x020e04b0, 0x00000030,\n+\t0x020e0464, 0x00000030,\n+\t0x020e0490, 0x00000030,\n+\t0x020e074c, 0x00000030,\n+\t0x020e0494, 0x00000030,\n+\t0x020e04a0, 0x00000000,\n+\t0x020e04b4, 0x00000030,\n+\t0x020e04b8, 0x00000030,\n+\t0x020e076c, 0x00000030,\n+\t0x020e0750, 0x00020000,\n+\t0x020e04bc, 0x00000030,\n+\t0x020e04c0, 0x00000030,\n+\t0x020e04c4, 0x00000030,\n+\t0x020e04c8, 0x00000030,\n+\t0x020e04cc, 0x00000030,\n+\t0x020e04d0, 0x00000030,\n+\t0x020e04d4, 0x00000030,\n+\t0x020e04d8, 0x00000030,\n+\t0x020e0760, 0x00020000,\n+\t0x020e0764, 0x00000030,\n+\t0x020e0770, 0x00000030,\n+\t0x020e0778, 0x00000030,\n+\t0x020e077c, 0x00000030,\n+\t0x020e0780, 0x00000030,\n+\t0x020e0784, 0x00000030,\n+\t0x020e078c, 0x00000030,\n+\t0x020e0748, 0x00000030,\n+\t0x020e0470, 0x00000030,\n+\t0x020e0474, 0x00000030,\n+\t0x020e0478, 0x00000030,\n+\t0x020e047c, 0x00000030,\n+\t0x020e0480, 0x00000030,\n+\t0x020e0484, 0x00000030,\n+\t0x020e0488, 0x00000030,\n+\t0x020e048c, 0x00000030,\n+\t0x021b0800, 0xa1390003,\n+\t0x021b080c, 0x001F001F,\n+\t0x021b0810, 0x001F001F,\n+\t0x021b480c, 0x001F001F,\n+\t0x021b4810, 0x001F001F,\n+\t0x021b083c, 0x4220021F,\n+\t0x021b0840, 0x0207017E,\n+\t0x021b483c, 0x4201020C,\n+\t0x021b4840, 0x01660172,\n+\t0x021b0848, 0x4A4D4E4D,\n+\t0x021b4848, 0x4A4F5049,\n+\t0x021b0850, 0x3F3C3D31,\n+\t0x021b4850, 0x3238372B,\n+\t0x021b081c, 0x33333333,\n+\t0x021b0820, 0x33333333,\n+\t0x021b0824, 0x33333333,\n+\t0x021b0828, 0x33333333,\n+\t0x021b481c, 0x33333333,\n+\t0x021b4820, 0x33333333,\n+\t0x021b4824, 0x33333333,\n+\t0x021b4828, 0x33333333,\n+\t0x021b08b8, 0x00000800,\n+\t0x021b48b8, 0x00000800,\n+\t0x021b0004, 0x0002002D,\n+\t0x021b0008, 0x00333030,\n+\t0x021b000c, 0x3F435313,\n+\t0x021b0010, 0xB66E8B63,\n+\t0x021b0014, 0x01FF00DB,\n+\t0x021b0018, 0x00001740,\n+\t0x021b001c, 0x00008000,\n+\t0x021b002c, 0x000026d2,\n+\t0x021b0030, 0x00431023,\n+\t0x021b0040, 0x00000027,\n+\t0x021b0000, 0x831A0000,\n+\t0x021b001c, 0x04008032,\n+\t0x021b001c, 0x00008033,\n+\t0x021b001c, 0x00048031,\n+\t0x021b001c, 0x05208030,\n+\t0x021b001c, 0x04008040,\n+\t0x021b0020, 0x00005800,\n+\t0x021b0818, 0x00011117,\n+\t0x021b4818, 0x00011117,\n+\t0x021b0004, 0x0002556D,\n+\t0x021b0404, 0x00011006,\n+\t0x021b001c, 0x00000000,\n+};\n+\n+static void ddr_init(int *table, int size)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < size / 2 ; i++)\n+\t\twritel(table[2 * i + 1], table[2 * i]);\n+}\n+\n+static void spl_dram_init(void)\n+{\n+\tif (is_mx6dq())\n+\t\tddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));\n+\telse if (is_mx6dqp())\n+\t\tddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));\n+\telse if (is_mx6sdl())\n+\t\tddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));\n+}\n+\n+void board_init_f(ulong dummy)\n+{\n+\t/* DDR initialization */\n+\tspl_dram_init();\n+\n+\t/* setup AIPS and disable watchdog */\n+\tarch_cpu_init();\n+\n+\tccgr_init();\n+\tgpr_init();\n+\n+\t/* iomux and setup of i2c */\n+\tboard_early_init_f();\n+\n+\t/* setup GP timer */\n+\ttimer_init();\n+\n+\t/* UART clocks enabled and gd valid - init serial console */\n+\tpreloader_console_init();\n+\n+\t/* Clear the BSS. */\n+\tmemset(__bss_start, 0, __bss_end - __bss_start);\n+\n+\t/* load/boot image from boot device */\n+\tboard_init_r(NULL, 0);\n+}\ndiff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig\nindex 2bfacb9..33e84f0 100644\n--- a/configs/mx6sabresd_spl_defconfig\n+++ b/configs/mx6sabresd_spl_defconfig\n@@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y\n CONFIG_SPL_LIBDISK_SUPPORT=y\n CONFIG_SPL_WATCHDOG_SUPPORT=y\n CONFIG_VIDEO=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"imx6q-sabresd\"\n CONFIG_SYS_EXTRA_OPTIONS=\"IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL\"\n CONFIG_BOOTDELAY=3\n # CONFIG_CONSOLE_MUX is not set\n@@ -48,3 +49,5 @@ CONFIG_G_DNL_VENDOR_NUM=0x0525\n CONFIG_G_DNL_PRODUCT_NUM=0xa4a5\n # CONFIG_VIDEO_SW_CURSOR is not set\n CONFIG_OF_LIBFDT=y\n+# CONFIG_BLK is not set\n+# CONFIG_DM_MMC_OPS is not set\ndiff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h\nindex a8c0e03..43a4aac 100644\n--- a/include/configs/mx6sabresd.h\n+++ b/include/configs/mx6sabresd.h\n@@ -11,6 +11,10 @@\n \n #ifdef CONFIG_SPL\n #include \"imx6_spl.h\"\n+# ifdef CONFIG_SPL_BUILD\n+#  undef CONFIG_DM_GPIO\n+#  undef CONFIG_DM_MMC\n+# endif\n #endif\n \n #define CONFIG_MACH_TYPE\t3980\n@@ -34,7 +38,6 @@\n #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)\n #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */\n \n-#define CONFIG_SYS_FSL_USDHC_NUM\t3\n #if defined(CONFIG_ENV_IS_IN_MMC)\n #define CONFIG_SYS_MMC_ENV_DEV\t\t1\t/* SDHC3 */\n #endif\n",
    "prefixes": [
        "U-Boot",
        "v7",
        "07/17"
    ]
}