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GET /api/patches/763796/?format=api
{ "id": 763796, "url": "http://patchwork.ozlabs.org/api/patches/763796/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170517221746.15538.89916.stgit@localhost6.localdomain6/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170517221746.15538.89916.stgit@localhost6.localdomain6>", "list_archive_url": null, "date": "2017-05-17T22:17:46", "name": "[2/5] ixgbe: add write flush when configuring CS4223/7", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "617fbc29c16dd8ed8570e64ed98310a78c417db6", "submitter": { "id": 1670, "url": "http://patchwork.ozlabs.org/api/people/1670/?format=api", "name": "Tantilov, Emil S", "email": "emil.s.tantilov@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170517221746.15538.89916.stgit@localhost6.localdomain6/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/763796/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/763796/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3wSph44LXRz9s06\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 18 May 2017 08:21:40 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 2AD2C87FC9;\n\tWed, 17 May 2017 22:21:39 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 54O_0Ddv5_pt; Wed, 17 May 2017 22:21:37 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 78D3887FC7;\n\tWed, 17 May 2017 22:21:37 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 30AB61C2092\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 17 May 2017 22:21:36 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 2B0DD89819\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 17 May 2017 22:21:36 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id eRcVckNeG0YY for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 17 May 2017 22:21:35 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 3EEDB896FD\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 17 May 2017 22:21:35 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t17 May 2017 15:21:34 -0700", "from estantil-desk3.jf.intel.com (HELO localhost6.localdomain6)\n\t([134.134.177.78])\n\tby orsmga004.jf.intel.com with ESMTP; 17 May 2017 15:21:34 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.38,356,1491289200\"; d=\"scan'208\";a=\"88577138\"", "From": "Emil Tantilov <emil.s.tantilov@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 17 May 2017 15:17:46 -0700", "Message-ID": "<20170517221746.15538.89916.stgit@localhost6.localdomain6>", "In-Reply-To": "<20170517221424.15538.5968.stgit@localhost6.localdomain6>", "References": "<20170517221424.15538.5968.stgit@localhost6.localdomain6>", "User-Agent": "StGit/0.17.1-17-ge4e0", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH 2/5] ixgbe: add write flush when\n\tconfiguring CS4223/7", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Make sure the writes are processed immediately. Without the flush it\nis possible for operations on one port to spill over the other as the\nresource is shared.\n\nSigned-off-by: Emil Tantilov <emil.s.tantilov@intel.com>\n---\n drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c | 20 ++++++++++++++++++--\n 1 file changed, 18 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\nindex 870f9e1..cb5d363 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\n@@ -1824,12 +1824,28 @@ static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)\n \n \t/* Configure CS4227/CS4223 LINE side to proper mode. */\n \treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;\n+\n+\tret_val = hw->phy.ops.read_reg(hw, reg_slice,\n+\t\t\t\t IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\treg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |\n+\t\t\t (IXGBE_CS4227_EDC_MODE_SR << 1));\n+\n \tif (setup_linear)\n \t\treg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;\n \telse\n \t\treg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;\n-\treturn hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE,\n-\t\t\t\t reg_phy_ext);\n+\n+\tret_val = hw->phy.ops.write_reg(hw, reg_slice,\n+\t\t\t\t\tIXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);\n+\tif (ret_val)\n+\t\treturn ret_val;\n+\n+\t/* Flush previous write with a read */\n+\treturn hw->phy.ops.read_reg(hw, reg_slice,\n+\t\t\t\t IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);\n }\n \n /**\n", "prefixes": [ "2/5" ] }