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{
    "id": 762605,
    "url": "http://patchwork.ozlabs.org/api/patches/762605/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1494864969-7374-2-git-send-email-york.sun@nxp.com/",
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        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
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    "msgid": "<1494864969-7374-2-git-send-email-york.sun@nxp.com>",
    "list_archive_url": null,
    "date": "2017-05-15T16:16:01",
    "name": "[U-Boot,v1,1/9] armv8: ls1043ardb: Use static DDR setting for SPL secure boot",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "de33548dd1286850f2db7aa2c7d2d55798e5064b",
    "submitter": {
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        "name": "York Sun",
        "email": "york.sun@nxp.com"
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        "username": "yorksun",
        "first_name": "York",
        "last_name": "Sun",
        "email": "yorksun@freescale.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1494864969-7374-2-git-send-email-york.sun@nxp.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/762605/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/762605/checks/",
    "tags": {},
    "related": [],
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        "From": "York Sun <york.sun@nxp.com>",
        "To": "U-Boot Mailing List <u-boot@lists.denx.de>",
        "Date": "Mon, 15 May 2017 09:16:01 -0700",
        "Message-ID": "<1494864969-7374-2-git-send-email-york.sun@nxp.com>",
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        "Cc": "Mingkai Hu <Mingkai.hu@freescale.com>,\n\tRuchika Gupta <ruchika.gupta@nxp.com>",
        "Subject": "[U-Boot] [PATCH v1 1/9] armv8: ls1043ardb: Use static DDR setting\n\tfor SPL secure boot",
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    },
    "content": "This board has soldered DDR chips. To reduce the SPL image size for\nsecure boot, use static DDR setting instead of dynamic DDR driver.\n\nSigned-off-by: York Sun <york.sun@nxp.com>\n---\n\n board/freescale/ls1043ardb/ddr.c | 46 +++++++++++++++++++++++++++\n board/freescale/ls1043ardb/ddr.h | 67 ++++++++++++++++++++++++++++++++++++++++\n include/configs/ls1043ardb.h     |  8 +++--\n 3 files changed, 118 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c\nindex 36d27ec..a3f1767 100644\n--- a/board/freescale/ls1043ardb/ddr.c\n+++ b/board/freescale/ls1043ardb/ddr.c\n@@ -168,18 +168,64 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,\n \n \treturn 0;\n }\n+#else\n+\n+phys_size_t fixed_sdram(void)\n+{\n+\tint i;\n+\tchar buf[32];\n+\tfsl_ddr_cfg_regs_t ddr_cfg_regs;\n+\tphys_size_t ddr_size;\n+\tulong ddr_freq, ddr_freq_mhz;\n+\n+\tddr_freq = get_ddr_freq(0);\n+\tddr_freq_mhz = ddr_freq / 1000000;\n+\n+\tprintf(\"Configuring DDR for %s MT/s data rate\\n\",\n+\t       strmhz(buf, ddr_freq));\n+\n+\tfor (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {\n+\t\tif ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&\n+\t\t    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {\n+\t\t\tmemcpy(&ddr_cfg_regs,\n+\t\t\t       fixed_ddr_parm_0[i].ddr_settings,\n+\t\t\t       sizeof(ddr_cfg_regs));\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (fixed_ddr_parm_0[i].max_freq == 0)\n+\t\tpanic(\"Unsupported DDR data rate %s MT/s data rate\\n\",\n+\t\t      strmhz(buf, ddr_freq));\n+\n+\tddr_size = (phys_size_t) 2048 * 1024 * 1024;\n+\tfsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);\n+\n+\treturn ddr_size;\n+}\n #endif\n \n int fsl_initdram(void)\n {\n \tphys_size_t dram_size;\n \n+#ifdef CONFIG_SYS_DDR_RAW_TIMING\n #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)\n \tputs(\"Initializing DDR....\\n\");\n \tdram_size = fsl_ddr_sdram();\n #else\n \tdram_size =  fsl_ddr_sdram_size();\n #endif\n+#else\n+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)\n+\tputs(\"Initialzing DDR using fixed setting\\n\");\n+\tdram_size = fixed_sdram();\n+#else\n+\tgd->ram_size = 0x80000000;\n+\n+\treturn 0;\n+#endif\n+#endif\n \terratum_a008850_post();\n \n #ifdef CONFIG_FSL_DEEP_SLEEP\ndiff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h\nindex a77ddf3..926eff8 100644\n--- a/board/freescale/ls1043ardb/ddr.h\n+++ b/board/freescale/ls1043ardb/ddr.h\n@@ -45,4 +45,71 @@ static const struct board_specific_parameters *udimms[] = {\n \tudimm0,\n };\n \n+#ifndef CONFIG_SYS_DDR_RAW_TIMING\n+fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {\n+\t.cs[0].bnds = 0x0000007F,\n+\t.cs[1].bnds = 0,\n+\t.cs[2].bnds = 0,\n+\t.cs[3].bnds = 0,\n+\t.cs[0].config = 0x80040322,\n+\t.cs[0].config_2 = 0,\n+\t.cs[1].config = 0,\n+\t.cs[1].config_2 = 0,\n+\t.cs[2].config = 0,\n+\t.cs[3].config = 0,\n+\t.timing_cfg_3 = 0x010C1000,\n+\t.timing_cfg_0 = 0x91550018,\n+\t.timing_cfg_1 = 0xBBB48C42,\n+\t.timing_cfg_2 = 0x0048C111,\n+\t.ddr_sdram_cfg = 0xC50C0008,\n+\t.ddr_sdram_cfg_2 = 0x00401100,\n+\t.ddr_sdram_cfg_3 = 0,\n+\t.ddr_sdram_mode = 0x03010210,\n+\t.ddr_sdram_mode_2 = 0,\n+\t.ddr_sdram_mode_3 = 0x00010210,\n+\t.ddr_sdram_mode_4 = 0,\n+\t.ddr_sdram_mode_5 = 0x00010210,\n+\t.ddr_sdram_mode_6 = 0,\n+\t.ddr_sdram_mode_7 = 0x00010210,\n+\t.ddr_sdram_mode_8 = 0,\n+\t.ddr_sdram_mode_9 = 0x00000500,\n+\t.ddr_sdram_mode_10 = 0x04000000,\n+\t.ddr_sdram_mode_11 = 0x00000400,\n+\t.ddr_sdram_mode_12 = 0x04000000,\n+\t.ddr_sdram_mode_13 = 0x00000400,\n+\t.ddr_sdram_mode_14 = 0x04000000,\n+\t.ddr_sdram_mode_15 = 0x00000400,\n+\t.ddr_sdram_mode_16 = 0x04000000,\n+\t.ddr_sdram_interval = 0x18600618,\n+\t.ddr_data_init = 0xDEADBEEF,\n+\t.ddr_sdram_clk_cntl = 0x03000000,\n+\t.ddr_init_addr = 0,\n+\t.ddr_init_ext_addr = 0,\n+\t.timing_cfg_4 = 0x00000002,\n+\t.timing_cfg_5 = 0x03401400,\n+\t.timing_cfg_6 = 0,\n+\t.timing_cfg_7 = 0x13300000,\n+\t.timing_cfg_8 = 0x02115600,\n+\t.timing_cfg_9 = 0,\n+\t.ddr_zq_cntl = 0x8A090705,\n+\t.ddr_wrlvl_cntl = 0x8675F607,\n+\t.ddr_wrlvl_cntl_2 = 0x07090800,\n+\t.ddr_wrlvl_cntl_3 = 0,\n+\t.ddr_sr_cntr = 0,\n+\t.ddr_sdram_rcw_1 = 0,\n+\t.ddr_sdram_rcw_2 = 0,\n+\t.ddr_cdr1 = 0x80040000,\n+\t.ddr_cdr2 = 0x0000A181,\n+\t.dq_map_0 = 0,\n+\t.dq_map_1 = 0,\n+\t.dq_map_2 = 0,\n+\t.dq_map_3 = 0,\n+\t.debug[28] = 0x00700046,\n+\n+};\n+fixed_ddr_parm_t fixed_ddr_parm_0[] = {\n+\t{1550, 1650, &ddr_cfg_regs_1600},\n+\t{0, 0, NULL}\n+};\n+#endif\n #endif\ndiff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h\nindex 5e570cd..7bac8b6 100644\n--- a/include/configs/ls1043ardb.h\n+++ b/include/configs/ls1043ardb.h\n@@ -28,13 +28,15 @@\n \n #define CONFIG_SYS_SPD_BUS_NUM\t\t0\n \n-#define CONFIG_FSL_DDR_BIST\n #ifndef CONFIG_SPL\n-#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n-#endif\n+#ifndef CONFIG_SECURE_BOOT\n #define CONFIG_SYS_DDR_RAW_TIMING\n+#endif\n+#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n+#define CONFIG_FSL_DDR_BIST\n #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\n #define CONFIG_MEM_INIT_VALUE           0xdeadbeef\n+#endif\n \n #ifdef CONFIG_RAMBOOT_PBL\n #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg\n",
    "prefixes": [
        "U-Boot",
        "v1",
        "1/9"
    ]
}