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GET /api/patches/748051/?format=api
{ "id": 748051, "url": "http://patchwork.ozlabs.org/api/patches/748051/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/1491544885.4166.153.camel@kernel.crashing.org/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1491544885.4166.153.camel@kernel.crashing.org>", "list_archive_url": null, "date": "2017-04-07T06:01:25", "name": "[2/2] xive: Fixes/improvements to xive reset for multi-chip systems", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "7c04544b711602b649a15514c48bc0c8210c9310", "submitter": { "id": 38, "url": "http://patchwork.ozlabs.org/api/people/38/?format=api", "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/1491544885.4166.153.camel@kernel.crashing.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/748051/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/748051/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vzpqn0qGxz9s7m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 7 Apr 2017 16:01:41 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3vzpqn02HlzDqHg\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 7 Apr 2017 16:01:41 +1000 (AEST)", "from gate.crashing.org (gate.crashing.org [63.228.1.57])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3vzpqb1wNBzDqJl\n\tfor <skiboot@lists.ozlabs.org>; Fri, 7 Apr 2017 16:01:31 +1000 (AEST)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby gate.crashing.org (8.14.1/8.13.8) with ESMTP id v3761PeA014148\n\tfor <skiboot@lists.ozlabs.org>; Fri, 7 Apr 2017 01:01:26 -0500" ], "Message-ID": "<1491544885.4166.153.camel@kernel.crashing.org>", "From": "Benjamin Herrenschmidt <benh@kernel.crashing.org>", "To": "skiboot@lists.ozlabs.org", "Date": "Fri, 07 Apr 2017 16:01:25 +1000", "X-Mailer": "Evolution 3.22.6 (3.22.6-1.fc25) ", "Mime-Version": "1.0", "Subject": "[Skiboot] [PATCH 2/2] xive: Fixes/improvements to xive reset for\n\tmulti-chip systems", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "On such systems, we really need to mask all the sources first,\nthen synchronize all the XIVEs, before we start whacking their\nEQs, VPs etc...\n\nSo this reworks the reset sequence to do that, using the new\nirq_for_each_source() iterator to get all the registered sources\ninto a clean off state, and separating the sync pass from the\nreset pass.\n\nThis also fixes a problem where the ipi_alloc_map wasn't being\nproperly reset.\n\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\n---\n hw/xive.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++-------------\n 1 file changed, 75 insertions(+), 19 deletions(-)", "diff": "diff --git a/hw/xive.c b/hw/xive.c\nindex 9713e8f..8b83f96 100644\n--- a/hw/xive.c\n+++ b/hw/xive.c\n@@ -2373,7 +2373,7 @@ static int64_t xive_sync(struct xive *x)\n \n static int64_t __xive_set_irq_config(struct irq_source *is, uint32_t girq,\n \t\t\t\t uint64_t vp, uint8_t prio, uint32_t lirq,\n-\t\t\t\t bool update_esb)\n+\t\t\t\t bool update_esb, bool no_sync)\n {\n \tstruct xive_src *s = container_of(is, struct xive_src, is);\n \tuint32_t old_target, vp_blk;\n@@ -2417,6 +2417,8 @@ static int64_t __xive_set_irq_config(struct irq_source *is, uint32_t girq,\n \t * WARNING: This assumes the VP and it's queues are on the same\n \t * XIVE instance !\n \t */\n+\tif (no_sync)\n+\t\treturn OPAL_SUCCESS;\n \txive_sync(s->xive);\n \tif (xive_decode_vp(old_target, &vp_blk, NULL, NULL, NULL)) {\n \t\tstruct xive *x = xive_from_pc_blk(vp_blk);\n@@ -2432,10 +2434,11 @@ static int64_t xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,\n {\n \tstruct irq_source *is = irq_find_source(girq);\n \n-\treturn __xive_set_irq_config(is, girq, vp, prio, lirq, update_esb);\n+\treturn __xive_set_irq_config(is, girq, vp, prio, lirq, update_esb,\n+\t\t\t\t false);\n }\n \n-static int64_t xive_source_set_xive(struct irq_source *is __unused,\n+static int64_t xive_source_set_xive(struct irq_source *is,\n \t\t\t\t uint32_t isn, uint16_t server, uint8_t prio)\n {\n \t/*\n@@ -2457,7 +2460,7 @@ static int64_t xive_source_set_xive(struct irq_source *is __unused,\n \tserver >>= 2;\n \n \t/* Set logical irq to match isn */\n-\treturn xive_set_irq_config(isn, server, prio, isn, true);\n+\treturn __xive_set_irq_config(is, isn, server, prio, isn, true, false);\n }\n \n void __xive_source_eoi(struct irq_source *is, uint32_t isn)\n@@ -2740,7 +2743,8 @@ static void xive_ipi_init(struct xive *x, struct cpu_thread *cpu)\n \tassert(xs);\n \n \t__xive_set_irq_config(&x->ipis.is, xs->ipi_irq, cpu->pir,\n-\t\t\t XIVE_EMULATION_PRIO, xs->ipi_irq, true);\n+\t\t\t XIVE_EMULATION_PRIO, xs->ipi_irq,\n+\t\t\t true, false);\n }\n \n static void xive_ipi_eoi(struct xive *x, uint32_t idx)\n@@ -2809,7 +2813,9 @@ void xive_cpu_callin(struct cpu_thread *cpu)\n \t/* Set VT to 1 */\n \tout_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2, 0x80);\n \n-\txive_cpu_dbg(cpu, \"Initialized interrupt management area\\n\");\n+\txive_cpu_dbg(cpu, \"Initialized TMA (VP: %x/%x W01=%016llx)\\n\",\n+\t\t xs->vp_blk, xs->vp_idx,\n+\t\t in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS));\n }\n \n static void xive_setup_hw_for_emu(struct xive_cpu_state *xs)\n@@ -3741,7 +3747,7 @@ static int64_t opal_xive_set_vp_info(uint64_t vp_id,\n \treturn OPAL_SUCCESS;\n }\n \n-static void xive_cleanup_cpu_cam(struct cpu_thread *c)\n+static void xive_cleanup_cpu_tma(struct cpu_thread *c)\n {\n \tstruct xive_cpu_state *xs = c->xstate;\n \tstruct xive *x = xs->xive;\n@@ -3760,6 +3766,11 @@ static void xive_cleanup_cpu_cam(struct cpu_thread *c)\n \t/* Set HV CPPR to 0 */\n \tout_8(ind_tm_base + TM_QW3_HV_PHYS + TM_CPPR, 0);\n \n+\t/* Dump HV state */\n+\txive_cpu_dbg(c, \"[reset] VP %x/%x W01 state: %016llx\\n\",\n+\t\t xs->vp_blk, xs->vp_idx,\n+\t\t in_be64(ind_tm_base + TM_QW3_HV_PHYS));\n+\n \t/* Reset indirect access */\n \txive_regw(x, PC_TCTXT_INDIR0, 0);\n }\n@@ -3768,19 +3779,24 @@ static void xive_reset_one(struct xive *x)\n {\n \tstruct cpu_thread *c;\n \tbool eq_firmware;\n-\tint i = 0;\n+\tint i;\n \n-\t/* Mask all interrupt sources */\n-\twhile ((i = bitmap_find_one_bit(*x->int_enabled_map,\n-\t\t\t\t\ti, MAX_INT_ENTRIES - i)) >= 0) {\n-\t\txive_set_irq_config(x->int_base + i, 0, 0xff,\n-\t\t\t\t x->int_base + i, true);\n-\t\ti++;\n-\t}\n-\txive_sync(x);\n+\txive_dbg(x, \"Resetting one xive...\\n\");\n \n \tlock(&x->lock);\n-\tmemset(x->int_enabled_map, 0, BITMAP_BYTES(MAX_INT_ENTRIES));\n+\n+\t/* Check all interrupts are disabled */\n+\ti = bitmap_find_one_bit(*x->int_enabled_map, 0, MAX_INT_ENTRIES);\n+\tif (i >= 0)\n+\t\txive_warn(x, \"Interrupt %d (and maybe more) not disabled\"\n+\t\t\t \" at reset !\\n\", i);\n+\n+\t/* Reset IPI allocation */\n+\txive_dbg(x, \"freeing alloc map %p/%p\\n\",\n+\t\t x->ipi_alloc_map, *x->ipi_alloc_map);\n+\tmemset(x->ipi_alloc_map, 0, BITMAP_BYTES(MAX_INT_ENTRIES));\n+\n+\txive_dbg(x, \"Resetting EQs...\\n\");\n \n \t/* Reset all allocated EQs and free the user ones */\n \tbitmap_for_each_one(*x->eq_map, MAX_EQ_COUNT >> 3, i) {\n@@ -3819,7 +3835,7 @@ static void xive_reset_one(struct xive *x)\n \t\t\tcontinue;\n \t\tif (!c->xstate)\n \t\t\tcontinue;\n-\t\txive_cleanup_cpu_cam(c);\n+\t\txive_cleanup_cpu_tma(c);\n \t}\n \n \t/* Reset all user-allocated VPs. This is inefficient, we should\n@@ -3873,16 +3889,56 @@ static void xive_reset_one(struct xive *x)\n \t}\n }\n \n+static void xive_reset_mask_source_cb(struct irq_source *is,\n+\t\t\t\t void *data __unused)\n+{\n+\tstruct xive_src *s = container_of(is, struct xive_src, is);\n+\tstruct xive *x;\n+\tuint32_t isn;\n+\n+\tif (is->ops != &xive_irq_source_ops)\n+\t\treturn;\n+\n+\t/* Skip escalation sources */\n+\tif (GIRQ_IS_ESCALATION(is->start))\n+\t\treturn;\n+\n+\tx = s->xive;\n+\n+\t/* Iterate all interrupts */\n+\tfor (isn = is->start; isn < is->end; isn++) {\n+\t\t/* Has it ever been enabled ? */\n+\t\tif (!bitmap_tst_bit(*x->int_enabled_map, GIRQ_TO_IDX(isn)))\n+\t\t\tcontinue;\n+\t\t/* Mask it and clear the enabled map bit */\n+\t\txive_dbg(x, \"[reset] disabling source 0x%x\\n\", isn);\n+\t\t__xive_set_irq_config(is, isn, 0, 0xff, isn, true, true);\n+\t\tbitmap_clr_bit(*x->int_enabled_map, GIRQ_TO_IDX(isn));\n+\t}\n+}\n+\n static int64_t opal_xive_reset(uint64_t version)\n {\n \tstruct proc_chip *chip;\n \n+\tprlog(PR_DEBUG, \"XIVE reset, version: %d...\\n\", (int)version);\n+\n \tif (version > 1)\n \t\treturn OPAL_PARAMETER;\n \n \txive_mode = version;\n \n-\t/* For each XIVE ... */\n+\t/* Mask all interrupt sources */\n+\tirq_for_each_source(xive_reset_mask_source_cb, NULL);\n+\n+\t/* For each XIVE do a sync... */\n+\tfor_each_chip(chip) {\n+\t\tif (!chip->xive)\n+\t\t\tcontinue;\n+\t\txive_sync(chip->xive);\n+\t}\n+\n+\t/* For each XIVE reset everything else... */\n \tfor_each_chip(chip) {\n \t\tif (!chip->xive)\n \t\t\tcontinue;\n", "prefixes": [ "2/2" ] }