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GET /api/patches/747628/?format=api
{ "id": 747628, "url": "http://patchwork.ozlabs.org/api/patches/747628/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170406072647.10753-1-sasha.neftin@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170406072647.10753-1-sasha.neftin@intel.com>", "list_archive_url": null, "date": "2017-04-06T07:26:47", "name": "[2/3] e1000e: Add Support for CannonLake", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "2b93a8a664dd170e591c37b820d0fd502af8ba69", "submitter": { "id": 69860, "url": "http://patchwork.ozlabs.org/api/people/69860/?format=api", "name": "Sasha Neftin", "email": "sasha.neftin@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170406072647.10753-1-sasha.neftin@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/747628/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/747628/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vzDmp2RDSz9s8S\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 6 Apr 2017 17:27:06 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 9637430283;\n\tThu, 6 Apr 2017 07:27:04 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id DOZ2n0W-kBs2; Thu, 6 Apr 2017 07:27:01 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 825CA3021A;\n\tThu, 6 Apr 2017 07:27:01 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id 323151C03CF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 6 Apr 2017 07:27:00 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 305D484E77\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 6 Apr 2017 07:27:00 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Z5w1whuMCW6G for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 6 Apr 2017 07:26:58 +0000 (UTC)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id 1ECB2835DA\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 6 Apr 2017 07:26:58 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga104.jf.intel.com with ESMTP; 06 Apr 2017 00:26:57 -0700", "from ccdlinuxdev01.ger.corp.intel.com (HELO\n\tccdlinuxdev01.iil.intel.com) ([143.185.162.145])\n\tby FMSMGA003.fm.intel.com with ESMTP; 06 Apr 2017 00:26:51 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.37,283,1488873600\"; d=\"scan'208\";a=\"842545720\"", "From": "Sasha Neftin <sasha.neftin@intel.com>", "To": "intel-wired-lan@lists.osuosl.org,\n\tjeffrey.t.kirsher@intel.com", "Date": "Thu, 6 Apr 2017 10:26:47 +0300", "Message-Id": "<20170406072647.10753-1-sasha.neftin@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH 2/3] e1000e: Add Support for CannonLake", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "Description: propagation of CannonLake mac type to\ndriver functionality\n\nReviewed-by: Raanan Avargil <raanan.avargil@intel.com>\nReviewed-by: Dima Ruinskiy <dima.ruinskiy@intel.com>\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\n---\n drivers/net/ethernet/intel/e1000e/ethtool.c | 10 ++--\n drivers/net/ethernet/intel/e1000e/ich8lan.c | 82 +++++++++++++++--------------\n drivers/net/ethernet/intel/e1000e/netdev.c | 29 +++++-----\n drivers/net/ethernet/intel/e1000e/ptp.c | 4 +-\n 4 files changed, 63 insertions(+), 62 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c\nindex 7aff68a4a4df..fc97ecc1d704 100644\n--- a/drivers/net/ethernet/intel/e1000e/ethtool.c\n+++ b/drivers/net/ethernet/intel/e1000e/ethtool.c\n@@ -904,19 +904,20 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)\n \tcase e1000_pch2lan:\n \tcase e1000_pch_lpt:\n \tcase e1000_pch_spt:\n+\t\t/* fall through */\n+\tcase e1000_pch_cnp:\n \t\tmask |= BIT(18);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n \n-\tif ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt))\n+\tif (mac->type >= e1000_pch_lpt)\n \t\twlock_mac = (er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK) >>\n \t\t E1000_FWSM_WLOCK_MAC_SHIFT;\n \n \tfor (i = 0; i < mac->rar_entry_count; i++) {\n-\t\tif ((mac->type == e1000_pch_lpt) ||\n-\t\t (mac->type == e1000_pch_spt)) {\n+\t\tif (mac->type >= e1000_pch_lpt) {\n \t\t\t/* Cannot test write-protected SHRAL[n] registers */\n \t\t\tif ((wlock_mac == 1) || (wlock_mac && (i > wlock_mac)))\n \t\t\t\tcontinue;\n@@ -1525,7 +1526,7 @@ static int e1000_setup_loopback_test(struct e1000_adapter *adapter)\n \tstruct e1000_hw *hw = &adapter->hw;\n \tu32 rctl, fext_nvm11, tarc0;\n \n-\tif (hw->mac.type == e1000_pch_spt) {\n+\tif (hw->mac.type >= e1000_pch_spt) {\n \t\tfext_nvm11 = er32(FEXTNVM11);\n \t\tfext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;\n \t\tew32(FEXTNVM11, fext_nvm11);\n@@ -1569,6 +1570,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)\n \n \tswitch (hw->mac.type) {\n \tcase e1000_pch_spt:\n+\tcase e1000_pch_cnp:\n \t\tfext_nvm11 = er32(FEXTNVM11);\n \t\tfext_nvm11 &= ~E1000_FEXTNVM11_DISABLE_MULR_FIX;\n \t\tew32(FEXTNVM11, fext_nvm11);\ndiff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c\nindex bf55e30f147d..6da4ead628fa 100644\n--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c\n+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c\n@@ -237,7 +237,7 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)\n \tif (ret_val)\n \t\treturn false;\n out:\n-\tif ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\t/* Only unforce SMBus if ME is not active */\n \t\tif (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {\n \t\t\t/* Unforce SMBus mode in PHY */\n@@ -333,6 +333,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)\n \tswitch (hw->mac.type) {\n \tcase e1000_pch_lpt:\n \tcase e1000_pch_spt:\n+\tcase e1000_pch_cnp:\n \t\tif (e1000_phy_is_accessible_pchlan(hw))\n \t\t\tbreak;\n \n@@ -474,6 +475,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)\n \t\tcase e1000_pch2lan:\n \t\tcase e1000_pch_lpt:\n \t\tcase e1000_pch_spt:\n+\t\tcase e1000_pch_cnp:\n \t\t\t/* In case the PHY needs to be in mdio slow mode,\n \t\t\t * set slow mode and try to get the PHY id again.\n \t\t\t */\n@@ -607,7 +609,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)\n \n \tnvm->type = e1000_nvm_flash_sw;\n \n-\tif (hw->mac.type == e1000_pch_spt) {\n+\tif (hw->mac.type >= e1000_pch_spt) {\n \t\t/* in SPT, gfpreg doesn't exist. NVM size is taken from the\n \t\t * STRAP register. This is because in SPT the GbE Flash region\n \t\t * is no longer accessed through the flash registers. Instead,\n@@ -715,6 +717,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)\n \t\t/* fall-through */\n \tcase e1000_pch_lpt:\n \tcase e1000_pch_spt:\n+\tcase e1000_pch_cnp:\n \tcase e1000_pchlan:\n \t\t/* check management mode */\n \t\tmac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;\n@@ -732,7 +735,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)\n \t\tbreak;\n \t}\n \n-\tif ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt)) {\n+\tif (mac->type >= e1000_pch_lpt) {\n \t\tmac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;\n \t\tmac->ops.rar_set = e1000_rar_set_pch_lpt;\n \t\tmac->ops.setup_physical_interface =\n@@ -1399,9 +1402,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t * aggressive resulting in many collisions. To avoid this, increase\n \t * the IPG and reduce Rx latency in the PHY.\n \t */\n-\tif (((hw->mac.type == e1000_pch2lan) ||\n-\t (hw->mac.type == e1000_pch_lpt) ||\n-\t (hw->mac.type == e1000_pch_spt)) && link) {\n+\tif ((hw->mac.type >= e1000_pch2lan) && link) {\n \t\tu16 speed, duplex;\n \n \t\te1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);\n@@ -1412,7 +1413,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t\t\ttipg_reg |= 0xFF;\n \t\t\t/* Reduce Rx latency in analog PHY */\n \t\t\temi_val = 0;\n-\t\t} else if (hw->mac.type == e1000_pch_spt &&\n+\t\t} else if (hw->mac.type >= e1000_pch_spt &&\n \t\t\t duplex == FULL_DUPLEX && speed != SPEED_1000) {\n \t\t\ttipg_reg |= 0xC;\n \t\t\temi_val = 1;\n@@ -1435,8 +1436,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t\t\temi_addr = I217_RX_CONFIG;\n \t\tret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);\n \n-\t\tif (hw->mac.type == e1000_pch_lpt ||\n-\t\t hw->mac.type == e1000_pch_spt) {\n+\t\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\t\tu16 phy_reg;\n \n \t\t\te1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);\n@@ -1452,7 +1452,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t\tif (ret_val)\n \t\t\treturn ret_val;\n \n-\t\tif (hw->mac.type == e1000_pch_spt) {\n+\t\tif (hw->mac.type >= e1000_pch_spt) {\n \t\t\tu16 data;\n \t\t\tu16 ptr_gap;\n \n@@ -1502,7 +1502,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t * on power up.\n \t * Set the Beacon Duration for I217 to 8 usec\n \t */\n-\tif ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\tu32 mac_reg;\n \n \t\tmac_reg = er32(FEXTNVM4);\n@@ -1520,8 +1520,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t\tif (ret_val)\n \t\t\treturn ret_val;\n \t}\n-\tif ((hw->mac.type == e1000_pch_lpt) ||\n-\t (hw->mac.type == e1000_pch_spt)) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\t/* Set platform power management values for\n \t\t * Latency Tolerance Reporting (LTR)\n \t\t */\n@@ -1533,15 +1532,18 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t/* Clear link partner's EEE ability */\n \thw->dev_spec.ich8lan.eee_lp_ability = 0;\n \n-\t/* FEXTNVM6 K1-off workaround */\n-\tif (hw->mac.type == e1000_pch_spt) {\n-\t\tu32 pcieanacfg = er32(PCIEANACFG);\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\tu32 fextnvm6 = er32(FEXTNVM6);\n \n-\t\tif (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)\n-\t\t\tfextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;\n-\t\telse\n-\t\t\tfextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;\n+\t\tif (hw->mac.type == e1000_pch_spt) {\n+\t\t\t/* FEXTNVM6 K1-off workaround - for SPT only */\n+\t\t\tu32 pcieanacfg = er32(PCIEANACFG);\n+\n+\t\t\tif (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)\n+\t\t\t\tfextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;\n+\t\t\telse\n+\t\t\t\tfextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;\n+\t\t}\n \n \t\tew32(FEXTNVM6, fextnvm6);\n \t}\n@@ -1640,6 +1642,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)\n \tcase e1000_pch2lan:\n \tcase e1000_pch_lpt:\n \tcase e1000_pch_spt:\n+\tcase e1000_pch_cnp:\n \t\trc = e1000_init_phy_params_pchlan(hw);\n \t\tbreak;\n \tdefault:\n@@ -2091,6 +2094,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)\n \tcase e1000_pch2lan:\n \tcase e1000_pch_lpt:\n \tcase e1000_pch_spt:\n+\tcase e1000_pch_cnp:\n \t\tsw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;\n \t\tbreak;\n \tdefault:\n@@ -3125,6 +3129,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)\n \n \tswitch (hw->mac.type) {\n \tcase e1000_pch_spt:\n+\tcase e1000_pch_cnp:\n \t\tbank1_offset = nvm->flash_bank_size;\n \t\tact_offset = E1000_ICH_NVM_SIG_WORD;\n \n@@ -3380,7 +3385,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)\n \t/* Clear FCERR and DAEL in hw status by writing 1 */\n \thsfsts.hsf_status.flcerr = 1;\n \thsfsts.hsf_status.dael = 1;\n-\tif (hw->mac.type == e1000_pch_spt)\n+\tif (hw->mac.type >= e1000_pch_spt)\n \t\tew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);\n \telse\n \t\tew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);\n@@ -3399,7 +3404,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)\n \t\t * Begin by setting Flash Cycle Done.\n \t\t */\n \t\thsfsts.hsf_status.flcdone = 1;\n-\t\tif (hw->mac.type == e1000_pch_spt)\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n \t\t\tew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);\n \t\telse\n \t\t\tew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);\n@@ -3423,7 +3428,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)\n \t\t\t * now set the Flash Cycle Done.\n \t\t\t */\n \t\t\thsfsts.hsf_status.flcdone = 1;\n-\t\t\tif (hw->mac.type == e1000_pch_spt)\n+\t\t\tif (hw->mac.type >= e1000_pch_spt)\n \t\t\t\tew32flash(ICH_FLASH_HSFSTS,\n \t\t\t\t\t hsfsts.regval & 0xFFFF);\n \t\t\telse\n@@ -3450,13 +3455,13 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)\n \tu32 i = 0;\n \n \t/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */\n-\tif (hw->mac.type == e1000_pch_spt)\n+\tif (hw->mac.type >= e1000_pch_spt)\n \t\thsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;\n \telse\n \t\thsflctl.regval = er16flash(ICH_FLASH_HSFCTL);\n \thsflctl.hsf_ctrl.flcgo = 1;\n \n-\tif (hw->mac.type == e1000_pch_spt)\n+\tif (hw->mac.type >= e1000_pch_spt)\n \t\tew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);\n \telse\n \t\tew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);\n@@ -3527,7 +3532,7 @@ static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,\n \t/* In SPT, only 32 bits access is supported,\n \t * so this function should not be called.\n \t */\n-\tif (hw->mac.type == e1000_pch_spt)\n+\tif (hw->mac.type >= e1000_pch_spt)\n \t\treturn -E1000_ERR_NVM;\n \telse\n \t\tret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);\n@@ -3634,8 +3639,7 @@ static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,\n \ts32 ret_val = -E1000_ERR_NVM;\n \tu8 count = 0;\n \n-\tif (offset > ICH_FLASH_LINEAR_ADDR_MASK ||\n-\t hw->mac.type != e1000_pch_spt)\n+\tif (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)\n \t\treturn -E1000_ERR_NVM;\n \tflash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +\n \t\t\t hw->nvm.flash_base_addr);\n@@ -4068,6 +4072,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)\n \tswitch (hw->mac.type) {\n \tcase e1000_pch_lpt:\n \tcase e1000_pch_spt:\n+\tcase e1000_pch_cnp:\n \t\tword = NVM_COMPAT;\n \t\tvalid_csum_mask = NVM_COMPAT_VALID_CSUM;\n \t\tbreak;\n@@ -4153,7 +4158,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n \ts32 ret_val;\n \tu8 count = 0;\n \n-\tif (hw->mac.type == e1000_pch_spt) {\n+\tif (hw->mac.type >= e1000_pch_spt) {\n \t\tif (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)\n \t\t\treturn -E1000_ERR_NVM;\n \t} else {\n@@ -4173,7 +4178,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n \t\t/* In SPT, This register is in Lan memory space, not\n \t\t * flash. Therefore, only 32 bit access is supported\n \t\t */\n-\t\tif (hw->mac.type == e1000_pch_spt)\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n \t\t\thsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;\n \t\telse\n \t\t\thsflctl.regval = er16flash(ICH_FLASH_HSFCTL);\n@@ -4185,7 +4190,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n \t\t * not flash. Therefore, only 32 bit access is\n \t\t * supported\n \t\t */\n-\t\tif (hw->mac.type == e1000_pch_spt)\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n \t\t\tew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);\n \t\telse\n \t\t\tew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);\n@@ -4243,7 +4248,7 @@ static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,\n \ts32 ret_val;\n \tu8 count = 0;\n \n-\tif (hw->mac.type == e1000_pch_spt) {\n+\tif (hw->mac.type >= e1000_pch_spt) {\n \t\tif (offset > ICH_FLASH_LINEAR_ADDR_MASK)\n \t\t\treturn -E1000_ERR_NVM;\n \t}\n@@ -4259,7 +4264,7 @@ static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,\n \t\t/* In SPT, This register is in Lan memory space, not\n \t\t * flash. Therefore, only 32 bit access is supported\n \t\t */\n-\t\tif (hw->mac.type == e1000_pch_spt)\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n \t\t\thsflctl.regval = er32flash(ICH_FLASH_HSFSTS)\n \t\t\t >> 16;\n \t\telse\n@@ -4272,7 +4277,7 @@ static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,\n \t\t * not flash. Therefore, only 32 bit access is\n \t\t * supported\n \t\t */\n-\t\tif (hw->mac.type == e1000_pch_spt)\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n \t\t\tew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);\n \t\telse\n \t\t\tew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);\n@@ -4464,14 +4469,14 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)\n \t\t\t/* Write a value 11 (block Erase) in Flash\n \t\t\t * Cycle field in hw flash control\n \t\t\t */\n-\t\t\tif (hw->mac.type == e1000_pch_spt)\n+\t\t\tif (hw->mac.type >= e1000_pch_spt)\n \t\t\t\thsflctl.regval =\n \t\t\t\t er32flash(ICH_FLASH_HSFSTS) >> 16;\n \t\t\telse\n \t\t\t\thsflctl.regval = er16flash(ICH_FLASH_HSFCTL);\n \n \t\t\thsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;\n-\t\t\tif (hw->mac.type == e1000_pch_spt)\n+\t\t\tif (hw->mac.type >= e1000_pch_spt)\n \t\t\t\tew32flash(ICH_FLASH_HSFSTS,\n \t\t\t\t\t hsflctl.regval << 16);\n \t\t\telse\n@@ -4894,8 +4899,7 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)\n \tew32(RFCTL, reg);\n \n \t/* Enable ECC on Lynxpoint */\n-\tif ((hw->mac.type == e1000_pch_lpt) ||\n-\t (hw->mac.type == e1000_pch_spt)) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\treg = er32(PBECCSTS);\n \t\treg |= E1000_PBECCSTS_ECC_ENABLE;\n \t\tew32(PBECCSTS, reg);\n@@ -5299,7 +5303,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)\n \t\t (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||\n \t\t (device_id == E1000_DEV_ID_PCH_I218_LM3) ||\n \t\t (device_id == E1000_DEV_ID_PCH_I218_V3) ||\n-\t\t (hw->mac.type == e1000_pch_spt)) {\n+\t\t (hw->mac.type >= e1000_pch_spt)) {\n \t\t\tu32 fextnvm6 = er32(FEXTNVM6);\n \n \t\t\tew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);\ndiff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c\nindex 4bda1cb97b27..dc83ac92cb67 100644\n--- a/drivers/net/ethernet/intel/e1000e/netdev.c\n+++ b/drivers/net/ethernet/intel/e1000e/netdev.c\n@@ -1792,8 +1792,7 @@ static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)\n \t}\n \n \t/* Reset on uncorrectable ECC error */\n-\tif ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||\n-\t\t\t\t\t(hw->mac.type == e1000_pch_spt))) {\n+\tif ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {\n \t\tu32 pbeccsts = er32(PBECCSTS);\n \n \t\tadapter->corr_errors +=\n@@ -1873,8 +1872,7 @@ static irqreturn_t e1000_intr(int __always_unused irq, void *data)\n \t}\n \n \t/* Reset on uncorrectable ECC error */\n-\tif ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||\n-\t\t\t\t\t(hw->mac.type == e1000_pch_spt))) {\n+\tif ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {\n \t\tu32 pbeccsts = er32(PBECCSTS);\n \n \t\tadapter->corr_errors +=\n@@ -2242,8 +2240,7 @@ static void e1000_irq_enable(struct e1000_adapter *adapter)\n \tif (adapter->msix_entries) {\n \t\tew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);\n \t\tew32(IMS, adapter->eiac_mask | E1000_IMS_LSC);\n-\t} else if ((hw->mac.type == e1000_pch_lpt) ||\n-\t\t (hw->mac.type == e1000_pch_spt)) {\n+\t} else if (hw->mac.type >= e1000_pch_lpt) {\n \t\tew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);\n \t} else {\n \t\tew32(IMS, IMS_ENABLE_MASK);\n@@ -3001,8 +2998,8 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)\n \n \thw->mac.ops.config_collision_dist(hw);\n \n-\t/* SPT Si errata workaround to avoid data corruption */\n-\tif (hw->mac.type == e1000_pch_spt) {\n+\t/* SPT and CNP Si errata workaround to avoid data corruption */\n+\tif (hw->mac.type >= e1000_pch_spt) {\n \t\tu32 reg_val;\n \n \t\treg_val = er32(IOSFPC);\n@@ -3498,8 +3495,7 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)\n \t/* Make sure clock is enabled on I217/I218/I219 before checking\n \t * the frequency\n \t */\n-\tif (((hw->mac.type == e1000_pch_lpt) ||\n-\t (hw->mac.type == e1000_pch_spt)) &&\n+\tif ((hw->mac.type >= e1000_pch_lpt) &&\n \t !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&\n \t !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {\n \t\tu32 fextnvm7 = er32(FEXTNVM7);\n@@ -4033,6 +4029,7 @@ void e1000e_reset(struct e1000_adapter *adapter)\n \tcase e1000_pch2lan:\n \tcase e1000_pch_lpt:\n \tcase e1000_pch_spt:\n+\tcase e1000_pch_cnp:\n \t\tfc->refresh_time = 0x0400;\n \n \t\tif (adapter->netdev->mtu <= ETH_DATA_LEN) {\n@@ -4077,7 +4074,7 @@ void e1000e_reset(struct e1000_adapter *adapter)\n \t\t}\n \t}\n \n-\tif (hw->mac.type == e1000_pch_spt)\n+\tif (hw->mac.type >= e1000_pch_spt)\n \t\te1000_flush_desc_rings(adapter);\n \t/* Allow time for pending master requests to run */\n \tmac->ops.reset_hw(hw);\n@@ -4152,7 +4149,7 @@ void e1000e_reset(struct e1000_adapter *adapter)\n \t\tphy_data &= ~IGP02E1000_PM_SPD;\n \t\te1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);\n \t}\n-\tif (hw->mac.type == e1000_pch_spt && adapter->int_mode == 0) {\n+\tif (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {\n \t\tu32 reg;\n \n \t\t/* Fextnvm7 @ 0xe4[2] = 1 */\n@@ -4286,7 +4283,7 @@ void e1000e_down(struct e1000_adapter *adapter, bool reset)\n \tif (!pci_channel_offline(adapter->pdev)) {\n \t\tif (reset)\n \t\t\te1000e_reset(adapter);\n-\t\telse if (hw->mac.type == e1000_pch_spt)\n+\t\telse if (hw->mac.type >= e1000_pch_spt)\n \t\t\te1000_flush_desc_rings(adapter);\n \t}\n \te1000_clean_tx_ring(adapter->tx_ring);\n@@ -4974,8 +4971,7 @@ static void e1000e_update_stats(struct e1000_adapter *adapter)\n \tadapter->stats.mgpdc += er32(MGTPDC);\n \n \t/* Correctable ECC Errors */\n-\tif ((hw->mac.type == e1000_pch_lpt) ||\n-\t (hw->mac.type == e1000_pch_spt)) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\tu32 pbeccsts = er32(PBECCSTS);\n \n \t\tadapter->corr_errors +=\n@@ -6349,8 +6345,7 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)\n \n \tif (adapter->hw.phy.type == e1000_phy_igp_3) {\n \t\te1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);\n-\t} else if ((hw->mac.type == e1000_pch_lpt) ||\n-\t\t (hw->mac.type == e1000_pch_spt)) {\n+\t} else if (hw->mac.type >= e1000_pch_lpt) {\n \t\tif (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))\n \t\t\t/* ULP does not support wake from unicast, multicast\n \t\t\t * or broadcast.\ndiff --git a/drivers/net/ethernet/intel/e1000e/ptp.c b/drivers/net/ethernet/intel/e1000e/ptp.c\nindex 34cc3be0df8e..b366885487a8 100644\n--- a/drivers/net/ethernet/intel/e1000e/ptp.c\n+++ b/drivers/net/ethernet/intel/e1000e/ptp.c\n@@ -301,8 +301,8 @@ void e1000e_ptp_init(struct e1000_adapter *adapter)\n \tcase e1000_pch2lan:\n \tcase e1000_pch_lpt:\n \tcase e1000_pch_spt:\n-\t\tif (((hw->mac.type != e1000_pch_lpt) &&\n-\t\t (hw->mac.type != e1000_pch_spt)) ||\n+\tcase e1000_pch_cnp:\n+\t\tif ((hw->mac.type < e1000_pch_lpt) ||\n \t\t (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {\n \t\t\tadapter->ptp_clock_info.max_adj = 24000000 - 1;\n \t\t\tbreak;\n", "prefixes": [ "2/3" ] }