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GET /api/patches/744345/?format=api
{ "id": 744345, "url": "http://patchwork.ozlabs.org/api/patches/744345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1490714052-18902-5-git-send-email-clombard@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1490714052-18902-5-git-send-email-clombard@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1490714052-18902-5-git-send-email-clombard@linux.vnet.ibm.com/", "date": "2017-03-28T15:14:09", "name": "[V3,4/7] cxl: Update implementation service layer", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "90b74b0457c6196659e55f16f2051ed5dd3730a8", "submitter": { "id": 67351, "url": "http://patchwork.ozlabs.org/api/people/67351/?format=api", "name": "Christophe Lombard", "email": "clombard@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1490714052-18902-5-git-send-email-clombard@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/744345/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/744345/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vsvm16MnPz9s2P\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 29 Mar 2017 02:22:57 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3vsvm15cTtzDqpd\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 29 Mar 2017 02:22:57 +1100 (AEDT)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3vsvbX4HbbzDqY7\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 29 Mar 2017 02:15:00 +1100 (AEDT)", "from pps.filterd (m0098416.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id\n\tv2SFE3m6046056\n\tfor <linuxppc-dev@lists.ozlabs.org>; Tue, 28 Mar 2017 11:14:49 -0400", "from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 29ft6f8f7s-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Tue, 28 Mar 2017 11:14:49 -0400", "from localhost\n\tby e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from\n\t<clombard@linux.vnet.ibm.com>; Tue, 28 Mar 2017 16:14:47 +0100", "from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194)\n\tby e06smtp12.uk.ibm.com (192.168.101.142) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tTue, 28 Mar 2017 16:14:46 +0100", "from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com\n\t[9.149.105.232])\n\tby b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v2SFEKFr15532358; Tue, 28 Mar 2017 15:14:20 GMT", "from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 5DB1452057;\n\tTue, 28 Mar 2017 15:12:35 +0100 (BST)", "from lombard-w520.ibm.com (unknown [9.167.235.7])\n\tby d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id C1E2A5204B; \n\tTue, 28 Mar 2017 15:12:34 +0100 (BST)" ], "From": "Christophe Lombard <clombard@linux.vnet.ibm.com>", "To": "linuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,\n\timunsie@au1.ibm.com, andrew.donnellan@au1.ibm.com", "Subject": "[PATCH V3 4/7] cxl: Update implementation service layer", "Date": "Tue, 28 Mar 2017 17:14:09 +0200", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1490714052-18902-1-git-send-email-clombard@linux.vnet.ibm.com>", "References": "<1490714052-18902-1-git-send-email-clombard@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17032815-0008-0000-0000-000004121437", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17032815-0009-0000-0000-00001D0422E3", "Message-Id": "<1490714052-18902-5-git-send-email-clombard@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-03-28_12:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=2\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001\n\tdefinitions=main-1703280131", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The service layer API (in cxl.h) lists some low-level functions whose\nimplementation is different on PSL8, PSL9 and XSL:\n- Init implementation for the adapter and the afu.\n- Invalidate TLB/SLB.\n- Attach process for dedicated/directed models.\n- Handle psl interrupts.\n- Debug registers for the adapter and the afu.\n- Traces.\nEach environment implements its own functions, and the common code uses\nthem through function pointers, defined in cxl_service_layer_ops.\n\nSigned-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>\n---\n drivers/misc/cxl/cxl.h | 40 ++++++++++++++++++++++++-----------\n drivers/misc/cxl/debugfs.c | 16 +++++++-------\n drivers/misc/cxl/guest.c | 2 +-\n drivers/misc/cxl/irq.c | 2 +-\n drivers/misc/cxl/native.c | 52 ++++++++++++++++++++++++++++------------------\n drivers/misc/cxl/pci.c | 47 ++++++++++++++++++++++++++++-------------\n 6 files changed, 102 insertions(+), 57 deletions(-)", "diff": "diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h\nindex d8282e4..65d9fb6 100644\n--- a/drivers/misc/cxl/cxl.h\n+++ b/drivers/misc/cxl/cxl.h\n@@ -553,13 +553,23 @@ struct cxl_context {\n \tstruct mm_struct *mm;\n };\n \n+struct cxl_irq_info;\n+\n struct cxl_service_layer_ops {\n \tint (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);\n+\tint (*invalidate_all)(struct cxl *adapter);\n \tint (*afu_regs_init)(struct cxl_afu *afu);\n+\tint (*sanitise_afu_regs)(struct cxl_afu *afu);\n \tint (*register_serr_irq)(struct cxl_afu *afu);\n \tvoid (*release_serr_irq)(struct cxl_afu *afu);\n-\tvoid (*debugfs_add_adapter_sl_regs)(struct cxl *adapter, struct dentry *dir);\n-\tvoid (*debugfs_add_afu_sl_regs)(struct cxl_afu *afu, struct dentry *dir);\n+\tirqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);\n+\tirqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);\n+\tint (*activate_dedicated_process)(struct cxl_afu *afu);\n+\tint (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);\n+\tint (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);\n+\tvoid (*update_dedicated_ivtes)(struct cxl_context *ctx);\n+\tvoid (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);\n+\tvoid (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);\n \tvoid (*psl_irq_dump_registers)(struct cxl_context *ctx);\n \tvoid (*err_irq_dump_registers)(struct cxl *adapter);\n \tvoid (*debugfs_stop_trace)(struct cxl *adapter);\n@@ -803,6 +813,11 @@ int afu_register_irqs(struct cxl_context *ctx, u32 count);\n void afu_release_irqs(struct cxl_context *ctx, void *cookie);\n void afu_irq_name_free(struct cxl_context *ctx);\n \n+int cxl_attach_afu_directed_psl(struct cxl_context *ctx, u64 wed, u64 amr);\n+int cxl_activate_dedicated_process_psl(struct cxl_afu *afu);\n+int cxl_attach_dedicated_process_psl(struct cxl_context *ctx, u64 wed, u64 amr);\n+void cxl_update_dedicated_ivtes_psl(struct cxl_context *ctx);\n+\n #ifdef CONFIG_DEBUG_FS\n \n int cxl_debugfs_init(void);\n@@ -811,10 +826,10 @@ int cxl_debugfs_adapter_add(struct cxl *adapter);\n void cxl_debugfs_adapter_remove(struct cxl *adapter);\n int cxl_debugfs_afu_add(struct cxl_afu *afu);\n void cxl_debugfs_afu_remove(struct cxl_afu *afu);\n-void cxl_stop_trace(struct cxl *cxl);\n-void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter, struct dentry *dir);\n-void cxl_debugfs_add_adapter_xsl_regs(struct cxl *adapter, struct dentry *dir);\n-void cxl_debugfs_add_afu_psl_regs(struct cxl_afu *afu, struct dentry *dir);\n+void cxl_stop_trace_psl(struct cxl *cxl);\n+void cxl_debugfs_add_adapter_regs_psl(struct cxl *adapter, struct dentry *dir);\n+void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter, struct dentry *dir);\n+void cxl_debugfs_add_afu_regs_psl(struct cxl_afu *afu, struct dentry *dir);\n \n #else /* CONFIG_DEBUG_FS */\n \n@@ -849,17 +864,17 @@ static inline void cxl_stop_trace(struct cxl *cxl)\n {\n }\n \n-static inline void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter,\n+static inline void cxl_debugfs_add_adapter_regs_psl(struct cxl *adapter,\n \t\t\t\t\t\t struct dentry *dir)\n {\n }\n \n-static inline void cxl_debugfs_add_adapter_xsl_regs(struct cxl *adapter,\n+static inline void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter,\n \t\t\t\t\t\t struct dentry *dir)\n {\n }\n \n-static inline void cxl_debugfs_add_afu_psl_regs(struct cxl_afu *afu, struct dentry *dir)\n+static inline void cxl_debugfs_add_afu_regs_psl(struct cxl_afu *afu, struct dentry *dir)\n {\n }\n \n@@ -917,19 +932,20 @@ struct cxl_irq_info {\n };\n \n void cxl_assign_psn_space(struct cxl_context *ctx);\n-irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);\n+int cxl_invalidate_all_psl(struct cxl *adapter);\n+irqreturn_t cxl_irq_psl(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);\n+irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);\n int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,\n \t\t\tvoid *cookie, irq_hw_number_t *dest_hwirq,\n \t\t\tunsigned int *dest_virq, const char *name);\n \n int cxl_check_error(struct cxl_afu *afu);\n int cxl_afu_slbia(struct cxl_afu *afu);\n-int cxl_tlb_slb_invalidate(struct cxl *adapter);\n int cxl_data_cache_flush(struct cxl *adapter);\n int cxl_afu_disable(struct cxl_afu *afu);\n int cxl_psl_purge(struct cxl_afu *afu);\n \n-void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx);\n+void cxl_native_irq_dump_regs_psl(struct cxl_context *ctx);\n void cxl_native_err_irq_dump_regs(struct cxl *adapter);\n int cxl_pci_vphb_add(struct cxl_afu *afu);\n void cxl_pci_vphb_remove(struct cxl_afu *afu);\ndiff --git a/drivers/misc/cxl/debugfs.c b/drivers/misc/cxl/debugfs.c\nindex 9c06ac8..4848ebf 100644\n--- a/drivers/misc/cxl/debugfs.c\n+++ b/drivers/misc/cxl/debugfs.c\n@@ -15,7 +15,7 @@\n \n static struct dentry *cxl_debugfs;\n \n-void cxl_stop_trace(struct cxl *adapter)\n+void cxl_stop_trace_psl(struct cxl *adapter)\n {\n \tint slice;\n \n@@ -53,7 +53,7 @@ static struct dentry *debugfs_create_io_x64(const char *name, umode_t mode,\n \t\t\t\t\t (void __force *)value, &fops_io_x64);\n }\n \n-void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter, struct dentry *dir)\n+void cxl_debugfs_add_adapter_regs_psl(struct cxl *adapter, struct dentry *dir)\n {\n \tdebugfs_create_io_x64(\"fir1\", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL_FIR1));\n \tdebugfs_create_io_x64(\"fir2\", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL_FIR2));\n@@ -61,7 +61,7 @@ void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter, struct dentry *dir)\n \tdebugfs_create_io_x64(\"trace\", S_IRUSR | S_IWUSR, dir, _cxl_p1_addr(adapter, CXL_PSL_TRACE));\n }\n \n-void cxl_debugfs_add_adapter_xsl_regs(struct cxl *adapter, struct dentry *dir)\n+void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter, struct dentry *dir)\n {\n \tdebugfs_create_io_x64(\"fec\", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_XSL_FEC));\n }\n@@ -82,8 +82,8 @@ int cxl_debugfs_adapter_add(struct cxl *adapter)\n \n \tdebugfs_create_io_x64(\"err_ivte\", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL_ErrIVTE));\n \n-\tif (adapter->native->sl_ops->debugfs_add_adapter_sl_regs)\n-\t\tadapter->native->sl_ops->debugfs_add_adapter_sl_regs(adapter, dir);\n+\tif (adapter->native->sl_ops->debugfs_add_adapter_regs)\n+\t\tadapter->native->sl_ops->debugfs_add_adapter_regs(adapter, dir);\n \treturn 0;\n }\n \n@@ -92,7 +92,7 @@ void cxl_debugfs_adapter_remove(struct cxl *adapter)\n \tdebugfs_remove_recursive(adapter->debugfs);\n }\n \n-void cxl_debugfs_add_afu_psl_regs(struct cxl_afu *afu, struct dentry *dir)\n+void cxl_debugfs_add_afu_regs_psl(struct cxl_afu *afu, struct dentry *dir)\n {\n \tdebugfs_create_io_x64(\"fir\", S_IRUSR, dir, _cxl_p1n_addr(afu, CXL_PSL_FIR_SLICE_An));\n \tdebugfs_create_io_x64(\"serr\", S_IRUSR, dir, _cxl_p1n_addr(afu, CXL_PSL_SERR_An));\n@@ -121,8 +121,8 @@ int cxl_debugfs_afu_add(struct cxl_afu *afu)\n \tdebugfs_create_io_x64(\"sstp1\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_SSTP1_An));\n \tdebugfs_create_io_x64(\"err_status\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_PSL_ErrStat_An));\n \n-\tif (afu->adapter->native->sl_ops->debugfs_add_afu_sl_regs)\n-\t\tafu->adapter->native->sl_ops->debugfs_add_afu_sl_regs(afu, dir);\n+\tif (afu->adapter->native->sl_ops->debugfs_add_afu_regs)\n+\t\tafu->adapter->native->sl_ops->debugfs_add_afu_regs(afu, dir);\n \n \treturn 0;\n }\ndiff --git a/drivers/misc/cxl/guest.c b/drivers/misc/cxl/guest.c\nindex e04bc4d..f6ba698 100644\n--- a/drivers/misc/cxl/guest.c\n+++ b/drivers/misc/cxl/guest.c\n@@ -169,7 +169,7 @@ static irqreturn_t guest_psl_irq(int irq, void *data)\n \t\treturn IRQ_HANDLED;\n \t}\n \n-\trc = cxl_irq(irq, ctx, &irq_info);\n+\trc = cxl_irq_psl(irq, ctx, &irq_info);\n \treturn rc;\n }\n \ndiff --git a/drivers/misc/cxl/irq.c b/drivers/misc/cxl/irq.c\nindex 1a402bb..2fa119e 100644\n--- a/drivers/misc/cxl/irq.c\n+++ b/drivers/misc/cxl/irq.c\n@@ -34,7 +34,7 @@ static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 da\n \treturn IRQ_HANDLED;\n }\n \n-irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info)\n+irqreturn_t cxl_irq_psl(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info)\n {\n \tu64 dsisr, dar;\n \ndiff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c\nindex 7257e8b..c5048e8 100644\n--- a/drivers/misc/cxl/native.c\n+++ b/drivers/misc/cxl/native.c\n@@ -258,7 +258,7 @@ void cxl_release_spa(struct cxl_afu *afu)\n \t}\n }\n \n-int cxl_tlb_slb_invalidate(struct cxl *adapter)\n+int cxl_invalidate_all_psl(struct cxl *adapter)\n {\n \tunsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);\n \n@@ -578,7 +578,7 @@ static void update_ivtes_directed(struct cxl_context *ctx)\n \t\tWARN_ON(add_process_element(ctx));\n }\n \n-static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)\n+int cxl_attach_afu_directed_psl(struct cxl_context *ctx, u64 wed, u64 amr)\n {\n \tu32 pid;\n \tint result;\n@@ -671,7 +671,7 @@ static int deactivate_afu_directed(struct cxl_afu *afu)\n \treturn 0;\n }\n \n-static int activate_dedicated_process(struct cxl_afu *afu)\n+int cxl_activate_dedicated_process_psl(struct cxl_afu *afu)\n {\n \tdev_info(&afu->dev, \"Activating dedicated process mode\\n\");\n \n@@ -694,7 +694,7 @@ static int activate_dedicated_process(struct cxl_afu *afu)\n \treturn cxl_chardev_d_afu_add(afu);\n }\n \n-static void update_ivtes_dedicated(struct cxl_context *ctx)\n+void cxl_update_dedicated_ivtes_psl(struct cxl_context *ctx)\n {\n \tstruct cxl_afu *afu = ctx->afu;\n \n@@ -710,7 +710,7 @@ static void update_ivtes_dedicated(struct cxl_context *ctx)\n \t\t\t((u64)ctx->irqs.range[3] & 0xffff));\n }\n \n-static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)\n+int cxl_attach_dedicated_process_psl(struct cxl_context *ctx, u64 wed, u64 amr)\n {\n \tstruct cxl_afu *afu = ctx->afu;\n \tu64 pid;\n@@ -728,7 +728,8 @@ static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)\n \n \tcxl_prefault(ctx, wed);\n \n-\tupdate_ivtes_dedicated(ctx);\n+\tif (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)\n+\t\tafu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);\n \n \tcxl_p2n_write(afu, CXL_PSL_AMR_An, amr);\n \n@@ -778,8 +779,9 @@ static int native_afu_activate_mode(struct cxl_afu *afu, int mode)\n \n \tif (mode == CXL_MODE_DIRECTED)\n \t\treturn activate_afu_directed(afu);\n-\tif (mode == CXL_MODE_DEDICATED)\n-\t\treturn activate_dedicated_process(afu);\n+\tif ((mode == CXL_MODE_DEDICATED) &&\n+\t (afu->adapter->native->sl_ops->activate_dedicated_process))\n+\t\treturn afu->adapter->native->sl_ops->activate_dedicated_process(afu);\n \n \treturn -EINVAL;\n }\n@@ -793,11 +795,13 @@ static int native_attach_process(struct cxl_context *ctx, bool kernel,\n \t}\n \n \tctx->kernel = kernel;\n-\tif (ctx->afu->current_mode == CXL_MODE_DIRECTED)\n-\t\treturn attach_afu_directed(ctx, wed, amr);\n+\tif ((ctx->afu->current_mode == CXL_MODE_DIRECTED) &&\n+\t (ctx->afu->adapter->native->sl_ops->attach_afu_directed))\n+\t\treturn ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr);\n \n-\tif (ctx->afu->current_mode == CXL_MODE_DEDICATED)\n-\t\treturn attach_dedicated(ctx, wed, amr);\n+\tif ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&\n+\t (ctx->afu->adapter->native->sl_ops->attach_dedicated_process))\n+\t\treturn ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr);\n \n \treturn -EINVAL;\n }\n@@ -830,8 +834,9 @@ static void native_update_ivtes(struct cxl_context *ctx)\n {\n \tif (ctx->afu->current_mode == CXL_MODE_DIRECTED)\n \t\treturn update_ivtes_directed(ctx);\n-\tif (ctx->afu->current_mode == CXL_MODE_DEDICATED)\n-\t\treturn update_ivtes_dedicated(ctx);\n+\tif ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&\n+\t (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes))\n+\t\treturn ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);\n \tWARN(1, \"native_update_ivtes: Bad mode\\n\");\n }\n \n@@ -875,7 +880,7 @@ static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)\n \treturn 0;\n }\n \n-void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx)\n+void cxl_native_irq_dump_regs_psl(struct cxl_context *ctx)\n {\n \tu64 fir1, fir2, fir_slice, serr, afu_debug;\n \n@@ -911,7 +916,7 @@ static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,\n \treturn cxl_ops->ack_irq(ctx, 0, errstat);\n }\n \n-static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info)\n+irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info)\n {\n \tif (irq_info->dsisr & CXL_PSL_DSISR_TRANS)\n \t\tcxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);\n@@ -927,7 +932,7 @@ static irqreturn_t native_irq_multiplexed(int irq, void *data)\n \tstruct cxl_context *ctx;\n \tstruct cxl_irq_info irq_info;\n \tu64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An);\n-\tint ph, ret;\n+\tint ph, ret = IRQ_HANDLED;\n \n \t/* check if eeh kicked in while the interrupt was in flight */\n \tif (unlikely(phreg == ~0ULL)) {\n@@ -940,13 +945,17 @@ static irqreturn_t native_irq_multiplexed(int irq, void *data)\n \tph = phreg & 0xffff;\n \tif ((ret = native_get_irq_info(afu, &irq_info))) {\n \t\tWARN(1, \"Unable to get CXL IRQ Info: %i\\n\", ret);\n-\t\treturn fail_psl_irq(afu, &irq_info);\n+\t\tif (afu->adapter->native->sl_ops->fail_irq)\n+\t\t\treturn afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);\n+\t\treturn IRQ_HANDLED;\n \t}\n \n \trcu_read_lock();\n \tctx = idr_find(&afu->contexts_idr, ph);\n \tif (ctx) {\n-\t\tret = cxl_irq(irq, ctx, &irq_info);\n+\t\tret = IRQ_HANDLED;\n+\t\tif (afu->adapter->native->sl_ops->handle_interrupt)\n+\t\t\tret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info);\n \t\trcu_read_unlock();\n \t\treturn ret;\n \t}\n@@ -956,7 +965,10 @@ static irqreturn_t native_irq_multiplexed(int irq, void *data)\n \t\t\" %016llx\\n(Possible AFU HW issue - was a term/remove acked\"\n \t\t\" with outstanding transactions?)\\n\", ph, irq_info.dsisr,\n \t\tirq_info.dar);\n-\treturn fail_psl_irq(afu, &irq_info);\n+\tret = IRQ_HANDLED;\n+\tif (afu->adapter->native->sl_ops->fail_irq)\n+\t\tret = afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);\n+\treturn ret;\n }\n \n static void native_irq_wait(struct cxl_context *ctx)\ndiff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c\nindex e82a207..4d475a5 100644\n--- a/drivers/misc/cxl/pci.c\n+++ b/drivers/misc/cxl/pci.c\n@@ -377,7 +377,7 @@ static int calc_capp_routing(struct pci_dev *dev, u64 *chipid, u64 *capp_unit_id\n \treturn 0;\n }\n \n-static int init_implementation_adapter_psl_regs(struct cxl *adapter, struct pci_dev *dev)\n+static int init_implementation_adapter_regs_psl(struct cxl *adapter, struct pci_dev *dev)\n {\n \tu64 psl_dsnctl, psl_fircntl;\n \tu64 chipid;\n@@ -409,7 +409,7 @@ static int init_implementation_adapter_psl_regs(struct cxl *adapter, struct pci_\n \treturn 0;\n }\n \n-static int init_implementation_adapter_xsl_regs(struct cxl *adapter, struct pci_dev *dev)\n+static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev)\n {\n \tu64 xsl_dsnctl;\n \tu64 chipid;\n@@ -513,7 +513,7 @@ static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)\n \treturn;\n }\n \n-static int init_implementation_afu_psl_regs(struct cxl_afu *afu)\n+static int init_implementation_afu_regs_psl(struct cxl_afu *afu)\n {\n \t/* read/write masks for this slice */\n \tcxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);\n@@ -996,7 +996,7 @@ static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)\n \treturn 0;\n }\n \n-static int sanitise_afu_regs(struct cxl_afu *afu)\n+static int sanitise_afu_regs_psl(struct cxl_afu *afu)\n {\n \tu64 reg;\n \n@@ -1102,8 +1102,11 @@ static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pc\n \tif ((rc = pci_map_slice_regs(afu, adapter, dev)))\n \t\treturn rc;\n \n-\tif ((rc = sanitise_afu_regs(afu)))\n-\t\tgoto err1;\n+\tif (adapter->native->sl_ops->sanitise_afu_regs) {\n+\t\trc = adapter->native->sl_ops->sanitise_afu_regs(afu);\n+\t\tif (rc)\n+\t\t\tgoto err1;\n+\t}\n \n \t/* We need to reset the AFU before we can read the AFU descriptor */\n \tif ((rc = cxl_ops->afu_reset(afu)))\n@@ -1432,9 +1435,15 @@ static void cxl_release_adapter(struct device *dev)\n \n static int sanitise_adapter_regs(struct cxl *adapter)\n {\n+\tint rc = 0;\n+\n \t/* Clear PSL tberror bit by writing 1 to it */\n \tcxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);\n-\treturn cxl_tlb_slb_invalidate(adapter);\n+\n+\tif (adapter->native->sl_ops->invalidate_all)\n+\t\trc = adapter->native->sl_ops->invalidate_all(adapter);\n+\n+\treturn rc;\n }\n \n /* This should contain *only* operations that can safely be done in\n@@ -1518,15 +1527,23 @@ static void cxl_deconfigure_adapter(struct cxl *adapter)\n }\n \n static const struct cxl_service_layer_ops psl_ops = {\n-\t.adapter_regs_init = init_implementation_adapter_psl_regs,\n-\t.afu_regs_init = init_implementation_afu_psl_regs,\n+\t.adapter_regs_init = init_implementation_adapter_regs_psl,\n+\t.invalidate_all = cxl_invalidate_all_psl,\n+\t.afu_regs_init = init_implementation_afu_regs_psl,\n+\t.sanitise_afu_regs = sanitise_afu_regs_psl,\n \t.register_serr_irq = cxl_native_register_serr_irq,\n \t.release_serr_irq = cxl_native_release_serr_irq,\n-\t.debugfs_add_adapter_sl_regs = cxl_debugfs_add_adapter_psl_regs,\n-\t.debugfs_add_afu_sl_regs = cxl_debugfs_add_afu_psl_regs,\n-\t.psl_irq_dump_registers = cxl_native_psl_irq_dump_regs,\n+\t.handle_interrupt = cxl_irq_psl,\n+\t.fail_irq = cxl_fail_irq_psl,\n+\t.activate_dedicated_process = cxl_activate_dedicated_process_psl,\n+\t.attach_afu_directed = cxl_attach_afu_directed_psl,\n+\t.attach_dedicated_process = cxl_attach_dedicated_process_psl,\n+\t.update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl,\n+\t.debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl,\n+\t.debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl,\n+\t.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl,\n \t.err_irq_dump_registers = cxl_native_err_irq_dump_regs,\n-\t.debugfs_stop_trace = cxl_stop_trace,\n+\t.debugfs_stop_trace = cxl_stop_trace_psl,\n \t.write_timebase_ctrl = write_timebase_ctrl_psl,\n \t.timebase_read = timebase_read_psl,\n \t.capi_mode = OPAL_PHB_CAPI_MODE_CAPI,\n@@ -1534,8 +1551,8 @@ static const struct cxl_service_layer_ops psl_ops = {\n };\n \n static const struct cxl_service_layer_ops xsl_ops = {\n-\t.adapter_regs_init = init_implementation_adapter_xsl_regs,\n-\t.debugfs_add_adapter_sl_regs = cxl_debugfs_add_adapter_xsl_regs,\n+\t.adapter_regs_init = init_implementation_adapter_regs_xsl,\n+\t.debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,\n \t.write_timebase_ctrl = write_timebase_ctrl_xsl,\n \t.timebase_read = timebase_read_xsl,\n \t.capi_mode = OPAL_PHB_CAPI_MODE_DMA,\n", "prefixes": [ "V3", "4/7" ] }