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GET /api/patches/744335/?format=api
{ "id": 744335, "url": "http://patchwork.ozlabs.org/api/patches/744335/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1490714052-18902-7-git-send-email-clombard@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1490714052-18902-7-git-send-email-clombard@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1490714052-18902-7-git-send-email-clombard@linux.vnet.ibm.com/", "date": "2017-03-28T15:14:11", "name": "[V3,6/7] cxl: Isolate few psl8 specific calls", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "4c33ab24d66a020026e5f6938c362b505412b6f4", "submitter": { "id": 67351, "url": "http://patchwork.ozlabs.org/api/people/67351/?format=api", "name": "Christophe Lombard", "email": "clombard@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1490714052-18902-7-git-send-email-clombard@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/744335/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/744335/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vsvd13pm5z9s2Q\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 29 Mar 2017 02:16:53 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3vsvd12pVszDqbc\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 29 Mar 2017 02:16:53 +1100 (AEDT)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3vsvbX4PBLzDqZJ\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 29 Mar 2017 02:15:09 +1100 (AEDT)", "from pps.filterd (m0098409.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id\n\tv2SFE4tV007175\n\tfor <linuxppc-dev@lists.ozlabs.org>; Tue, 28 Mar 2017 11:14:57 -0400", "from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 29fsf74bnp-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Tue, 28 Mar 2017 11:14:57 -0400", "from localhost\n\tby e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from\n\t<clombard@linux.vnet.ibm.com>; Tue, 28 Mar 2017 16:14:51 +0100", "from b06cxnps4075.portsmouth.uk.ibm.com (9.149.109.197)\n\tby e06smtp14.uk.ibm.com (192.168.101.144) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tTue, 28 Mar 2017 16:14:50 +0100", "from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com\n\t[9.149.105.232])\n\tby b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v2SFEOto28573726; Tue, 28 Mar 2017 15:14:24 GMT", "from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id CB7B85203F;\n\tTue, 28 Mar 2017 15:12:38 +0100 (BST)", "from lombard-w520.ibm.com (unknown [9.167.235.7])\n\tby d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 3C82C5204D; \n\tTue, 28 Mar 2017 15:12:38 +0100 (BST)" ], "From": "Christophe Lombard <clombard@linux.vnet.ibm.com>", "To": "linuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,\n\timunsie@au1.ibm.com, andrew.donnellan@au1.ibm.com", "Subject": "[PATCH V3 6/7] cxl: Isolate few psl8 specific calls", "Date": "Tue, 28 Mar 2017 17:14:11 +0200", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1490714052-18902-1-git-send-email-clombard@linux.vnet.ibm.com>", "References": "<1490714052-18902-1-git-send-email-clombard@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17032815-0016-0000-0000-000004681374", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17032815-0017-0000-0000-00002700648F", "Message-Id": "<1490714052-18902-7-git-send-email-clombard@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-03-28_12:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=2\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001\n\tdefinitions=main-1703280131", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Point out the specific Coherent Accelerator Interface Architecture,\nlevel 1, registers.\nCode and functions specific to PSL8 (CAIA1) must be framed.\n\nSigned-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>\n---\n drivers/misc/cxl/context.c | 28 +++++++++++---------\n drivers/misc/cxl/cxl.h | 35 +++++++++++++++++++------\n drivers/misc/cxl/debugfs.c | 6 +++--\n drivers/misc/cxl/fault.c | 14 +++++-----\n drivers/misc/cxl/native.c | 58 ++++++++++++++++++++++++++---------------\n drivers/misc/cxl/pci.c | 64 +++++++++++++++++++++++++++++++---------------\n 6 files changed, 136 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c\nindex 2e935ea..ac2531e 100644\n--- a/drivers/misc/cxl/context.c\n+++ b/drivers/misc/cxl/context.c\n@@ -39,23 +39,26 @@ int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master)\n {\n \tint i;\n \n-\tspin_lock_init(&ctx->sste_lock);\n \tctx->afu = afu;\n \tctx->master = master;\n \tctx->pid = NULL; /* Set in start work ioctl */\n \tmutex_init(&ctx->mapping_lock);\n \tctx->mapping = NULL;\n \n-\t/*\n-\t * Allocate the segment table before we put it in the IDR so that we\n-\t * can always access it when dereferenced from IDR. For the same\n-\t * reason, the segment table is only destroyed after the context is\n-\t * removed from the IDR. Access to this in the IOCTL is protected by\n-\t * Linux filesytem symantics (can't IOCTL until open is complete).\n-\t */\n-\ti = cxl_alloc_sst(ctx);\n-\tif (i)\n-\t\treturn i;\n+\tif (cxl_is_psl8(afu)) {\n+\t\tspin_lock_init(&ctx->sste_lock);\n+\n+\t\t/*\n+\t\t * Allocate the segment table before we put it in the IDR so that we\n+\t\t * can always access it when dereferenced from IDR. For the same\n+\t\t * reason, the segment table is only destroyed after the context is\n+\t\t * removed from the IDR. Access to this in the IOCTL is protected by\n+\t\t * Linux filesytem symantics (can't IOCTL until open is complete).\n+\t\t */\n+\t\ti = cxl_alloc_sst(ctx);\n+\t\tif (i)\n+\t\t\treturn i;\n+\t}\n \n \tINIT_WORK(&ctx->fault_work, cxl_handle_fault);\n \n@@ -308,7 +311,8 @@ static void reclaim_ctx(struct rcu_head *rcu)\n {\n \tstruct cxl_context *ctx = container_of(rcu, struct cxl_context, rcu);\n \n-\tfree_page((u64)ctx->sstp);\n+\tif (cxl_is_psl8(ctx->afu))\n+\t\tfree_page((u64)ctx->sstp);\n \tif (ctx->ff_page)\n \t\t__free_page(ctx->ff_page);\n \tctx->sstp = NULL;\ndiff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h\nindex c7dd315..2f2d9e4 100644\n--- a/drivers/misc/cxl/cxl.h\n+++ b/drivers/misc/cxl/cxl.h\n@@ -73,7 +73,7 @@ static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};\n static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};\n static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};\n \n-/* PSL Lookaside Buffer Management Area */\n+/* PSL Lookaside Buffer Management Area - CAIA 1 */\n static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};\n static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};\n static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};\n@@ -82,7 +82,7 @@ static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};\n static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};\n \n /* 0x00C0:7EFF Implementation dependent area */\n-/* PSL registers */\n+/* PSL registers - CAIA 1 */\n static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};\n static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};\n static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};\n@@ -109,7 +109,7 @@ static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};\n static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};\n static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};\n static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};\n-/* Memory Management and Lookaside Buffer Management */\n+/* Memory Management and Lookaside Buffer Management - CAIA 1*/\n static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};\n static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};\n /* Pointer Area */\n@@ -124,6 +124,7 @@ static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};\n /* 0xC0:FF Implementation Dependent Area */\n static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};\n static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};\n+/* 0xC0:FF Implementation Dependent Area - CAIA 1 */\n static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};\n static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};\n static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};\n@@ -133,12 +134,14 @@ static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};\n /* Configuration and Control Area */\n static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};\n static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};\n+/* Configuration and Control Area - CAIA 1 */\n static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};\n static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};\n static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};\n static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};\n+/* Configuration and Control Area - CAIA 1 */\n static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};\n-/* Segment Lookaside Buffer Management */\n+/* Segment Lookaside Buffer Management - CAIA 1 */\n static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};\n static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};\n static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};\n@@ -257,7 +260,7 @@ static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};\n #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))\n #define CXL_SSTP1_An_V (1ull << (63-63))\n \n-/****** CXL_PSL_SLBIE_[An] **************************************************/\n+/****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/\n /* write: */\n #define CXL_SLBIE_C PPC_BIT(36) /* Class */\n #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */\n@@ -267,10 +270,10 @@ static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};\n #define CXL_SLBIE_MAX PPC_BITMASK(24, 31)\n #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)\n \n-/****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/\n+/****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/\n #define CXL_TLB_SLB_P (1ull) /* Pending (read) */\n \n-/****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/\n+/****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/\n #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */\n #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */\n #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */\n@@ -278,7 +281,7 @@ static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};\n /****** CXL_PSL_AFUSEL ******************************************************/\n #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */\n \n-/****** CXL_PSL_DSISR_An ****************************************************/\n+/****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/\n #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */\n #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */\n #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */\n@@ -749,6 +752,22 @@ static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)\n \t\treturn ~0ULL;\n }\n \n+static inline bool cxl_is_power8(void)\n+{\n+\tif ((pvr_version_is(PVR_POWER8E)) ||\n+\t (pvr_version_is(PVR_POWER8NVL)) ||\n+\t (pvr_version_is(PVR_POWER8)))\n+\t\treturn true;\n+\treturn false;\n+}\n+\n+static inline bool cxl_is_psl8(struct cxl_afu *afu)\n+{\n+\tif (afu->adapter->caia_major == 1)\n+\t\treturn true;\n+\treturn false;\n+}\n+\n ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,\n \t\t\t\tloff_t off, size_t count);\n \ndiff --git a/drivers/misc/cxl/debugfs.c b/drivers/misc/cxl/debugfs.c\nindex 2ff10a9..43a1a27 100644\n--- a/drivers/misc/cxl/debugfs.c\n+++ b/drivers/misc/cxl/debugfs.c\n@@ -94,6 +94,9 @@ void cxl_debugfs_adapter_remove(struct cxl *adapter)\n \n void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)\n {\n+\tdebugfs_create_io_x64(\"sstp0\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_SSTP0_An));\n+\tdebugfs_create_io_x64(\"sstp1\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_SSTP1_An));\n+\n \tdebugfs_create_io_x64(\"fir\", S_IRUSR, dir, _cxl_p1n_addr(afu, CXL_PSL_FIR_SLICE_An));\n \tdebugfs_create_io_x64(\"serr\", S_IRUSR, dir, _cxl_p1n_addr(afu, CXL_PSL_SERR_An));\n \tdebugfs_create_io_x64(\"afu_debug\", S_IRUSR, dir, _cxl_p1n_addr(afu, CXL_AFU_DEBUG_An));\n@@ -117,8 +120,7 @@ int cxl_debugfs_afu_add(struct cxl_afu *afu)\n \tdebugfs_create_io_x64(\"sr\", S_IRUSR, dir, _cxl_p1n_addr(afu, CXL_PSL_SR_An));\n \tdebugfs_create_io_x64(\"dsisr\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_PSL_DSISR_An));\n \tdebugfs_create_io_x64(\"dar\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_PSL_DAR_An));\n-\tdebugfs_create_io_x64(\"sstp0\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_SSTP0_An));\n-\tdebugfs_create_io_x64(\"sstp1\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_SSTP1_An));\n+\n \tdebugfs_create_io_x64(\"err_status\", S_IRUSR, dir, _cxl_p2n_addr(afu, CXL_PSL_ErrStat_An));\n \n \tif (afu->adapter->native->sl_ops->debugfs_add_afu_regs)\ndiff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c\nindex cf8488b..f24c15c 100644\n--- a/drivers/misc/cxl/fault.c\n+++ b/drivers/misc/cxl/fault.c\n@@ -230,12 +230,14 @@ void cxl_handle_fault(struct work_struct *fault_work)\n \t\t}\n \t}\n \n-\tif (dsisr & CXL_PSL_DSISR_An_DS)\n-\t\tcxl_handle_segment_miss(ctx, mm, dar);\n-\telse if (dsisr & CXL_PSL_DSISR_An_DM)\n-\t\tcxl_handle_page_fault(ctx, mm, dsisr, dar);\n-\telse\n-\t\tWARN(1, \"cxl_handle_fault has nothing to handle\\n\");\n+\tif (cxl_is_psl8(ctx->afu)) {\n+\t\tif (dsisr & CXL_PSL_DSISR_An_DS)\n+\t\t\tcxl_handle_segment_miss(ctx, mm, dar);\n+\t\telse if (dsisr & CXL_PSL_DSISR_An_DM)\n+\t\t\tcxl_handle_page_fault(ctx, mm, dsisr, dar);\n+\t\telse\n+\t\t\tWARN(1, \"cxl_handle_fault has nothing to handle\\n\");\n+\t}\n \n \tif (mm)\n \t\tmmput(mm);\ndiff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c\nindex 9f7f06d..7b86ffa 100644\n--- a/drivers/misc/cxl/native.c\n+++ b/drivers/misc/cxl/native.c\n@@ -155,16 +155,25 @@ int cxl_psl_purge(struct cxl_afu *afu)\n \t\t}\n \n \t\tdsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);\n-\t\tpr_devel_ratelimited(\"PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\\n\", PSL_CNTL, dsisr);\n-\t\tif (dsisr & CXL_PSL_DSISR_TRANS) {\n-\t\t\tdar = cxl_p2n_read(afu, CXL_PSL_DAR_An);\n-\t\t\tdev_notice(&afu->dev, \"PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\\n\", dsisr, dar);\n-\t\t\tcxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);\n-\t\t} else if (dsisr) {\n-\t\t\tdev_notice(&afu->dev, \"PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\\n\", dsisr);\n-\t\t\tcxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);\n-\t\t} else {\n-\t\t\tcpu_relax();\n+\t\tpr_devel_ratelimited(\"PSL purging... PSL_CNTL: 0x%016llx\"\n+\t\t\t\t \" PSL_DSISR: 0x%016llx\\n\",\n+\t\t\t\t PSL_CNTL, dsisr);\n+\t\tif (cxl_is_psl8(afu)) {\n+\t\t\tif (dsisr & CXL_PSL_DSISR_TRANS) {\n+\t\t\t\tdar = cxl_p2n_read(afu, CXL_PSL_DAR_An);\n+\t\t\t\tdev_notice(&afu->dev, \"PSL purge terminating \"\n+\t\t\t\t\t\t \"pending translation, \"\n+\t\t\t\t\t\t \"DSISR: 0x%016llx, DAR: 0x%016llx\\n\",\n+\t\t\t\t\t\t dsisr, dar);\n+\t\t\t\tcxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);\n+\t\t\t} else if (dsisr) {\n+\t\t\t\tdev_notice(&afu->dev, \"PSL purge acknowledging \"\n+\t\t\t\t\t\t \"pending non-translation fault, \"\n+\t\t\t\t\t\t \"DSISR: 0x%016llx\\n\", dsisr);\n+\t\t\t\tcxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);\n+\t\t\t} else {\n+\t\t\t\tcpu_relax();\n+\t\t\t}\n \t\t}\n \t\tPSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);\n \t}\n@@ -466,7 +475,8 @@ static int remove_process_element(struct cxl_context *ctx)\n \n \tif (!rc)\n \t\tctx->pe_inserted = false;\n-\tslb_invalid(ctx);\n+\tif (cxl_is_power8())\n+\t\tslb_invalid(ctx);\n \tpr_devel(\"%s Remove pe: %i finished\\n\", __func__, ctx->pe);\n \tmutex_unlock(&ctx->afu->native->spa_mutex);\n \n@@ -499,7 +509,8 @@ static int activate_afu_directed(struct cxl_afu *afu)\n \tattach_spa(afu);\n \n \tcxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);\n-\tcxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);\n+\tif (cxl_is_power8())\n+\t\tcxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);\n \tcxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);\n \n \tafu->current_mode = CXL_MODE_DIRECTED;\n@@ -872,7 +883,8 @@ static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)\n \n \tinfo->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);\n \tinfo->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);\n-\tinfo->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);\n+\tif (cxl_is_power8())\n+\t\tinfo->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);\n \tinfo->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);\n \tinfo->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);\n \tinfo->proc_handle = 0;\n@@ -986,7 +998,8 @@ static void native_irq_wait(struct cxl_context *ctx)\n \t\tif (ph != ctx->pe)\n \t\t\treturn;\n \t\tdsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);\n-\t\tif ((dsisr & CXL_PSL_DSISR_PENDING) == 0)\n+\t\tif (cxl_is_psl8(ctx->afu) &&\n+\t\t ((dsisr & CXL_PSL_DSISR_PENDING) == 0))\n \t\t\treturn;\n \t\t/*\n \t\t * We are waiting for the workqueue to process our\n@@ -1003,21 +1016,25 @@ static void native_irq_wait(struct cxl_context *ctx)\n static irqreturn_t native_slice_irq_err(int irq, void *data)\n {\n \tstruct cxl_afu *afu = data;\n-\tu64 fir_slice, errstat, serr, afu_debug, afu_error, dsisr;\n+\tu64 errstat, serr, afu_error, dsisr;\n+\tu64 fir_slice, afu_debug;\n \n \t/*\n \t * slice err interrupt is only used with full PSL (no XSL)\n \t */\n \tserr = cxl_p1n_read(afu, CXL_PSL_SERR_An);\n-\tfir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);\n \terrstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);\n-\tafu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);\n \tafu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);\n \tdsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);\n \tcxl_afu_decode_psl_serr(afu, serr);\n-\tdev_crit(&afu->dev, \"PSL_FIR_SLICE_An: 0x%016llx\\n\", fir_slice);\n+\n+\tif (cxl_is_power8()) {\n+\t\tfir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);\n+\t\tafu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);\n+\t\tdev_crit(&afu->dev, \"PSL_FIR_SLICE_An: 0x%016llx\\n\", fir_slice);\n+\t\tdev_crit(&afu->dev, \"CXL_PSL_AFU_DEBUG_An: 0x%016llx\\n\", afu_debug);\n+\t}\n \tdev_crit(&afu->dev, \"CXL_PSL_ErrStat_An: 0x%016llx\\n\", errstat);\n-\tdev_crit(&afu->dev, \"CXL_PSL_AFU_DEBUG_An: 0x%016llx\\n\", afu_debug);\n \tdev_crit(&afu->dev, \"AFU_ERR_An: 0x%.16llx\\n\", afu_error);\n \tdev_crit(&afu->dev, \"PSL_DSISR_An: 0x%.16llx\\n\", dsisr);\n \n@@ -1110,7 +1127,8 @@ int cxl_native_register_serr_irq(struct cxl_afu *afu)\n \t}\n \n \tserr = cxl_p1n_read(afu, CXL_PSL_SERR_An);\n-\tserr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);\n+\tif (cxl_is_power8())\n+\t\tserr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);\n \tcxl_p1n_write(afu, CXL_PSL_SERR_An, serr);\n \n \treturn 0;\ndiff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c\nindex cb76013..360c231 100644\n--- a/drivers/misc/cxl/pci.c\n+++ b/drivers/misc/cxl/pci.c\n@@ -324,32 +324,33 @@ static void dump_afu_descriptor(struct cxl_afu *afu)\n #undef show_reg\n }\n \n-#define CAPP_UNIT0_ID 0xBA\n-#define CAPP_UNIT1_ID 0XBE\n+#define P8_CAPP_UNIT0_ID 0xBA\n+#define P8_CAPP_UNIT1_ID 0XBE\n \n static u64 get_capp_unit_id(struct device_node *np)\n {\n \tu32 phb_index;\n \n-\t/*\n-\t * For chips other than POWER8NVL, we only have CAPP 0,\n-\t * irrespective of which PHB is used.\n-\t */\n-\tif (!pvr_version_is(PVR_POWER8NVL))\n-\t\treturn CAPP_UNIT0_ID;\n+\tif (of_property_read_u32(np, \"ibm,phb-index\", &phb_index))\n+\t\treturn 0;\n \n \t/*\n-\t * For POWER8NVL, assume CAPP 0 is attached to PHB0 and\n-\t * CAPP 1 is attached to PHB1.\n+\t * POWER 8:\n+\t * - For chips other than POWER8NVL, we only have CAPP 0,\n+\t * irrespective of which PHB is used.\n+\t * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and\n+\t * CAPP 1 is attached to PHB1.\n \t */\n-\tif (of_property_read_u32(np, \"ibm,phb-index\", &phb_index))\n-\t\treturn 0;\n+\tif (cxl_is_power8()) {\n+\t\tif (!pvr_version_is(PVR_POWER8NVL))\n+\t\t\treturn P8_CAPP_UNIT0_ID;\n \n-\tif (phb_index == 0)\n-\t\treturn CAPP_UNIT0_ID;\n+\t\tif (phb_index == 0)\n+\t\t\treturn P8_CAPP_UNIT0_ID;\n \n-\tif (phb_index == 1)\n-\t\treturn CAPP_UNIT1_ID;\n+\t\tif (phb_index == 1)\n+\t\t\treturn P8_CAPP_UNIT1_ID;\n+\t}\n \n \treturn 0;\n }\n@@ -968,7 +969,7 @@ static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)\n \t}\n \n \tif (afu->pp_psa && (afu->pp_size < PAGE_SIZE))\n-\t\tdev_warn(&afu->dev, \"AFU uses < PAGE_SIZE per-process PSA!\");\n+\t\tdev_warn(&afu->dev, \"AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\\n\", afu->pp_size);\n \n \tfor (i = 0; i < afu->crs_num; i++) {\n \t\trc = cxl_ops->afu_cr_read32(afu, i, 0, &val);\n@@ -1251,8 +1252,13 @@ int cxl_pci_reset(struct cxl *adapter)\n \n \tdev_info(&dev->dev, \"CXL reset\\n\");\n \n-\t/* the adapter is about to be reset, so ignore errors */\n-\tcxl_data_cache_flush(adapter);\n+\t/*\n+\t * The adapter is about to be reset, so ignore errors.\n+\t * Not supported on P9 DD1 but don't forget to enable it\n+\t * on P9 DD2\n+\t */\n+\tif (cxl_is_power8())\n+\t\tcxl_data_cache_flush(adapter);\n \n \t/* pcie_warm_reset requests a fundamental pci reset which includes a\n \t * PERST assert/deassert. PERST triggers a loading of the image\n@@ -1382,6 +1388,14 @@ static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)\n \tpci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);\n }\n \n+static bool cxl_compatible_caia_version(struct cxl *adapter)\n+{\n+\tif (cxl_is_power8() && (adapter->caia_major == 1))\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)\n {\n \tif (adapter->vsec_status & CXL_STATUS_SECOND_PORT)\n@@ -1392,6 +1406,12 @@ static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)\n \t\treturn -EINVAL;\n \t}\n \n+\tif (!cxl_compatible_caia_version(adapter)) {\n+\t\tdev_info(&dev->dev, \"Ignoring card. PSL type is not supported \"\n+\t\t\t\t \"(caia version: %d)\\n\", adapter->caia_major);\n+\t\treturn -ENODEV;\n+\t}\n+\n \tif (!adapter->slices) {\n \t\t/* Once we support dynamic reprogramming we can use the card if\n \t\t * it supports loadable AFUs */\n@@ -1566,8 +1586,10 @@ static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)\n \t\tadapter->native->sl_ops = &xsl_ops;\n \t\tadapter->min_pe = 1; /* Workaround for CX-4 hardware bug */\n \t} else {\n-\t\tdev_info(&dev->dev, \"Device uses a PSL8\\n\");\n-\t\tadapter->native->sl_ops = &psl8_ops;\n+\t\tif (cxl_is_power8()) {\n+\t\t\tdev_info(&dev->dev, \"Device uses a PSL8\\n\");\n+\t\t\tadapter->native->sl_ops = &psl8_ops;\n+\t\t}\n \t}\n }\n \n", "prefixes": [ "V3", "6/7" ] }