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GET /api/patches/740018/?format=api
{ "id": 740018, "url": "http://patchwork.ozlabs.org/api/patches/740018/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/patch/20170316213624.140344-15-maxims@google.com/", "project": { "id": 56, "url": "http://patchwork.ozlabs.org/api/projects/56/?format=api", "name": "OpenBMC development", "link_name": "openbmc", "list_id": "openbmc.lists.ozlabs.org", "list_email": "openbmc@lists.ozlabs.org", "web_url": "http://github.com/openbmc/", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170316213624.140344-15-maxims@google.com>", "list_archive_url": null, "date": "2017-03-16T21:36:21", "name": "[14/17] aspeed: Refactor SCU to use consistent mask & shift", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "ed18c343bbde6e4de1253de305f8661f8e0a74df", "submitter": { "id": 69876, "url": "http://patchwork.ozlabs.org/api/people/69876/?format=api", "name": "Maxim Sloyko", "email": "maxims@google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openbmc/patch/20170316213624.140344-15-maxims@google.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/740018/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/740018/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vkhj01rRJz9s0Z\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 17 Mar 2017 08:40:20 +1100 (AEDT)", "from lists.ozlabs.org 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\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=gWmK54AhHgdf9h3tHZgWy2HPSpQV8DfvF8tO7CeXGI0=;\n\tb=tBFp1m/8kMj3XMNuY5wBsiYDOg7GaKioD2Bjv+1YtA2Xh4tj23kdmKD3yDPt0sORHM\n\trfsSRkf3FSjFijeOuqnTZhmghGeo7bGVXbQP2hzOMC9FuWzaOsq9iWIBZDkM4ZJ1Cx/v\n\tl3BiyXk3CFHv1U4UxMEgRvFc97S1gz42F+8PObYRdkxHwtAGwntWpvB+G645kzONWD3K\n\tYRuxXG0bBZYsIYlraK1VfVm3gLUftmCcVwRMEe76ptVRfLsgfa5TNHgA64pBWn6KGIU7\n\tLENO9U3uzTYXrTUOqvMu/v71WuK9d/f8mGj3UlAW/9L7LgyeYDGaLhgw/RzikOJ6cTMD\n\traFQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; 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"<20170316213624.140344-15-maxims@google.com>", "X-Mailer": "git-send-email 2.12.0.367.g23dc2f6d3c-goog", "In-Reply-To": "<20170316213624.140344-1-maxims@google.com>", "References": "<20170316213624.140344-1-maxims@google.com>", "X-BeenThere": "openbmc@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Development list for OpenBMC <openbmc.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/openbmc/>", "List-Post": "<mailto:openbmc@lists.ozlabs.org>", "List-Help": "<mailto:openbmc-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/openbmc>,\n\t<mailto:openbmc-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Albert Aribaud <albert.u.boot@aribaud.net>, openbmc@lists.ozlabs.org", "Errors-To": "openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"openbmc\"\n\t<openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "Refactor SCU header to use consistent Mask & Shift values.\nNow, consistently, to read value from SCU register, mask needs\nto be applied before shift.\n\nSigned-off-by: Maxim Sloyko <maxims@google.com>\n---\n\n arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 12 ++++----\n arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 5 ++--\n drivers/clk/aspeed/clk_ast2500.c | 39 +++++++++++++-------------\n 3 files changed, 27 insertions(+), 29 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h\nindex fe877b5430..590aed2f6c 100644\n--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h\n+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h\n@@ -8,8 +8,8 @@\n \n #define SCU_UNLOCK_VALUE\t\t0x1688a8a8\n \n-#define SCU_HWSTRAP_VGAMEM_MASK\t\t3\n #define SCU_HWSTRAP_VGAMEM_SHIFT\t2\n+#define SCU_HWSTRAP_VGAMEM_MASK\t\t(3 << SCU_HWSTRAP_VGAMEM_SHIFT)\n #define SCU_HWSTRAP_MAC1_RGMII\t\t(1 << 6)\n #define SCU_HWSTRAP_MAC2_RGMII\t\t(1 << 7)\n #define SCU_HWSTRAP_DDR4\t\t(1 << 24)\n@@ -18,17 +18,17 @@\n #define SCU_MPLL_DENUM_SHIFT\t\t0\n #define SCU_MPLL_DENUM_MASK\t\t0x1f\n #define SCU_MPLL_NUM_SHIFT\t\t5\n-#define SCU_MPLL_NUM_MASK\t\t0xff\n+#define SCU_MPLL_NUM_MASK\t\t(0xff << SCU_MPLL_NUM_SHIFT)\n #define SCU_MPLL_POST_SHIFT\t\t13\n-#define SCU_MPLL_POST_MASK\t\t0x3f\n+#define SCU_MPLL_POST_MASK\t\t(0x3f << SCU_MPLL_POST_SHIFT)\n #define SCU_PCLK_DIV_SHIFT\t\t23\n-#define SCU_PCLK_DIV_MASK\t\t7\n+#define SCU_PCLK_DIV_MASK\t\t(7 << SCU_PCLK_DIV_SHIFT)\n #define SCU_HPLL_DENUM_SHIFT\t\t0\n #define SCU_HPLL_DENUM_MASK\t\t0x1f\n #define SCU_HPLL_NUM_SHIFT\t\t5\n-#define SCU_HPLL_NUM_MASK\t\t0xff\n+#define SCU_HPLL_NUM_MASK\t\t(0xff << SCU_HPLL_NUM_SHIFT)\n #define SCU_HPLL_POST_SHIFT\t\t13\n-#define SCU_HPLL_POST_MASK\t\t0x3f\n+#define SCU_HPLL_POST_MASK\t\t(0x3f << SCU_HPLL_POST_SHIFT)\n \n #define SCU_MACCLK_SHIFT\t\t16\n #define SCU_MACCLK_MASK\t\t\t(7 << SCU_MACCLK_SHIFT)\ndiff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c\nindex efcf452b17..6383f727f2 100644\n--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c\n+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c\n@@ -183,9 +183,8 @@ static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)\n static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)\n {\n \tsize_t vga_mem_size_base = 8 * 1024 * 1024;\n-\tu32 vga_hwconf = (readl(&info->scu->hwstrap)\n-\t\t\t >> SCU_HWSTRAP_VGAMEM_SHIFT)\n-\t\t\t& SCU_HWSTRAP_VGAMEM_MASK;\n+\tu32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)\n+\t >> SCU_HWSTRAP_VGAMEM_SHIFT;\n \n \treturn vga_mem_size_base << vga_hwconf;\n }\ndiff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c\nindex 7b4b5c64ac..ccf47a1da1 100644\n--- a/drivers/clk/aspeed/clk_ast2500.c\n+++ b/drivers/clk/aspeed/clk_ast2500.c\n@@ -52,11 +52,11 @@ struct ast2500_div_config {\n */\n static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)\n {\n-\tconst ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK;\n-\tconst ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT)\n-\t\t\t& SCU_MPLL_DENUM_MASK;\n-\tconst ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)\n-\t\t\t& SCU_MPLL_POST_MASK;\n+\tconst ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;\n+\tconst ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)\n+\t\t\t>> SCU_MPLL_DENUM_SHIFT;\n+\tconst ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)\n+\t\t\t>> SCU_MPLL_POST_SHIFT;\n \n \treturn (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);\n }\n@@ -67,11 +67,11 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)\n */\n static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)\n {\n-\tconst ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK;\n-\tconst ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT)\n-\t\t\t& SCU_HPLL_DENUM_MASK;\n-\tconst ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)\n-\t\t\t& SCU_HPLL_POST_MASK;\n+\tconst ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;\n+\tconst ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)\n+\t\t\t>> SCU_HPLL_DENUM_SHIFT;\n+\tconst ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)\n+\t\t\t>> SCU_HPLL_POST_SHIFT;\n \n \treturn (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);\n }\n@@ -136,11 +136,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)\n \tcase BCLK_PCLK:\n \t\t{\n \t\t\tulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)\n-\t\t\t\t\t\t >> SCU_PCLK_DIV_SHIFT) &\n-\t\t\t\t\t\t SCU_PCLK_DIV_MASK);\n+\t\t\t\t\t\t & SCU_PCLK_DIV_MASK)\n+\t\t\t\t\t\t >> SCU_PCLK_DIV_SHIFT);\n \t\t\trate = ast2500_get_hpll_rate(clkin,\n-\t\t\t\t\t\t readl(&priv->scu->\n-\t\t\t\t\t\t\t h_pll_param));\n+\t\t\t\t\t\t readl(&priv->\n+\t\t\t\t\t\t\t scu->h_pll_param));\n \t\t\trate = rate / apb_div;\n \t\t}\n \t\tbreak;\n@@ -223,17 +223,16 @@ static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)\n \tulong clkin = ast2500_get_clkin(scu);\n \tu32 mpll_reg;\n \tstruct ast2500_div_config div_cfg = {\n-\t\t.num = SCU_MPLL_NUM_MASK,\n-\t\t.denum = SCU_MPLL_DENUM_MASK,\n-\t\t.post_div = SCU_MPLL_POST_MASK\n+\t\t.num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),\n+\t\t.denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),\n+\t\t.post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),\n \t};\n \n \tast2500_calc_clock_config(clkin, rate, &div_cfg);\n \n \tmpll_reg = readl(&scu->m_pll_param);\n-\tmpll_reg &= ~((SCU_MPLL_POST_MASK << SCU_MPLL_POST_SHIFT)\n-\t\t | (SCU_MPLL_NUM_MASK << SCU_MPLL_NUM_SHIFT)\n-\t\t | (SCU_MPLL_DENUM_MASK << SCU_MPLL_DENUM_SHIFT));\n+\tmpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK\n+\t\t | SCU_MPLL_DENUM_MASK);\n \tmpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)\n \t | (div_cfg.num << SCU_MPLL_NUM_SHIFT)\n \t | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);\n", "prefixes": [ "14/17" ] }