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GET /api/patches/726445/?format=api
{ "id": 726445, "url": "http://patchwork.ozlabs.org/api/patches/726445/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/1486717462-5016-5-git-send-email-clombard@linux.vnet.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1486717462-5016-5-git-send-email-clombard@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2017-02-10T09:04:22", "name": "[4/4] capi: Load capp microcode for phb4", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "dda05517fab401a0e1f41de2b5ac8fd49a994bc5", "submitter": { "id": 67351, "url": "http://patchwork.ozlabs.org/api/people/67351/?format=api", "name": "Christophe Lombard", "email": "clombard@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/1486717462-5016-5-git-send-email-clombard@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/726445/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/726445/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vKTZ225mlz9s2G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Feb 2017 20:05:46 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3vKTZ21MbGzDqJZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Feb 2017 20:05:46 +1100 (AEDT)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3vKTYF4kyhzDqGX\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 20:05:05 +1100 (AEDT)", "from pps.filterd (m0098421.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id\n\tv1A8x3mP102961\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 04:05:03 -0500", "from e06smtp08.uk.ibm.com (e06smtp08.uk.ibm.com [195.75.94.104])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 28gxd2h4ea-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 04:05:02 -0500", "from localhost\n\tby e06smtp08.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <skiboot@lists.ozlabs.org> from <clombard@linux.vnet.ibm.com>;\n\tFri, 10 Feb 2017 09:05:01 -0000", "from d06dlp03.portsmouth.uk.ibm.com (9.149.20.15)\n\tby e06smtp08.uk.ibm.com (192.168.101.138) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tFri, 10 Feb 2017 09:04:58 -0000", "from b06cxnps4076.portsmouth.uk.ibm.com\n\t(d06relay13.portsmouth.uk.ibm.com [9.149.109.198])\n\tby d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id\n\t24BBA1B08067\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 09:07:52 +0000 (GMT)", "from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com\n\t[9.149.105.59])\n\tby b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v1A94WTP9634290; Fri, 10 Feb 2017 09:04:32 GMT", "from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 93678A4065;\n\tFri, 10 Feb 2017 09:04:28 +0000 (GMT)", "from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 9320DA405D;\n\tFri, 10 Feb 2017 09:04:27 +0000 (GMT)", "from lombard-w520.ibm.com (unknown [9.164.182.111])\n\tby d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tFri, 10 Feb 2017 09:04:27 +0000 (GMT)" ], "From": "Christophe Lombard <clombard@linux.vnet.ibm.com>", "To": "skiboot@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com, imunsie@au1.ibm.com,\n\tandrew.donnellan@au1.ibm.com, christophe_lombard@fr.ibm.com", "Date": "Fri, 10 Feb 2017 10:04:22 +0100", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1486717462-5016-1-git-send-email-clombard@linux.vnet.ibm.com>", "References": "<1486717462-5016-1-git-send-email-clombard@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "17021009-0032-0000-0000-0000071AA7E5", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17021009-0033-0000-0000-00002360D343", "Message-Id": "<1486717462-5016-5-git-send-email-clombard@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-02-10_03:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=2\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000\n\tdefinitions=main-1702100090", "Subject": "[Skiboot] [PATCH 4/4] capi: Load capp microcode for phb4", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "CAPP microcode flash download and CAPP upload for PHB4.\nA new file 'capp.c' is created to receive common capp code for PHB3 and\nPHB4.\n\nSigned-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>\n---\n core/init.c | 2 +-\n hw/Makefile.inc | 2 +-\n hw/capp.c | 235 ++++++++++++++++++++++++++++++++++++++++++++++++++++++\n hw/phb3.c | 212 ++++--------------------------------------------\n hw/phb4.c | 15 ++++\n include/capp.h | 18 ++++-\n include/skiboot.h | 3 +-\n 7 files changed, 283 insertions(+), 204 deletions(-)\n create mode 100644 hw/capp.c", "diff": "diff --git a/core/init.c b/core/init.c\nindex 7bcb680..795746c 100644\n--- a/core/init.c\n+++ b/core/init.c\n@@ -918,7 +918,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt)\n \top_display(OP_LOG, OP_MOD_INIT, 0x0002);\n \n \tphb3_preload_vpd();\n-\tphb3_preload_capp_ucode();\n+\tpreload_capp_ucode();\n \tstart_preload_kernel();\n \n \t/* NX init */\ndiff --git a/hw/Makefile.inc b/hw/Makefile.inc\nindex f2dc328..5a3fd39 100644\n--- a/hw/Makefile.inc\n+++ b/hw/Makefile.inc\n@@ -6,7 +6,7 @@ HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-842.o\n HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o\n HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o\n HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o\n-HW_OBJS += fake-nvram.o\n+HW_OBJS += fake-nvram.o capp.o\n HW=hw/built-in.o\n \n # FIXME hack this for now\ndiff --git a/hw/capp.c b/hw/capp.c\nnew file mode 100644\nindex 0000000..c7c359d\n--- /dev/null\n+++ b/hw/capp.c\n@@ -0,0 +1,235 @@\n+/* Copyright 2013-2017 IBM Corp.\n+ *\n+ * Licensed under the Apache License, Version 2.0 (the \"License\");\n+ * you may not use this file except in compliance with the License.\n+ * You may obtain a copy of the License at\n+ *\n+ * \thttp://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS,\n+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or\n+ * implied.\n+ * See the License for the specific language governing permissions and\n+ * limitations under the License.\n+ */\n+#include <skiboot.h>\n+#include <io.h>\n+#include <opal.h>\n+#include <chip.h>\n+#include <xscom.h>\n+#include <capp.h>\n+\n+#define PHBERR(opal_id, chip_id, index, fmt, a...) \\\n+\t prlog(PR_ERR, \"PHB#%04x[%d:%d]: \" fmt, \\\n+\t\t opal_id, chip_id, \\\n+\t\t index, ## a)\n+\n+static struct {\n+\tuint32_t\t\t\tec_level;\n+\tstruct capp_lid_hdr\t\t*lid;\n+\tsize_t size;\n+\tint load_result;\n+} capp_ucode_info = { 0, NULL, 0, false };\n+\n+#define CAPP_UCODE_MAX_SIZE 0x20000\n+\n+bool capp_ucode_loaded(struct proc_chip *chip, unsigned int index)\n+{\n+\treturn (chip->capp_ucode_loaded & (1 << index));\n+}\n+\n+int preload_capp_ucode(void)\n+{\n+\tstruct dt_node *p;\n+\tstruct proc_chip *chip;\n+\tuint32_t index;\n+\tuint64_t rc;\n+\tint ret;\n+\n+\tp = dt_find_compatible_node(dt_root, NULL, \"ibm,power8-pbcq\");\n+\n+\tif (!p) {\n+\t\tp = dt_find_compatible_node(dt_root, NULL, \"ibm,power9-pbcq\");\n+\t\tif (!p) {\n+\t\t\tprintf(\"CAPI: WARNING: no compat thing found\\n\");\n+\t\t\treturn OPAL_SUCCESS;\n+\t\t}\n+\t}\n+\n+\tchip = get_chip(dt_get_chip_id(p));\n+\n+\trc = xscom_read_cfam_chipid(chip->id, &index);\n+\tif (rc) {\n+\t\tprerror(\"CAPP: Error reading cfam chip-id\\n\");\n+\t\tret = OPAL_HARDWARE;\n+\t\treturn ret;\n+\t}\n+\t/* Keep ChipID and Major/Minor EC. Mask out the Location Code. */\n+\tindex = index & 0xf0fff;\n+\n+\t/* Assert that we're preloading */\n+\tassert(capp_ucode_info.lid == NULL);\n+\tcapp_ucode_info.load_result = OPAL_EMPTY;\n+\n+\tcapp_ucode_info.ec_level = index;\n+\n+\t/* Is the ucode preloaded like for BML? */\n+\tif (dt_has_node_property(p, \"ibm,capp-ucode\", NULL)) {\n+\t\tcapp_ucode_info.lid = (struct capp_lid_hdr *)(u64)\n+\t\t\tdt_prop_get_u32(p, \"ibm,capp-ucode\");\n+\t\tret = OPAL_SUCCESS;\n+\t\tgoto end;\n+\t}\n+\t/* If we successfully download the ucode, we leave it around forever */\n+\tcapp_ucode_info.size = CAPP_UCODE_MAX_SIZE;\n+\tcapp_ucode_info.lid = malloc(CAPP_UCODE_MAX_SIZE);\n+\tif (!capp_ucode_info.lid) {\n+\t\tprerror(\"CAPP: Can't allocate space for ucode lid\\n\");\n+\t\tret = OPAL_NO_MEM;\n+\t\tgoto end;\n+\t}\n+\n+\tprintf(\"CAPI: Preloading ucode %x\\n\", capp_ucode_info.ec_level);\n+\n+\tret = start_preload_resource(RESOURCE_ID_CAPP, index,\n+\t\t\t\t capp_ucode_info.lid,\n+\t\t\t\t &capp_ucode_info.size);\n+\n+\tif (ret != OPAL_SUCCESS)\n+\t\tprerror(\"CAPI: Failed to preload resource %d\\n\", ret);\n+\n+end:\n+\treturn ret;\n+}\n+\n+static int64_t capp_lid_download(void)\n+{\n+\tint64_t ret;\n+\n+\tif (capp_ucode_info.load_result != OPAL_EMPTY)\n+\t\treturn capp_ucode_info.load_result;\n+\n+\tcapp_ucode_info.load_result = wait_for_resource_loaded(\n+\t\tRESOURCE_ID_CAPP,\n+\t\tcapp_ucode_info.ec_level);\n+\n+\tif (capp_ucode_info.load_result != OPAL_SUCCESS) {\n+\t\tprerror(\"CAPP: Error loading ucode lid. index=%x\\n\",\n+\t\t\tcapp_ucode_info.ec_level);\n+\t\tret = OPAL_RESOURCE;\n+\t\tfree(capp_ucode_info.lid);\n+\t\tcapp_ucode_info.lid = NULL;\n+\t\tgoto end;\n+\t}\n+\n+\tret = OPAL_SUCCESS;\n+end:\n+\treturn ret;\n+}\n+\n+int64_t capp_load_ucode(unsigned int index, unsigned int chip_id,\n+\t\t\tunsigned int max_phb_index, u64 lidec,\n+\t\t\tuint32_t reg_offset, uint32_t opal_id,\n+\t\t\tuint64_t apc_master_addr, uint64_t apc_master_write,\n+\t\t\tuint64_t snp_array_addr, uint64_t snp_array_write)\n+{\n+\tstruct proc_chip *chip = get_chip(chip_id);\n+\tstruct capp_ucode_lid *ucode;\n+\tstruct capp_ucode_data *data;\n+\tstruct capp_lid_hdr *lid;\n+\tuint64_t rc, val, addr;\n+\tuint32_t chunk_count, offset;\n+\tint i;\n+\n+\tif (capp_ucode_loaded(chip, index))\n+\t\treturn OPAL_SUCCESS;\n+\n+\t/* Return if PHB not attached to a CAPP unit */\n+\tif (index > max_phb_index)\n+\t\treturn OPAL_HARDWARE;\n+\n+\trc = capp_lid_download();\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tprlog(PR_INFO, \"CHIP%i: CAPP ucode lid loaded at %p\\n\",\n+\t chip_id, capp_ucode_info.lid);\n+\n+\tlid = capp_ucode_info.lid;\n+\t/*\n+\t * If lid header is present (on FSP machines), it'll tell us where to\n+\t * find the ucode. Otherwise this is the ucode.\n+\t */\n+\tucode = (struct capp_ucode_lid *)lid;\n+\t/* PHB3: 'CAPPLIDH' in ASCII\n+\t * PHB4: 'CAPPPSLL' in ASCII\n+\t */\n+\tif (be64_to_cpu(lid->eyecatcher) == lidec) {\n+\t\tif (be64_to_cpu(lid->version) != 0x1) {\n+\t\t\tPHBERR(opal_id, chip_id, index,\n+\t\t\t \"capi ucode lid header invalid\\n\");\n+\t\t\treturn OPAL_HARDWARE;\n+\t\t}\n+\t\tucode = (struct capp_ucode_lid *)\n+\t\t\t((char *)ucode + be64_to_cpu(lid->ucode_offset));\n+\t}\n+\n+\t/* 'CAPPULID' in ASCII */\n+\tif ((be64_to_cpu(ucode->eyecatcher) != 0x43415050554C4944) ||\n+\t (ucode->version != 1)) {\n+\t\tPHBERR(opal_id, chip_id, index,\n+\t\t \"CAPP: ucode header invalid\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\n+\toffset = 0;\n+\twhile (offset < be64_to_cpu(ucode->data_size)) {\n+\t\tdata = (struct capp_ucode_data *)\n+\t\t\t((char *)&ucode->data + offset);\n+\t\tchunk_count = be32_to_cpu(data->hdr.chunk_count);\n+\t\toffset += sizeof(struct capp_ucode_data_hdr) + chunk_count * 8;\n+\n+\t\t/* 'CAPPUCOD' in ASCII */\n+\t\tif (be64_to_cpu(data->hdr.eyecatcher) != 0x4341505055434F44) {\n+\t\t\tPHBERR(opal_id, chip_id, index,\n+\t\t\t \"CAPP: ucode data header invalid:%i\\n\",\n+\t\t\t offset);\n+\t\t\treturn OPAL_HARDWARE;\n+\t\t}\n+\n+\t\tswitch (data->hdr.reg) {\n+\t\tcase apc_master_cresp:\n+\t\t\txscom_write(chip_id, apc_master_addr + reg_offset,\n+\t\t\t\t 0);\n+\t\t\taddr = apc_master_write;\n+\t\t\tbreak;\n+\t\tcase apc_master_uop_table:\n+\t\t\txscom_write(chip_id, apc_master_addr + reg_offset,\n+\t\t\t\t 0x180ULL << 52);\n+\t\t\taddr = apc_master_write;\n+\t\t\tbreak;\n+\t\tcase snp_ttype:\n+\t\t\txscom_write(chip_id, snp_array_addr + reg_offset,\n+\t\t\t\t 0x5000ULL << 48);\n+\t\t\taddr = snp_array_write;\n+\t\t\tbreak;\n+\t\tcase snp_uop_table:\n+\t\t\txscom_write(chip_id, snp_array_addr + reg_offset,\n+\t\t\t\t 0x4000ULL << 48);\n+\t\t\taddr = snp_array_write;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tfor (i = 0; i < chunk_count; i++) {\n+\t\t\tval = be64_to_cpu(data->data[i]);\n+\t\t\txscom_write(chip_id, addr + reg_offset, val);\n+\t\t}\n+\t}\n+\n+\tchip->capp_ucode_loaded |= (1 << index);\n+\n+\treturn OPAL_SUCCESS;\n+}\ndiff --git a/hw/phb3.c b/hw/phb3.c\nindex f0e957c..0af20a6 100644\n--- a/hw/phb3.c\n+++ b/hw/phb3.c\n@@ -2417,139 +2417,6 @@ static int64_t phb3_freset(struct pci_slot *slot)\n }\n \n struct lock capi_lock = LOCK_UNLOCKED;\n-static struct {\n-\tuint32_t\t\t\tec_level;\n-\tstruct capp_lid_hdr\t\t*lid;\n-\tsize_t size;\n-\tint load_result;\n-} capp_ucode_info = { 0, NULL, 0, false };\n-\n-#define CAPP_UCODE_MAX_SIZE 0x20000\n-\n-#define CAPP_UCODE_LOADED(chip, p) \\\n-\t ((chip)->capp_ucode_loaded & (1 << (p)->index))\n-\n-static int64_t capp_lid_download(void)\n-{\n-\tint64_t ret;\n-\n-\tif (capp_ucode_info.load_result != OPAL_EMPTY)\n-\t\treturn capp_ucode_info.load_result;\n-\n-\tcapp_ucode_info.load_result = wait_for_resource_loaded(\n-\t\tRESOURCE_ID_CAPP,\n-\t\tcapp_ucode_info.ec_level);\n-\n-\tif (capp_ucode_info.load_result != OPAL_SUCCESS) {\n-\t\tprerror(\"CAPP: Error loading ucode lid. index=%x\\n\",\n-\t\t\tcapp_ucode_info.ec_level);\n-\t\tret = OPAL_RESOURCE;\n-\t\tfree(capp_ucode_info.lid);\n-\t\tcapp_ucode_info.lid = NULL;\n-\t\tgoto end;\n-\t}\n-\n-\tret = OPAL_SUCCESS;\n-end:\n-\treturn ret;\n-}\n-\n-static int64_t capp_load_ucode(struct phb3 *p)\n-{\n-\tstruct proc_chip *chip = get_chip(p->chip_id);\n-\tstruct capp_ucode_lid *ucode;\n-\tstruct capp_ucode_data *data;\n-\tstruct capp_lid_hdr *lid;\n-\tuint64_t rc, val, addr;\n-\tuint32_t chunk_count, offset, reg_offset;\n-\tint i;\n-\n-\tif (CAPP_UCODE_LOADED(chip, p))\n-\t\treturn OPAL_SUCCESS;\n-\n-\t/* Return if PHB not attached to a CAPP unit */\n-\tif (p->index > PHB3_CAPP_MAX_PHB_INDEX(p))\n-\t\treturn OPAL_HARDWARE;\n-\n-\trc = capp_lid_download();\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tprlog(PR_INFO, \"CHIP%i: CAPP ucode lid loaded at %p\\n\",\n-\t p->chip_id, capp_ucode_info.lid);\n-\tlid = capp_ucode_info.lid;\n-\t/*\n-\t * If lid header is present (on FSP machines), it'll tell us where to\n-\t * find the ucode. Otherwise this is the ucode.\n-\t */\n-\tucode = (struct capp_ucode_lid *)lid;\n-\tif (be64_to_cpu(lid->eyecatcher) == 0x434150504c494448) {\n-\t\tif (be64_to_cpu(lid->version) != 0x1) {\n-\t\t\tPHBERR(p, \"capi ucode lid header invalid\\n\");\n-\t\t\treturn OPAL_HARDWARE;\n-\t\t}\n-\t\tucode = (struct capp_ucode_lid *)\n-\t\t\t((char *)ucode + be64_to_cpu(lid->ucode_offset));\n-\t}\n-\n-\tif ((be64_to_cpu(ucode->eyecatcher) != 0x43415050554C4944) ||\n-\t (ucode->version != 1)) {\n-\t\tPHBERR(p, \"CAPP: ucode header invalid\\n\");\n-\t\treturn OPAL_HARDWARE;\n-\t}\n-\n-\treg_offset = PHB3_CAPP_REG_OFFSET(p);\n-\toffset = 0;\n-\twhile (offset < be64_to_cpu(ucode->data_size)) {\n-\t\tdata = (struct capp_ucode_data *)\n-\t\t\t((char *)&ucode->data + offset);\n-\t\tchunk_count = be32_to_cpu(data->hdr.chunk_count);\n-\t\toffset += sizeof(struct capp_ucode_data_hdr) + chunk_count * 8;\n-\n-\t\tif (be64_to_cpu(data->hdr.eyecatcher) != 0x4341505055434F44) {\n-\t\t\tPHBERR(p, \"CAPP: ucode data header invalid:%i\\n\",\n-\t\t\t offset);\n-\t\t\treturn OPAL_HARDWARE;\n-\t\t}\n-\n-\t\tswitch (data->hdr.reg) {\n-\t\tcase apc_master_cresp:\n-\t\t\txscom_write(p->chip_id,\n-\t\t\t\t CAPP_APC_MASTER_ARRAY_ADDR_REG + reg_offset,\n-\t\t\t\t 0);\n-\t\t\taddr = CAPP_APC_MASTER_ARRAY_WRITE_REG;\n-\t\t\tbreak;\n-\t\tcase apc_master_uop_table:\n-\t\t\txscom_write(p->chip_id,\n-\t\t\t\t CAPP_APC_MASTER_ARRAY_ADDR_REG + reg_offset,\n-\t\t\t\t 0x180ULL << 52);\n-\t\t\taddr = CAPP_APC_MASTER_ARRAY_WRITE_REG;\n-\t\t\tbreak;\n-\t\tcase snp_ttype:\n-\t\t\txscom_write(p->chip_id,\n-\t\t\t\t CAPP_SNP_ARRAY_ADDR_REG + reg_offset,\n-\t\t\t\t 0x5000ULL << 48);\n-\t\t\taddr = CAPP_SNP_ARRAY_WRITE_REG;\n-\t\t\tbreak;\n-\t\tcase snp_uop_table:\n-\t\t\txscom_write(p->chip_id,\n-\t\t\t\t CAPP_SNP_ARRAY_ADDR_REG + reg_offset,\n-\t\t\t\t 0x4000ULL << 48);\n-\t\t\taddr = CAPP_SNP_ARRAY_WRITE_REG;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tfor (i = 0; i < chunk_count; i++) {\n-\t\t\tval = be64_to_cpu(data->data[i]);\n-\t\t\txscom_write(p->chip_id, addr + reg_offset, val);\n-\t\t}\n-\t}\n-\n-\tchip->capp_ucode_loaded |= (1 << p->index);\n-\treturn OPAL_SUCCESS;\n-}\n \n static void do_capp_recovery_scoms(struct phb3 *p)\n {\n@@ -2561,7 +2428,13 @@ static void do_capp_recovery_scoms(struct phb3 *p)\n \toffset = PHB3_CAPP_REG_OFFSET(p);\n \t/* disable snoops */\n \txscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0);\n-\tcapp_load_ucode(p);\n+\tcapp_load_ucode(p->index, p->chip_id, PHB3_CAPP_MAX_PHB_INDEX(p),\n+\t\t\t0x434150504c494448, PHB3_CAPP_REG_OFFSET(p),\n+\t\t\tp->phb.opal_id,\n+\t\t\tCAPP_APC_MASTER_ARRAY_ADDR_REG,\n+\t\t\tCAPP_APC_MASTER_ARRAY_WRITE_REG,\n+\t\t\tCAPP_SNP_ARRAY_ADDR_REG,\n+\t\t\tCAPP_SNP_ARRAY_WRITE_REG);\n \t/* clear err rpt reg*/\n \txscom_write(p->chip_id, CAPP_ERR_RPT_CLR + offset, 0);\n \t/* clear capp fir */\n@@ -3596,7 +3469,7 @@ static int64_t phb3_set_capi_mode(struct phb *phb, uint64_t mode,\n \tuint32_t offset;\n \tu8 mask;\n \n-\tif (!CAPP_UCODE_LOADED(chip, p)) {\n+\tif (!capp_ucode_loaded(chip, p->index)) {\n \t\tPHBERR(p, \"CAPP: ucode not loaded\\n\");\n \t\treturn OPAL_RESOURCE;\n \t}\n@@ -4624,7 +4497,13 @@ static void phb3_create(struct dt_node *np)\n \tphb3_init_hw(p, true);\n \n \t/* Load capp microcode into capp unit */\n-\tcapp_load_ucode(p);\n+\tcapp_load_ucode(p->index, p->chip_id, PHB3_CAPP_MAX_PHB_INDEX(p),\n+\t\t\t0x434150504c494448, PHB3_CAPP_REG_OFFSET(p),\n+\t\t\tp->phb.opal_id,\n+\t\t\tCAPP_APC_MASTER_ARRAY_ADDR_REG,\n+\t\t\tCAPP_APC_MASTER_ARRAY_WRITE_REG,\n+\t\t\tCAPP_SNP_ARRAY_ADDR_REG,\n+\t\t\tCAPP_SNP_ARRAY_WRITE_REG);\n \n \t/* Platform additional setup */\n \tif (platform.pci_setup_phb)\n@@ -4817,67 +4696,6 @@ static void phb3_probe_pbcq(struct dt_node *pbcq)\n \tadd_chip_dev_associativity(np);\n }\n \n-int phb3_preload_capp_ucode(void)\n-{\n-\tstruct dt_node *p;\n-\tstruct proc_chip *chip;\n-\tuint32_t index;\n-\tuint64_t rc;\n-\tint ret;\n-\n-\tp = dt_find_compatible_node(dt_root, NULL, \"ibm,power8-pbcq\");\n-\n-\tif (!p) {\n-\t\tprintf(\"CAPI: WARNING: no compat thing found\\n\");\n-\t\treturn OPAL_SUCCESS;\n-\t}\n-\n-\tchip = get_chip(dt_get_chip_id(p));\n-\n-\trc = xscom_read_cfam_chipid(chip->id, &index);\n-\tif (rc) {\n-\t\tprerror(\"CAPP: Error reading cfam chip-id\\n\");\n-\t\tret = OPAL_HARDWARE;\n-\t\treturn ret;\n-\t}\n-\t/* Keep ChipID and Major/Minor EC. Mask out the Location Code. */\n-\tindex = index & 0xf0fff;\n-\n-\t/* Assert that we're preloading */\n-\tassert(capp_ucode_info.lid == NULL);\n-\tcapp_ucode_info.load_result = OPAL_EMPTY;\n-\n-\tcapp_ucode_info.ec_level = index;\n-\n-\t/* Is the ucode preloaded like for BML? */\n-\tif (dt_has_node_property(p, \"ibm,capp-ucode\", NULL)) {\n-\t\tcapp_ucode_info.lid = (struct capp_lid_hdr *)(u64)\n-\t\t\tdt_prop_get_u32(p, \"ibm,capp-ucode\");\n-\t\tret = OPAL_SUCCESS;\n-\t\tgoto end;\n-\t}\n-\t/* If we successfully download the ucode, we leave it around forever */\n-\tcapp_ucode_info.size = CAPP_UCODE_MAX_SIZE;\n-\tcapp_ucode_info.lid = malloc(CAPP_UCODE_MAX_SIZE);\n-\tif (!capp_ucode_info.lid) {\n-\t\tprerror(\"CAPP: Can't allocate space for ucode lid\\n\");\n-\t\tret = OPAL_NO_MEM;\n-\t\tgoto end;\n-\t}\n-\n-\tprintf(\"CAPI: Preloading ucode %x\\n\", capp_ucode_info.ec_level);\n-\n-\tret = start_preload_resource(RESOURCE_ID_CAPP, index,\n-\t\t\t\t capp_ucode_info.lid,\n-\t\t\t\t &capp_ucode_info.size);\n-\n-\tif (ret != OPAL_SUCCESS)\n-\t\tprerror(\"CAPI: Failed to preload resource %d\\n\", ret);\n-\n-end:\n-\treturn ret;\n-}\n-\n void phb3_preload_vpd(void)\n {\n \tconst struct dt_property *prop;\ndiff --git a/hw/phb4.c b/hw/phb4.c\nindex 9858ad8..8b07590 100644\n--- a/hw/phb4.c\n+++ b/hw/phb4.c\n@@ -49,6 +49,7 @@\n #include <phb4.h>\n #include <phb4-regs.h>\n #include <phb4-capp.h>\n+#include <capp.h>\n #include <fsp.h>\n #include <chip.h>\n #include <chiptod.h>\n@@ -2592,6 +2593,11 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode,\n \tuint64_t reg;\n \tuint32_t offset;\n \n+\tif (!capp_ucode_loaded(chip, p->index)) {\n+\t\tPHBERR(p, \"CAPP: ucode not loaded\\n\");\n+\t\treturn OPAL_RESOURCE;\n+\t}\n+\n \tlock(&capi_lock);\n \t/* Only PHB0 and PHB3 have the PHB/CAPP I/F so CAPI Adapters can\n \t * be connected to whether PEC0 or PEC2. Single port CAPI adapter\n@@ -3505,6 +3511,15 @@ static void phb4_create(struct dt_node *np)\n \t/* Get the HW up and running */\n \tphb4_init_hw(p, true);\n \n+\t/* Load capp microcode into capp unit */\n+\tcapp_load_ucode(p->index, p->chip_id, PHB4_CAPP_MAX_PHB_INDEX,\n+\t\t\t0x4341505050534C4C, PHB4_CAPP_REG_OFFSET(p),\n+\t\t\tp->phb.opal_id,\n+\t\t\tCAPP_APC_MASTER_ARRAY_ADDR_REG,\n+\t\t\tCAPP_APC_MASTER_ARRAY_WRITE_REG,\n+\t\t\tCAPP_SNP_ARRAY_ADDR_REG,\n+\t\t\tCAPP_SNP_ARRAY_WRITE_REG);\n+\n \t/* Register all interrupt sources with XIVE */\n \txive_register_hw_source(p->base_msi, p->num_irqs - 8, 16,\n \t\t\t\tp->int_mmio, XIVE_SRC_SHIFT_BUG,\ndiff --git a/include/capp.h b/include/capp.h\nindex d0c28c9..82b08f2 100644\n--- a/include/capp.h\n+++ b/include/capp.h\n@@ -17,8 +17,12 @@\n #ifndef __CAPP_H\n #define __CAPP_H\n \n+/*\n+ * eyecatcher PHB3: 'CAPPLIDH' in ASCII\n+ * eyecatcher PHB4: 'CAPPPSLL' in ASCII\n+ */\n struct capp_lid_hdr {\n-\tbe64 eyecatcher;\t/* 'CAPPLIDH' in ASCII */\n+\tbe64 eyecatcher;\n \tbe64 version;\n \tbe64 lid_no;\n \tbe64 pad;\n@@ -27,7 +31,7 @@ struct capp_lid_hdr {\n };\n \n struct capp_ucode_data_hdr {\n-\tbe64 eyecatcher; \t/* 'CAPPUCOD' in ASCII */\n+\tbe64 eyecatcher;\t/* 'CAPPUCOD' in ASCII */\n \tu8 version;\n \tu8 reg;\n \tu8 reserved[2];\n@@ -47,7 +51,6 @@ struct capp_ucode_lid {\n \tstruct capp_ucode_data data; /* This repeats */\n };\n \n-\n enum capp_reg {\n \tapc_master_cresp\t\t= 0x1,\n \tapc_master_uop_table\t\t= 0x2,\n@@ -62,4 +65,13 @@ enum capp_reg {\n \tapc_master_powerbus_ctrl\t= 0xB\n };\n \n+struct proc_chip;\n+extern bool capp_ucode_loaded(struct proc_chip *chip, unsigned int index);\n+\n+extern int64_t capp_load_ucode(unsigned int index, unsigned int chip_id,\n+\t\t\t unsigned int max_phb_index, u64 lidec,\n+\t\t\t uint32_t reg_offset, uint32_t opal_id,\n+\t\t\t uint64_t apc_master_addr, uint64_t apc_master_write,\n+\t\t\t uint64_t snp_array_addr, uint64_t snp_array_write);\n+\n #endif /* __CAPP_H */\ndiff --git a/include/skiboot.h b/include/skiboot.h\nindex 33447a4..30b8ade 100644\n--- a/include/skiboot.h\n+++ b/include/skiboot.h\n@@ -210,9 +210,8 @@ extern void setup_reset_vector(void);\n extern void probe_p7ioc(void);\n extern void probe_phb3(void);\n extern void probe_phb4(void);\n-extern int phb3_preload_capp_ucode(void);\n extern void phb3_preload_vpd(void);\n-extern int phb4_preload_capp_ucode(void);\n+extern int preload_capp_ucode(void);\n extern void phb4_preload_vpd(void);\n extern void probe_npu(void);\n extern void uart_init(void);\n", "prefixes": [ "4/4" ] }