Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/726444/?format=api
{ "id": 726444, "url": "http://patchwork.ozlabs.org/api/patches/726444/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/1486717462-5016-2-git-send-email-clombard@linux.vnet.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1486717462-5016-2-git-send-email-clombard@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2017-02-10T09:04:19", "name": "[1/4] capi: Externalize capp timebase synchronization", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "173e449dddafa8ac5853b6346773b5d32cb6e328", "submitter": { "id": 67351, "url": "http://patchwork.ozlabs.org/api/people/67351/?format=api", "name": "Christophe Lombard", "email": "clombard@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/1486717462-5016-2-git-send-email-clombard@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/726444/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/726444/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vKTYl06L9z9s2G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Feb 2017 20:05:31 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3vKTYk6PkJzDqJp\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Feb 2017 20:05:30 +1100 (AEDT)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3vKTYF0J34zDqHh\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 20:05:04 +1100 (AEDT)", "from pps.filterd (m0098393.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id\n\tv1A8xOTC003969\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 04:05:03 -0500", "from e06smtp11.uk.ibm.com (e06smtp11.uk.ibm.com [195.75.94.107])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 28gp6ggtuv-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 04:05:02 -0500", "from localhost\n\tby e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <skiboot@lists.ozlabs.org> from <clombard@linux.vnet.ibm.com>;\n\tFri, 10 Feb 2017 09:05:00 -0000", "from d06dlp03.portsmouth.uk.ibm.com (9.149.20.15)\n\tby e06smtp11.uk.ibm.com (192.168.101.141) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tFri, 10 Feb 2017 09:04:57 -0000", "from b06cxnps4075.portsmouth.uk.ibm.com\n\t(d06relay12.portsmouth.uk.ibm.com [9.149.109.197])\n\tby d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id\n\t0FCD51B08023\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 09:07:46 +0000 (GMT)", "from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com\n\t[9.149.105.59])\n\tby b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v1A94QXF60031046; Fri, 10 Feb 2017 09:04:26 GMT", "from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 9D97DA405E;\n\tFri, 10 Feb 2017 09:04:22 +0000 (GMT)", "from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id EBDDAA405B;\n\tFri, 10 Feb 2017 09:04:21 +0000 (GMT)", "from lombard-w520.ibm.com (unknown [9.164.182.111])\n\tby d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tFri, 10 Feb 2017 09:04:21 +0000 (GMT)" ], "From": "Christophe Lombard <clombard@linux.vnet.ibm.com>", "To": "skiboot@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com, imunsie@au1.ibm.com,\n\tandrew.donnellan@au1.ibm.com, christophe_lombard@fr.ibm.com", "Date": "Fri, 10 Feb 2017 10:04:19 +0100", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1486717462-5016-1-git-send-email-clombard@linux.vnet.ibm.com>", "References": "<1486717462-5016-1-git-send-email-clombard@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "17021009-0040-0000-0000-00000344D23C", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17021009-0041-0000-0000-00001EDA6CD2", "Message-Id": "<1486717462-5016-2-git-send-email-clombard@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-02-10_03:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000\n\tdefinitions=main-1702100090", "Subject": "[Skiboot] [PATCH 1/4] capi: Externalize capp timebase\n\tsynchronization", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "Externalize the chiptod code. this code will be common for PHB3 and\nPHB4.\nThe reference to the structure PHB3 is remove and new arguments appear\ndue to specific address registers.\n\nSigned-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>\n---\n hw/chiptod.c | 40 ++++++++++++++++++----------------------\n hw/phb3.c | 2 +-\n include/chiptod.h | 4 ++--\n 3 files changed, 21 insertions(+), 25 deletions(-)", "diff": "diff --git a/hw/chiptod.c b/hw/chiptod.c\nindex 16dd0ae..746876a 100644\n--- a/hw/chiptod.c\n+++ b/hw/chiptod.c\n@@ -21,10 +21,8 @@\n #include <skiboot.h>\n #include <xscom.h>\n #include <pci.h>\n-#include <phb3.h>\n #include <chiptod.h>\n #include <chip.h>\n-#include <capp.h>\n #include <io.h>\n #include <cpu.h>\n #include <timebase.h>\n@@ -1792,7 +1790,7 @@ void chiptod_init(void)\n \n /* CAPP timebase sync */\n \n-static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset)\n+static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset)\n {\n \tuint64_t tfmr;\n \tunsigned long timeout = 0;\n@@ -1808,12 +1806,12 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset)\n \ttfmr |= SPR_TFMR_TFMR_CORRUPT;\n \n \t/* Write CAPP TFMR */\n-\txscom_write(chip_id, CAPP_TFMR + offset, tfmr);\n+\txscom_write(chip_id, tfmr_addr + offset, tfmr);\n \n \t/* We have to write \"Clear TB Errors\" again */\n \ttfmr = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;\n \t/* Write CAPP TFMR */\n-\txscom_write(chip_id, CAPP_TFMR + offset, tfmr);\n+\txscom_write(chip_id, tfmr_addr + offset, tfmr);\n \n \tdo {\n \t\tif (++timeout >= TIMEOUT_LOOPS) {\n@@ -1821,7 +1819,7 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset)\n \t\t\treturn false;\n \t\t}\n \t\t/* Read CAPP TFMR */\n-\t\txscom_read(chip_id, CAPP_TFMR + offset, &tfmr);\n+\t\txscom_read(chip_id, tfmr_addr + offset, &tfmr);\n \t\tif (tfmr & SPR_TFMR_TFMR_CORRUPT) {\n \t\t\tprerror(\"CAPP: TB error reset: corrupt TFMR!\\n\");\n \t\t\treturn false;\n@@ -1830,20 +1828,20 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset)\n \treturn true;\n }\n \n-static bool chiptod_capp_mod_tb(uint32_t chip_id, uint32_t offset)\n+static bool chiptod_capp_mod_tb(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset)\n {\n \tuint64_t timeout = 0;\n \tuint64_t tfmr;\n \n \t/* Switch CAPP timebase to \"Not Set\" state */\n \ttfmr = base_tfmr | SPR_TFMR_LOAD_TOD_MOD;\n-\txscom_write(chip_id, CAPP_TFMR + offset, tfmr);\n+\txscom_write(chip_id, tfmr_addr + offset, tfmr);\n \tdo {\n \t\tif (++timeout >= (TIMEOUT_LOOPS*2)) {\n \t\t\tprerror(\"CAPP: TB \\\"Not Set\\\" timeout\\n\");\n \t\t\treturn false;\n \t\t}\n-\t\txscom_read(chip_id, CAPP_TFMR + offset, &tfmr);\n+\t\txscom_read(chip_id, tfmr_addr + offset, &tfmr);\n \t\tif (tfmr & SPR_TFMR_TFMR_CORRUPT) {\n \t\t\tprerror(\"CAPP: TB \\\"Not Set\\\" TFMR corrupt\\n\");\n \t\t\treturn false;\n@@ -1878,7 +1876,7 @@ static bool chiptod_wait_for_chip_sync(void)\n \treturn true;\n }\n \n-static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset)\n+static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset)\n {\n \tuint64_t tfmr;\n \tuint64_t timeout = 0;\n@@ -1889,7 +1887,7 @@ static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset)\n \t\t\tprerror(\"CAPP: TB Invalid!\\n\");\n \t\t\treturn false;\n \t\t}\n-\t\txscom_read(chip_id, CAPP_TFMR + offset, &tfmr);\n+\t\txscom_read(chip_id, tfmr_addr + offset, &tfmr);\n \t\tif (tfmr & SPR_TFMR_TFMR_CORRUPT) {\n \t\t\tprerror(\"CAPP: TFMR corrupt!\\n\");\n \t\t\treturn false;\n@@ -1898,25 +1896,23 @@ static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset)\n \treturn true;\n }\n \n-bool chiptod_capp_timebase_sync(struct phb3 *p)\n+bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr,\n+\t\t\t\tuint32_t tb_addr, uint32_t offset)\n {\n \tuint64_t tfmr;\n \tuint64_t capp_tb;\n \tint64_t delta;\n-\tuint32_t offset;\n \tunsigned int retry = 0;\n \n-\toffset = PHB3_CAPP_REG_OFFSET(p);\n-\n \t/* Set CAPP TFMR to base tfmr value */\n-\txscom_write(p->chip_id, CAPP_TFMR + offset, base_tfmr);\n+\txscom_write(chip_id, tfmr_addr + offset, base_tfmr);\n \n \t/* Reset CAPP TB errors before attempting the sync */\n-\tif (!chiptod_capp_reset_tb_errors(p->chip_id, offset))\n+\tif (!chiptod_capp_reset_tb_errors(chip_id, tfmr_addr, offset))\n \t\treturn false;\n \n \t/* Switch CAPP TB to \"Not Set\" state */\n-\tif (!chiptod_capp_mod_tb(p->chip_id, offset))\n+\tif (!chiptod_capp_mod_tb(chip_id, tfmr_addr, offset))\n \t\treturn false;\n \n \t/* Sync CAPP TB with core TB, retry while difference > 16usecs */\n@@ -1928,19 +1924,19 @@ bool chiptod_capp_timebase_sync(struct phb3 *p)\n \n \t\t/* Make CAPP ready to get the TB, wait for chip sync */\n \t\ttfmr = base_tfmr | SPR_TFMR_MOVE_CHIP_TOD_TO_TB;\n-\t\txscom_write(p->chip_id, CAPP_TFMR + offset, tfmr);\n+\t\txscom_write(chip_id, tfmr_addr + offset, tfmr);\n \t\tif (!chiptod_wait_for_chip_sync())\n \t\t\treturn false;\n \n \t\t/* Set CAPP TB from core TB */\n-\t\txscom_write(p->chip_id, CAPP_TB + offset, mftb());\n+\t\txscom_write(chip_id, tb_addr + offset, mftb());\n \n \t\t/* Wait for CAPP TFMR tb_valid bit */\n-\t\tif (!chiptod_capp_check_tb_running(p->chip_id, offset))\n+\t\tif (!chiptod_capp_check_tb_running(chip_id, tfmr_addr, offset))\n \t\t\treturn false;\n \n \t\t/* Read CAPP TB, read core TB, compare */\n-\t\txscom_read(p->chip_id, CAPP_TB + offset, &capp_tb);\n+\t\txscom_read(chip_id, tb_addr + offset, &capp_tb);\n \t\tdelta = mftb() - capp_tb;\n \t\tif (delta < 0)\n \t\t\tdelta = -delta;\ndiff --git a/hw/phb3.c b/hw/phb3.c\nindex e246e46..4010739 100644\n--- a/hw/phb3.c\n+++ b/hw/phb3.c\n@@ -3577,7 +3577,7 @@ static int64_t enable_capi_mode(struct phb3 *p, uint64_t pe_number, bool dma_mod\n \n \tphb3_init_capp_regs(p, dma_mode);\n \n-\tif (!chiptod_capp_timebase_sync(p)) {\n+\tif (!chiptod_capp_timebase_sync(p->chip_id, CAPP_TFMR, CAPP_TB, PHB3_CAPP_REG_OFFSET(p))) {\n \t\tPHBERR(p, \"CAPP: Failed to sync timebase\\n\");\n \t\treturn OPAL_HARDWARE;\n \t}\ndiff --git a/include/chiptod.h b/include/chiptod.h\nindex 64df8bc..fd5cd96 100644\n--- a/include/chiptod.h\n+++ b/include/chiptod.h\n@@ -32,7 +32,7 @@ extern bool chiptod_wakeup_resync(void);\n extern int chiptod_recover_tb_errors(void);\n extern void chiptod_reset_tb(void);\n extern bool chiptod_adjust_topology(enum chiptod_topology topo, bool enable);\n-struct phb3;\n-extern bool chiptod_capp_timebase_sync(struct phb3 *p);\n+extern bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr,\n+\t\t\t\t uint32_t tb_addr, uint32_t offset);\n \n #endif /* __CHIPTOD_H */\n", "prefixes": [ "1/4" ] }