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GET /api/patches/726443/?format=api
{ "id": 726443, "url": "http://patchwork.ozlabs.org/api/patches/726443/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/1486717462-5016-4-git-send-email-clombard@linux.vnet.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1486717462-5016-4-git-send-email-clombard@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2017-02-10T09:04:21", "name": "[3/4] capi: Enable capi mode for phb4", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "daf561e9089c30357b2097fa76093a8c02b75299", "submitter": { "id": 67351, "url": "http://patchwork.ozlabs.org/api/people/67351/?format=api", "name": "Christophe Lombard", "email": "clombard@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/1486717462-5016-4-git-send-email-clombard@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/726443/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/726443/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3vKTYc6BrYz9s2G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Feb 2017 20:05:24 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3vKTYc5RClzDqGw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Feb 2017 20:05:24 +1100 (AEDT)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3vKTYD5VhHzDqHd\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 20:05:04 +1100 (AEDT)", "from pps.filterd (m0098419.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id\n\tv1A8x3J5136433\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 04:05:02 -0500", "from e06smtp15.uk.ibm.com (e06smtp15.uk.ibm.com [195.75.94.111])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 28h507km61-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 04:05:02 -0500", "from localhost\n\tby e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <skiboot@lists.ozlabs.org> from <clombard@linux.vnet.ibm.com>;\n\tFri, 10 Feb 2017 09:04:59 -0000", "from d06dlp01.portsmouth.uk.ibm.com (9.149.20.13)\n\tby e06smtp15.uk.ibm.com (192.168.101.145) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tFri, 10 Feb 2017 09:04:56 -0000", "from b06cxnps4074.portsmouth.uk.ibm.com\n\t(d06relay11.portsmouth.uk.ibm.com [9.149.109.196])\n\tby d06dlp01.portsmouth.uk.ibm.com (Postfix) with ESMTP id\n\t2215F17D8042\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Feb 2017 09:08:01 +0000 (GMT)", "from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com\n\t[9.149.105.59])\n\tby b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v1A94Taj66912488; Fri, 10 Feb 2017 09:04:29 GMT", "from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 5C3ADA405D;\n\tFri, 10 Feb 2017 09:04:26 +0000 (GMT)", "from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id A1AAAA4057;\n\tFri, 10 Feb 2017 09:04:25 +0000 (GMT)", "from lombard-w520.ibm.com (unknown [9.164.182.111])\n\tby d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tFri, 10 Feb 2017 09:04:25 +0000 (GMT)" ], "From": "Christophe Lombard <clombard@linux.vnet.ibm.com>", "To": "skiboot@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com, imunsie@au1.ibm.com,\n\tandrew.donnellan@au1.ibm.com, christophe_lombard@fr.ibm.com", "Date": "Fri, 10 Feb 2017 10:04:21 +0100", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1486717462-5016-1-git-send-email-clombard@linux.vnet.ibm.com>", "References": "<1486717462-5016-1-git-send-email-clombard@linux.vnet.ibm.com>", "MIME-Version": "1.0", "X-TM-AS-GCONF": "00", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "17021009-0020-0000-0000-00000303FBDA", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17021009-0021-0000-0000-000040578364", "Message-Id": "<1486717462-5016-4-git-send-email-clombard@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-02-10_03:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000\n\tdefinitions=main-1702100090", "Subject": "[Skiboot] [PATCH 3/4] capi: Enable capi mode for phb4", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "Enable the Coherently attached processor interface. The PHB is used as\na CAPI interface.\nCAPI Adapters can be connected to whether PEC0 or PEC2. Single port\nCAPI adapter can be connected to either PEC0 or PEC2, but Dual-Port\nAdapter can be only connected to PEC2\n CAPP0 attached to PHB0(PEC0 - single port)\n CAPP1 attached to PHB3(PEC2 - single or dual port)\nAs we did for PHB3, a new specific file 'phb4-capp.h' is created to\ncontain the CAPP register definitions.\n\nSigned-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>\n---\n hw/phb4.c | 264 +++++++++++++++++++++++++++++++++++++++++++++++++++-\n include/chip.h | 1 +\n include/phb4-capp.h | 57 ++++++++++++\n include/phb4-regs.h | 8 +-\n 4 files changed, 328 insertions(+), 2 deletions(-)\n create mode 100644 include/phb4-capp.h", "diff": "diff --git a/hw/phb4.c b/hw/phb4.c\nindex 3cdacea..9858ad8 100644\n--- a/hw/phb4.c\n+++ b/hw/phb4.c\n@@ -48,7 +48,7 @@\n #include <affinity.h>\n #include <phb4.h>\n #include <phb4-regs.h>\n-#include <capp.h>\n+#include <phb4-capp.h>\n #include <fsp.h>\n #include <chip.h>\n #include <chiptod.h>\n@@ -1976,6 +1976,8 @@ static int64_t phb4_freset(struct pci_slot *slot)\n \treturn OPAL_HARDWARE;\n }\n \n+extern struct lock capi_lock;\n+\n static int64_t phb4_creset(struct pci_slot *slot)\n {\n \tstruct phb4 *p = phb_to_phb4(slot->phb);\n@@ -2374,6 +2376,265 @@ static int64_t phb4_get_diag_data(struct phb *phb,\n \treturn OPAL_SUCCESS;\n }\n \n+static void phb4_init_capp_regs(struct phb4 *p)\n+{\n+\tuint64_t reg;\n+\tuint32_t offset;\n+\n+\toffset = PHB4_CAPP_REG_OFFSET(p);\n+\n+\t/* enable combined response examination (set by initfile) */\n+\txscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, ®);\n+\treg |= PPC_BIT(0);\n+\txscom_write(p->chip_id, APC_MASTER_PB_CTRL + offset, reg);\n+\n+\t/* Set PHB mode, HPC Dir State and P9 mode */\n+\txscom_write(p->chip_id, APC_MASTER_CAPI_CTRL + offset, 0x1072000000000000);\n+\tPHBINF(p, \"CAPP: port attached\\n\");\n+\n+\t/* should be enabled on LCO shifts only */\n+\t/* xscom_write(p->chip_id, LCO_MASTER_TARGET + offset, 0xFFF2000000000000); */\n+\n+\t/* Set snoop ttype decoding , dir size to 256k */\n+\txscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0xA000000000000000);\n+\n+\t/* Use Read Epsilon Tier2 for all scopes, Address Pipeline Master\n+\t * Wait Count to highest(1023) and Number of rpt_hang.data to 3\n+\t */\n+\txscom_write(p->chip_id, SNOOP_CONTROL + offset, 0x8000000010072000);\n+\n+\t/* TLBI Hang Divider = 1 (initfile). LPC buffers=0. X16 PCIe(14 buffers) */\n+\txscom_write(p->chip_id, TRANSPORT_CONTROL + offset, 0x401404000400000B);\n+\n+\t/* Enable epoch timer */\n+\txscom_write(p->chip_id, EPOCH_RECOVERY_TIMERS_CTRL + offset, 0xC0000000FFF0FFE0);\n+\n+\t/* Deassert TLBI_FENCED and tlbi_psl_is_dead */\n+\txscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, 0);\n+\n+\txscom_write(p->chip_id, FLUSH_SUE_STATE_MAP + offset,\n+\t\t 0x1DCF5F6600000000);\n+\txscom_write(p->chip_id, FLUSH_SUE_UOP1 + offset,\n+\t\t 0xE3105005C8000000);\n+\txscom_write(p->chip_id, APC_FSM_READ_MASK + offset,\n+\t\t 0xFFFFFFFFFFFF0000);\n+\txscom_write(p->chip_id, XPT_FSM_RMM + offset,\n+\t\t 0xFFFFFFFFFFFF0000);\n+}\n+\n+/* override some inits with CAPI defaults */\n+static void phb4_init_capp_errors(struct phb4 *p)\n+{\n+\tout_be64(p->regs + 0x0d30,\t0xdff7ff0bf7ddfff0ull);\n+\tout_be64(p->regs + 0x0db0,\t0xfbffd7bbff7fbfefull);\n+\tout_be64(p->regs + 0x0e30,\t0xfffffeffff7fff57ull);\n+\tout_be64(p->regs + 0x0eb0,\t0xfbaeffaf00000000ull);\n+\tout_be64(p->regs + 0x0cb0,\t0x35777073ff000000ull);\n+}\n+\n+/* Power Bus Common Queue Registers\n+ * All PBCQ and PBAIB registers are accessed via SCOM\n+ * NestBase = 4010C00 for PEC0\n+ * 4011000 for PEC1\n+ * 4011400 for PEC2\n+ *\n+ * Some registers are shared amongst all of the stacks and will only\n+ * have 1 copy. Other registers are implemented one per stack.\n+ * Registers that are duplicated will have an additional offset\n+ * of “StackBase” so that they have a unique address.\n+ * Stackoffset = 00000040 for Stack0\n+ * = 00000080 for Stack1\n+ * = 000000C0 for Stack2\n+ */\n+static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number)\n+{\n+\tuint64_t reg;\n+\t/*uint64_t mbt0, mbt1;*/\n+\tuint32_t offset;\n+\tint i;\n+\n+\txscom_read(p->chip_id, p->pe_xscom + 0x7, ®);\n+\tif (reg & PPC_BIT(0))\n+\t\tPHBDBG(p, \"Already in CAPP mode\\n\");\n+\n+\t/* PEC Phase 3 (PBCQ) registers Init */\n+\t/* poll cqstat */\n+\toffset = 0x40;\n+\tif (p->index > 0 && p->index < 3)\n+\t\toffset = 0x80;\n+\telse if (p->index > 2)\n+\t\toffset = 0xC0;\n+\n+\tfor (i = 0; i < 500000; i++) {\n+\t\txscom_read(p->chip_id, p->pe_xscom + offset + 0xC, ®);\n+\t\tif (!(reg & 0xC000000000000000))\n+\t\t\tbreak;\n+\t\ttime_wait_us(10);\n+\t}\n+\tif (reg & 0xC000000000000000) {\n+\t\tPHBERR(p, \"CAPP: Timeout waiting for pending transaction\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\n+\t/* Enable CAPP Mode , Set 14 CI Store buffers for CAPP,\n+\t * Set 48 Read machines for CAPP)\n+\t */\n+\treg = 0x8000DFFFFFFFFFFFUll;\n+\txscom_write(p->chip_id, p->pe_xscom + 0x7, reg);\n+\n+\t/* PEC Phase 4 (PHB) registers adjustement\n+\t * Bit [0:7] XSL_DSNCTL[capiind]\n+\t * Init_25 - CAPI Compare/Mask\n+\t */\n+\tout_be64(p->regs + PHB_CAPI_CMPM,\n+\t\t 0x0200FE0000000000Ull | PHB_CAPI_CMPM_ENABLE);\n+\n+\tif (!(p->rev == PHB4_REV_NIMBUS_DD10)) {\n+\t\t/* Init_123 : NBW Compare/Mask Register */\n+\t\tout_be64(p->regs + PHB_PBL_NBW_CMPM,\n+\t\t\t 0x0300FF0000000000Ull);\n+\n+\t\t/* Init_24 - ASN Compare/Mask */\n+\t\tout_be64(p->regs + PHB_PBL_ASN_CMPM,\n+\t\t\t 0x0400FF0000000000Ull);\n+\t}\n+\n+\t/* non-translate/50-bit mode */\n+\tout_be64(p->regs + PHB_XLATE_PREFIX, 0x0000000000000000Ull);\n+\n+\t/* set tve no translate mode allow mmio window */\n+\tmemset(p->tve_cache, 0x0, sizeof(p->tve_cache));\n+\n+\t/*\n+\t * In 50-bit non-translate mode, the fields of the TVE are\n+\t * used to perform an address range check. In this mode TCE\n+\t * Table Size(0) must be a '1' (TVE[51] = 1)\n+\t * PCI Addr(49:24) >= TVE[52:53]+TVE[0:23] and\n+\t * PCI Addr(49:24) < TVE[54:55]+TVE[24:47]\n+\t *\n+\t * TVE[51] = 1\n+\t * TVE[56] = 1: 50-bit Non-Translate Mode Enable\n+\t * TVE[0:23] = 0x000000\n+\t * TVE[24:47] = 0xFFFFFF\n+\t *\n+\t * capi dma mode: CAPP DMA mode needs access to all of memory\n+\t * capi mode: Allow address range (bit 14 = 1)\n+\t * 0x0002000000000000: 0x0002FFFFFFFFFFFF\n+\t * TVE[52:53] = '10' and TVE[54:55] = '10'\n+\t *\n+\t * --> we use capi dma mode by default\n+\t */\n+\tp->tve_cache[pe_number * 2] = PPC_BIT(51);\n+\tp->tve_cache[pe_number * 2] |= IODA3_TVT_NON_TRANSLATE_50;\n+\tp->tve_cache[pe_number * 2] |= (0xfffffful << 16);\n+\n+\tphb4_ioda_sel(p, IODA3_TBL_TVT, 0, true);\n+\tfor (i = 0; i < p->tvt_size; i++)\n+\t\tout_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);\n+\n+\t/* set mbt bar to pass capi mmio window. First applied cleared\n+\t * values to HW\n+\t */\n+\tfor (i = 0; i < p->mbt_size; i++) {\n+\t\tp->mbt_cache[i][0] = 0;\n+\t\tp->mbt_cache[i][1] = 0;\n+\t}\n+\tphb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);\n+\tfor (i = 0; i < p->mbt_size; i++) {\n+\t\tout_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);\n+\t\tout_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);\n+\t}\n+\n+\tp->mbt_cache[0][0] = IODA3_MBT0_ENABLE |\n+\t\t\t IODA3_MBT0_TYPE_M64 |\n+\t\tSETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_SINGLE_PE) |\n+\t\tSETFIELD(IODA3_MBT0_MDT_COLUMN, 0ull, 0) |\n+\t\t(p->mm0_base & IODA3_MBT0_BASE_ADDR);\n+\tp->mbt_cache[0][1] = IODA3_MBT1_ENABLE |\n+\t\t((~(p->mm0_size - 1)) & IODA3_MBT1_MASK) |\n+\t\tSETFIELD(IODA3_MBT1_SINGLE_PE_NUM, 0ull, pe_number);\n+\n+\tp->mbt_cache[1][0] = IODA3_MBT0_ENABLE |\n+\t\t\t IODA3_MBT0_TYPE_M64 |\n+\t\tSETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_SINGLE_PE) |\n+\t\tSETFIELD(IODA3_MBT0_MDT_COLUMN, 0ull, 0) |\n+\t\t(0x0002000000000000ULL & IODA3_MBT0_BASE_ADDR);\n+\tp->mbt_cache[1][1] = IODA3_MBT1_ENABLE |\n+\t\t(0x00ff000000000000ULL & IODA3_MBT1_MASK) |\n+\t\tSETFIELD(IODA3_MBT1_SINGLE_PE_NUM, 0ull, pe_number);\n+\n+\tphb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);\n+\tfor (i = 0; i < p->mbt_size; i++) {\n+\t\tout_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);\n+\t\tout_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);\n+\t}\n+\n+\tphb4_init_capp_errors(p);\n+\n+\tphb4_init_capp_regs(p);\n+\n+\tif (!(p->rev == PHB4_REV_NIMBUS_DD10)) {\n+\t\tif (!chiptod_capp_timebase_sync(p->chip_id, CAPP_TFMR,\n+\t\t\t\t\t\tCAPP_TB,\n+\t\t\t\t\t\tPHB4_CAPP_REG_OFFSET(p))) {\n+\t\t\tPHBERR(p, \"CAPP: Failed to sync timebase\\n\");\n+\t\t\treturn OPAL_HARDWARE;\n+\t\t}\n+\t}\n+\treturn OPAL_SUCCESS;\n+}\n+\n+static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode,\n+\t\t\t\t uint64_t pe_number)\n+{\n+\tstruct phb4 *p = phb_to_phb4(phb);\n+\tstruct proc_chip *chip = get_chip(p->chip_id);\n+\tuint64_t reg;\n+\tuint32_t offset;\n+\n+\tlock(&capi_lock);\n+\t/* Only PHB0 and PHB3 have the PHB/CAPP I/F so CAPI Adapters can\n+\t * be connected to whether PEC0 or PEC2. Single port CAPI adapter\n+\t * can be connected to either PEC0 or PEC2, but Dual-Port Adapter\n+\t * can be only connected to PEC2\n+\t */\n+\tchip->capp_phb4_attached_mask |= 1 << p->index;\n+\tunlock(&capi_lock);\n+\n+\toffset = PHB4_CAPP_REG_OFFSET(p);\n+\txscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®);\n+\tif ((reg & PPC_BIT(5))) {\n+\t\tPHBERR(p, \"CAPP: recovery failed (%016llx)\\n\", reg);\n+\t\treturn OPAL_HARDWARE;\n+\t} else if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) {\n+\t\tPHBDBG(p, \"CAPP: recovery in progress\\n\");\n+\t\treturn OPAL_BUSY;\n+\t}\n+\n+\tswitch (mode) {\n+\tcase OPAL_PHB_CAPI_MODE_PCIE:\n+\t\treturn OPAL_UNSUPPORTED;\n+\n+\tcase OPAL_PHB_CAPI_MODE_CAPI:\n+\t\treturn enable_capi_mode(p, pe_number);\n+\n+\tcase OPAL_PHB_CAPI_MODE_SNOOP_OFF:\n+\t\txscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset,\n+\t\t\t 0x0000000000000000);\n+\t\treturn OPAL_SUCCESS;\n+\n+\tcase OPAL_PHB_CAPI_MODE_SNOOP_ON:\n+\t\txscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL + offset,\n+\t\t\t 0x0000000000000000);\n+\t\treg = 0xA1F0000000000000;\n+\t\txscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, reg);\n+\n+\t\treturn OPAL_SUCCESS;\n+\t}\n+\n+\treturn OPAL_UNSUPPORTED;\n+}\n+\n static const struct phb_ops phb4_ops = {\n \t.cfg_read8\t\t= phb4_pcicfg_read8,\n \t.cfg_read16\t\t= phb4_pcicfg_read16,\n@@ -2405,6 +2666,7 @@ static const struct phb_ops phb4_ops = {\n \t.get_diag_data\t\t= NULL,\n \t.get_diag_data2\t\t= phb4_get_diag_data,\n \t.tce_kill\t\t= phb4_tce_kill,\n+\t.set_capi_mode\t\t= phb4_set_capi_mode,\n };\n \n static void phb4_init_ioda3(struct phb4 *p)\ndiff --git a/include/chip.h b/include/chip.h\nindex 588db9f..a4a1e1e 100644\n--- a/include/chip.h\n+++ b/include/chip.h\n@@ -190,6 +190,7 @@ struct proc_chip {\n \n \t/* Must hold capi_lock to change */\n \tuint8_t\t\t\tcapp_phb3_attached_mask;\n+\tuint8_t\t\t\tcapp_phb4_attached_mask;\n \tuint8_t\t\t\tcapp_ucode_loaded;\n \n \t/* Used by hw/centaur.c */\ndiff --git a/include/phb4-capp.h b/include/phb4-capp.h\nnew file mode 100644\nindex 0000000..a42383e\n--- /dev/null\n+++ b/include/phb4-capp.h\n@@ -0,0 +1,57 @@\n+/* Copyright 2013-2017 IBM Corp.\n+ *\n+ * Licensed under the Apache License, Version 2.0 (the \"License\");\n+ * you may not use this file except in compliance with the License.\n+ * You may obtain a copy of the License at\n+ *\n+ *\thttp://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS,\n+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or\n+ * implied.\n+ * See the License for the specific language governing permissions and\n+ * limitations under the License.\n+ */\n+\n+#ifndef __PHB4_CAPP_H\n+#define __PHB4_CAPP_H\n+\n+#define CAPP_SNP_ARRAY_WRITE_REG\t\t0x2010841 /* S2 */\n+#define CAPP_SNP_ARRAY_ADDR_REG \t\t0x2010828\n+#define CAPP_APC_MASTER_ARRAY_ADDR_REG\t\t0x201082A\n+#define CAPP_APC_MASTER_ARRAY_WRITE_REG \t0x2010842 /* S2 */\n+\n+#define APC_MASTER_PB_CTRL\t\t\t0x2010818\n+#define APC_MASTER_CAPI_CTRL\t\t\t0x2010819\n+#define LCO_MASTER_TARGET\t\t\t0x2010821\n+#define EPOCH_RECOVERY_TIMERS_CTRL\t\t0x201082C\n+#define SNOOP_CAPI_CONFIG\t\t\t0x201081A\n+#define SNOOP_CONTROL\t\t\t\t0x201081B\n+#define TRANSPORT_CONTROL\t\t\t0x201081C\n+#define CAPP_TB \t\t\t\t0x2010826\n+#define CAPP_TFMR\t\t\t\t0x2010827\n+#define CAPP_ERR_STATUS_CTRL\t\t\t0x201080E\n+#define FLUSH_SUE_STATE_MAP\t\t\t0x201080F\n+#define FLUSH_CPIG_STATE_MAP\t\t\t0x2010820 /* TBD */\n+#define FLUSH_SUE_UOP1\t\t\t\t0x2010843 /* S2 */\n+#define APC_FSM_READ_MASK\t\t\t0x2010823\n+#define XPT_FSM_RMM\t\t\t\t0x2010831\n+\n+/* CAPP0 attached to PHB0(PEC0 - single port)\n+ * CAPP1 attached to PHB3(PEC2 - single or dual port)\n+ *\n+ * SCOM address Base (Ring = ‘0010’b)\n+ * CAPP Unit Satellite SCOM address Base\n+ * CAPP 0 S1 (sat = ‘0000’b) x02010800\n+ * CAPP 0 S2 (sat = ‘0001’b) x02010840\n+ * CAPP 1 S1 (sat = ‘0000’b) x04010800\n+ * CAPP 1 S2 (sat = ‘0001’b) x04010840\n+ */\n+#define CAPP1_REG_OFFSET 0x2000000\n+\n+#define PHB4_CAPP_MAX_PHB_INDEX 3\n+\n+#define PHB4_CAPP_REG_OFFSET(p) ((p)->index == 0 ? 0x0 : CAPP1_REG_OFFSET)\n+\n+#endif /* __PHB4_CAPP_H */\ndiff --git a/include/phb4-regs.h b/include/phb4-regs.h\nindex 48953e4..4cb0b26 100644\n--- a/include/phb4-regs.h\n+++ b/include/phb4-regs.h\n@@ -71,8 +71,12 @@\n #define PHB_PEST_BAR\t\t\t0x1a8\n #define PHB_PEST_BAR_ENABLE\t\tPPC_BIT(0)\n #define PHB_PEST_BASE_ADDRESS\t\tPPC_BITMASK(8,51)\n+#define PHB_PBL_ASN_CMPM\t\t0x1C0\n+#define PHB_CAPI_ASN_ENABLE\t\tPPC_BIT(63)\n+#define PHB_CAPI_CMPM\t\t\t0x1C8\n+#define PHB_CAPI_CMPM_ENABLE\t\tPPC_BIT(63)\n #define PHB_M64_UPPER_BITS\t\t0x1f0\n-#define PHB_INTREP_TIMER\t\t0x1f8\n+#define PHB_XLATE_PREFIX\t\t0x1f8\n #define PHB_DMARD_SYNC\t\t\t0x200\n #define PHB_DMARD_SYNC_START\t\tPPC_BIT(0)\n #define PHB_DMARD_SYNC_COMPLETE\tPPC_BIT(1)\n@@ -157,6 +161,8 @@\n #define PHB_RC_CONFIG_BASE\t\t0x1000\n \n #define PHB_PBL_TIMEOUT_CTRL\t\t0x1810\n+#define PHB_PBL_NBW_CMPM\t\t0x1830\n+#define PHB_CAPI_NBW_ENABLE\t\tPPC_BIT(63)\n \n // FIXME add more here\n #define PHB_PCIE_SCR\t\t\t0x1A00\n", "prefixes": [ "3/4" ] }