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GET /api/patches/723989/?format=api
{ "id": 723989, "url": "http://patchwork.ozlabs.org/api/patches/723989/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170204023258.10080-1-wenyou.yang@atmel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170204023258.10080-1-wenyou.yang@atmel.com>", "list_archive_url": null, "date": "2017-02-04T02:32:58", "name": "[U-Boot] nand: atmel: add drvice tree support and dm gpio APIs", "commit_ref": null, "pull_url": null, "state": "deferred", "archived": false, "hash": "0b6a9c96d91ebbcc3ba4114cfc59ab55636cc916", "submitter": { "id": 16102, "url": "http://patchwork.ozlabs.org/api/people/16102/?format=api", "name": "Wenyou Yang", "email": "wenyou.yang@atmel.com" }, "delegate": { "id": 6342, "url": "http://patchwork.ozlabs.org/api/users/6342/?format=api", "username": "abiessmann", "first_name": "Andreas", "last_name": "Bießmann", "email": "andreas.biessmann@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170204023258.10080-1-wenyou.yang@atmel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/723989/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/723989/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 3vFdFG2BlDz9s7G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 4 Feb 2017 13:37:53 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 764A2A7701;\n\tSat, 4 Feb 2017 03:37:47 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id rA-Qd_8ClGht; Sat, 4 Feb 2017 03:37:47 +0100 (CET)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 7F1F24A99B;\n\tSat, 4 Feb 2017 03:37:46 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id AB2464A99B\n\tfor <u-boot@lists.denx.de>; Sat, 4 Feb 2017 03:37:40 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 3cFuVyHEnyrj for <u-boot@lists.denx.de>;\n\tSat, 4 Feb 2017 03:37:40 +0100 (CET)", "from eusmtp01.atmel.com (eusmtp01.atmel.com [212.144.249.242])\n\tby theia.denx.de (Postfix) with ESMTPS id 57AEB4A08A\n\tfor <u-boot@lists.denx.de>; Sat, 4 Feb 2017 03:37:36 +0100 (CET)", "from apsmtp01.atmel.com (10.168.254.30) by eusmtp01.atmel.com\n\t(10.145.145.30) with Microsoft SMTP Server id 14.3.235.1;\n\tSat, 4 Feb 2017 03:37:28 +0100", "from shaarm01.corp.atmel.com (10.168.254.13) by\n\tapsmtp01.corp.atmel.com (10.168.254.30) with Microsoft SMTP Server id\n\t14.3.235.1; Sat, 4 Feb 2017 10:40:46 +0800" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Wenyou Yang <wenyou.yang@atmel.com>", "To": "U-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Sat, 4 Feb 2017 10:32:58 +0800", "Message-ID": "<20170204023258.10080-1-wenyou.yang@atmel.com>", "X-Mailer": "git-send-email 2.11.0", "MIME-Version": "1.0", "Cc": "Scott Wood <scottwood@freescale.com>", "Subject": "[U-Boot] [PATCH] nand: atmel: add drvice tree support and dm gpio\n\tAPIs", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "In order to use the driver model gpio APIs, add the device tree\nsupport.\n\nSigned-off-by: Wenyou Yang <wenyou.yang@atmel.com>\n---\n\n drivers/mtd/nand/atmel_nand.c | 143 ++++++++++++++++++++++++++++++++++--------\n include/fdtdec.h | 1 +\n lib/fdtdec.c | 1 +\n 3 files changed, 119 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c\nindex 8669432deb..87ff5c2eb4 100644\n--- a/drivers/mtd/nand/atmel_nand.c\n+++ b/drivers/mtd/nand/atmel_nand.c\n@@ -14,29 +14,34 @@\n #include <common.h>\n #include <asm/gpio.h>\n #include <asm/arch/gpio.h>\n+#ifdef CONFIG_DM_GPIO\n+#include <asm/gpio.h>\n+#endif\n \n+#include <fdtdec.h>\n #include <malloc.h>\n #include <nand.h>\n #include <watchdog.h>\n #include <linux/mtd/nand_ecc.h>\n \n-#ifdef CONFIG_ATMEL_NAND_HWECC\n-\n-/* Register access macros */\n-#define ecc_readl(add, reg)\t\t\t\t\\\n-\treadl(add + ATMEL_ECC_##reg)\n-#define ecc_writel(add, reg, value)\t\t\t\\\n-\twritel((value), add + ATMEL_ECC_##reg)\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+struct atmel_nand_data {\n+\tstruct gpio_desc enable_pin;\t/* chip enable */\n+\tstruct gpio_desc det_pin;\t/* card detect */\n+\tstruct gpio_desc rdy_pin;\t/* ready/busy */\n+\tu8\t\tale;\t/* address line number connected to ALE */\n+\tu8\t\tcle;\t/* address line number connected to CLE */\n+\tu8\t\tbus_width_16;\t/* buswidth is 16 bit */\n+\tu8\t\tecc_mode;\t/* ecc mode */\n+\tu8\t\ton_flash_bbt;\t/* bbt on flash */\n+};\n \n-#include \"atmel_nand_ecc.h\"\t/* Hardware ECC registers */\n+struct atmel_nand_host {\n+\tvoid __iomem\t\t*io_base;\n+\tstruct atmel_nand_data\tboard;\n \n #ifdef CONFIG_ATMEL_NAND_HW_PMECC\n-\n-#ifdef CONFIG_SPL_BUILD\n-#undef CONFIG_SYS_NAND_ONFI_DETECTION\n-#endif\n-\n-struct atmel_nand_host {\n \tstruct pmecc_regs __iomem *pmecc;\n \tstruct pmecc_errloc_regs __iomem *pmerrloc;\n \tvoid __iomem\t\t*pmecc_rom_base;\n@@ -63,9 +68,26 @@ struct atmel_nand_host {\n \tint\t*pmecc_mu;\n \tint\t*pmecc_dmu;\n \tint\t*pmecc_delta;\n+#endif\n };\n \n-static struct atmel_nand_host pmecc_host;\n+static struct atmel_nand_host nand_host;\n+#ifdef CONFIG_ATMEL_NAND_HWECC\n+\n+/* Register access macros */\n+#define ecc_readl(add, reg)\t\t\t\t\\\n+\treadl(add + ATMEL_ECC_##reg)\n+#define ecc_writel(add, reg, value)\t\t\t\\\n+\twritel((value), add + ATMEL_ECC_##reg)\n+\n+#include \"atmel_nand_ecc.h\"\t/* Hardware ECC registers */\n+\n+#ifdef CONFIG_ATMEL_NAND_HW_PMECC\n+\n+#ifdef CONFIG_SPL_BUILD\n+#undef CONFIG_SYS_NAND_ONFI_DETECTION\n+#endif\n+\n static struct nand_ecclayout atmel_pmecc_oobinfo;\n \n /*\n@@ -805,12 +827,9 @@ static uint16_t *create_lookup_table(int sector_size)\n static int atmel_pmecc_nand_init_params(struct nand_chip *nand,\n \t\tstruct mtd_info *mtd)\n {\n-\tstruct atmel_nand_host *host;\n+\tstruct atmel_nand_host *host = nand_get_controller_data(nand);\n \tint cap, sector_size;\n \n-\thost = &pmecc_host;\n-\tnand_set_controller_data(nand, host);\n-\n \tnand->ecc.mode = NAND_ECC_HW;\n \tnand->ecc.calculate = NULL;\n \tnand->ecc.correct = NULL;\n@@ -1207,12 +1226,24 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)\n #endif /* CONFIG_ATMEL_NAND_HWECC */\n \n static void at91_nand_hwcontrol(struct mtd_info *mtd,\n-\t\t\t\t\t int cmd, unsigned int ctrl)\n+\t\t\t\tint cmd, unsigned int ctrl)\n {\n \tstruct nand_chip *this = mtd_to_nand(mtd);\n+#if CONFIG_IS_ENABLED(OF_CONTROL)\n+\tstruct atmel_nand_host *host = nand_get_controller_data(this);\n+#endif\n \n \tif (ctrl & NAND_CTRL_CHANGE) {\n-\t\tulong IO_ADDR_W = (ulong) this->IO_ADDR_W;\n+\t\tulong IO_ADDR_W = (ulong)this->IO_ADDR_W;\n+#if CONFIG_IS_ENABLED(OF_CONTROL)\n+\t\tIO_ADDR_W &= ~((1 << host->board.ale)\n+\t\t\t | (1 << host->board.cle));\n+\n+\t\tif (ctrl & NAND_CLE)\n+\t\t\tIO_ADDR_W |= (1 << host->board.cle);\n+\t\tif (ctrl & NAND_ALE)\n+\t\t\tIO_ADDR_W |= (1 << host->board.ale);\n+#else\n \t\tIO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE\n \t\t\t | CONFIG_SYS_NAND_MASK_CLE);\n \n@@ -1220,10 +1251,18 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,\n \t\t\tIO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;\n \t\tif (ctrl & NAND_ALE)\n \t\t\tIO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;\n+#endif\n \n+#ifdef CONFIG_DM_GPIO\n+\t\tif (dm_gpio_is_valid(&host->board.enable_pin))\n+\t\t\tdm_gpio_set_value(&host->board.enable_pin,\n+\t\t\t\t\t !(ctrl & NAND_NCE));\n+#else\n #ifdef CONFIG_SYS_NAND_ENABLE_PIN\n \t\tgpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));\n #endif\n+#endif\n+\n \t\tthis->IO_ADDR_W = (void *) IO_ADDR_W;\n \t}\n \n@@ -1231,12 +1270,24 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,\n \t\twriteb(cmd, this->IO_ADDR_W);\n }\n \n-#ifdef CONFIG_SYS_NAND_READY_PIN\n static int at91_nand_ready(struct mtd_info *mtd)\n {\n+#ifdef CONFIG_DM_GPIO\n+\tstruct nand_chip *nand_chip = mtd_to_nand(mtd);\n+\tstruct atmel_nand_host *host = nand_get_controller_data(nand_chip);\n+\n+\tif (dm_gpio_is_valid(&host->board.rdy_pin))\n+\t\treturn dm_gpio_get_value(&host->board.rdy_pin);\n+\n+\treturn 0;\n+#else\n+#ifdef CONFIG_SYS_NAND_READY_PIN\n \treturn gpio_get_value(CONFIG_SYS_NAND_READY_PIN);\n-}\n+#else\n+\treturn 0;\n #endif\n+#endif\n+}\n \n #ifdef CONFIG_SPL_BUILD\n /* The following code is for SPL */\n@@ -1419,6 +1470,10 @@ int at91_nand_wait_ready(struct mtd_info *mtd)\n int board_nand_init(struct nand_chip *nand)\n {\n \tint ret = 0;\n+\tstruct atmel_nand_host *host;\n+\n+\thost = &nand_host;\n+\tnand_set_controller_data(nand, host);\n \n \tnand->ecc.mode = NAND_ECC_SOFT;\n #ifdef CONFIG_SYS_NAND_DBW_16\n@@ -1486,9 +1541,45 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)\n \tint ret;\n \tstruct nand_chip *nand = &nand_chip[devnum];\n \tstruct mtd_info *mtd = nand_to_mtd(nand);\n+\tstruct atmel_nand_host *host;\n+\n+\thost = &nand_host;\n+\tnand_set_controller_data(nand, host);\n+\n+#if CONFIG_IS_ENABLED(OF_CONTROL)\n+\tstruct atmel_nand_data *board;\n+\tint node;\n+\n+\tboard = &host->board;\n+\tnode = fdtdec_next_compatible(gd->fdt_blob, 0,\n+\t\t\t\t COMPAT_ATMEL_NAND);\n+\tif (node < 0)\n+\t\treturn -1;\n+\n+\tnand->IO_ADDR_R = (void __iomem *)\n+\t\t\t fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,\n+\t\t\t\t\t\t\t node, \"reg\",\n+\t\t\t\t\t\t\t 0, NULL, true);\n+\tnand->IO_ADDR_W = nand->IO_ADDR_R;\n \n-\tnand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;\n+\tboard->ale = fdtdec_get_uint(gd->fdt_blob, node,\n+\t\t\t\t \"atmel,nand-addr-offset\", 21);\n \n+\tboard->cle = fdtdec_get_uint(gd->fdt_blob, node,\n+\t\t\t\t \"atmel,nand-cmd-offset\", 22);\n+\n+\tgpio_request_by_name_nodev(gd->fdt_blob, node, \"gpios\", 0,\n+\t\t\t\t &board->rdy_pin, GPIOD_IS_IN);\n+\n+\tgpio_request_by_name_nodev(gd->fdt_blob, node, \"gpios\", 1,\n+\t\t\t\t &board->enable_pin, GPIOD_IS_OUT);\n+\n+\tgpio_request_by_name_nodev(gd->fdt_blob, node, \"gpios\", 2,\n+\t\t\t\t &board->det_pin, GPIOD_IS_IN);\n+#else\n+\tnand->IO_ADDR_R = (void __iomem *)base_addr;\n+\tnand->IO_ADDR_W = (void __iomem *)base_addr;\n+#endif\n #ifdef CONFIG_NAND_ECC_BCH\n \tnand->ecc.mode = NAND_ECC_SOFT_BCH;\n #else\n@@ -1498,9 +1589,9 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)\n \tnand->options = NAND_BUSWIDTH_16;\n #endif\n \tnand->cmd_ctrl = at91_nand_hwcontrol;\n-#ifdef CONFIG_SYS_NAND_READY_PIN\n+\n \tnand->dev_ready = at91_nand_ready;\n-#endif\n+\n \tnand->chip_delay = 75;\n #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT\n \tnand->bbt_options |= NAND_BBT_USE_FLASH;\ndiff --git a/include/fdtdec.h b/include/fdtdec.h\nindex d074478f14..eacf251d63 100644\n--- a/include/fdtdec.h\n+++ b/include/fdtdec.h\n@@ -155,6 +155,7 @@ enum fdt_compat_id {\n \tCOMPAT_INTEL_BAYTRAIL_FSP_MDP,\t/* Intel FSP memory-down params */\n \tCOMPAT_INTEL_IVYBRIDGE_FSP,\t/* Intel Ivy Bridge FSP */\n \tCOMPAT_SUNXI_NAND,\t\t/* SUNXI NAND controller */\n+\tCOMPAT_ATMEL_NAND,\t\t/* Atmel NAND controller */\n \n \tCOMPAT_COUNT,\n };\ndiff --git a/lib/fdtdec.c b/lib/fdtdec.c\nindex 81f47ef2c7..a89e8272e1 100644\n--- a/lib/fdtdec.c\n+++ b/lib/fdtdec.c\n@@ -66,6 +66,7 @@ static const char * const compat_names[COMPAT_COUNT] = {\n \tCOMPAT(INTEL_BAYTRAIL_FSP_MDP, \"intel,baytrail-fsp-mdp\"),\n \tCOMPAT(INTEL_IVYBRIDGE_FSP, \"intel,ivybridge-fsp\"),\n \tCOMPAT(COMPAT_SUNXI_NAND, \"allwinner,sun4i-a10-nand\"),\n+\tCOMPAT(COMPAT_ATMEL_NAND, \"atmel,at91rm9200-nand\"),\n };\n \n const char *fdtdec_get_compatible(enum fdt_compat_id id)\n", "prefixes": [ "U-Boot" ] }