Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/702568/?format=api
{ "id": 702568, "url": "http://patchwork.ozlabs.org/api/patches/702568/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1480913809-23817-1-git-send-email-qiang.zhao@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1480913809-23817-1-git-send-email-qiang.zhao@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1480913809-23817-1-git-send-email-qiang.zhao@nxp.com/", "date": "2016-12-05T04:56:49", "name": "[v9] QE: remove PPCisms for QE", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "82ddc1f2bfb5ab4e3ae0e8f70a525867ed400eab", "submitter": { "id": 68014, "url": "http://patchwork.ozlabs.org/api/people/68014/?format=api", "name": "Qiang Zhao", "email": "qiang.zhao@nxp.com" }, "delegate": { "id": 1707, "url": "http://patchwork.ozlabs.org/api/users/1707/?format=api", "username": "scottwood", "first_name": "Scott", "last_name": "Wood", "email": "scottwood@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1480913809-23817-1-git-send-email-qiang.zhao@nxp.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/702568/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/702568/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3tXCXR6LKxz9t1B\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 5 Dec 2016 16:11:19 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3tXCXR5VGDzDw5G\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 5 Dec 2016 16:11:19 +1100 (AEDT)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam02on0056.outbound.protection.outlook.com [104.47.36.56])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3tXCWF5yFMzDvkB\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tMon, 5 Dec 2016 16:10:17 +1100 (AEDT)", "from BY2PR03CA039.namprd03.prod.outlook.com (10.141.249.12) by\n\tBY2PR0301MB0742.namprd03.prod.outlook.com (10.160.63.20) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.747.13; Mon, 5 Dec 2016 05:10:12 +0000", "from BL2FFO11FD033.protection.gbl (2a01:111:f400:7c09::181) by\n\tBY2PR03CA039.outlook.office365.com (2a01:111:e400:2c5d::12) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.761.9 via\n\tFrontend Transport; Mon, 5 Dec 2016 05:10:12 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBL2FFO11FD033.mail.protection.outlook.com (10.173.161.129) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.1.734.4 via Frontend Transport; Mon, 5 Dec 2016 05:10:11 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tuB55A7uU001435; Sun, 4 Dec 2016 22:10:07 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com;\n\tnxp.com; \n\tdkim=none (message not signed) header.d=none;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "X-IncomingTopHeaderMarker": "OriginalChecksum:; UpperCasedChecksum:;\n\tSizeAsReceived:612; Count:8", "From": "Zhao Qiang <qiang.zhao@nxp.com>", "To": "<oss@buserror.net>", "Subject": "[PATCH v9] QE: remove PPCisms for QE", "Date": "Mon, 5 Dec 2016 12:56:49 +0800", "Message-ID": "<1480913809-23817-1-git-send-email-qiang.zhao@nxp.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-IncomingHeaderCount": "8", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131253882115280306;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(7916002)(2980300002)(1109001)(1110001)(336004)(339900001)(199003)(189002)(39450400002)(39380400001)(39400400001)(39410400001)(38730400001)(85426001)(626004)(92566002)(68736007)(48376002)(50466002)(189998001)(39860400001)(39840400001)(39850400001)(77096006)(36756003)(86362001)(2906002)(305945005)(8936002)(105606002)(356003)(6666003)(6916009)(106466001)(110136003)(97736004)(8666005)(7846002)(47776003)(4326007)(81156014)(81166006)(2351001)(5660300001)(33646002)(50226002)(8676002)(5003940100001)(50986999)(104016004)(7059030);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR0301MB0742;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; ", "X-Microsoft-Exchange-Diagnostics": [ "1; BL2FFO11FD033;\n\t1:nq4i+IkP2ev5F6hzVbD55KKAi1QH1M9tDg5SgrEtn543oxNElDHElUeHAlVy6Hw+ulqFEN4X+lMeKrdFccxGzf7inFpk/gm6iUV3nAzroe8HDUlvS8fsvfb7vFcex/XGu3taMKbrPMoEF4ZOGrqyijcbDyynq9zw62w2WZMYri7+0+P7oQQxFptflR7a6vBLopOIgsE8hXmSqTjhA4YVQQSjV1iX6PEiaVMysP0Y4w7ECbl41zVsifKkKneaHiL8Nzv3pV4dsClYbXIn74JjSZQLrX9gMv0lTUfMQ3P0KZrBMRScOfWyQMDwkYZ83l6jw4hD8KMslNrp333XM6DcijCrH1gna+mgZhc9hL+yVjD4dOC6ZEP9XHBBgTgTZtLI4VIpiQd/2pMz8nEG8ASUEUfT41VHURivuUczW+S1lMdIpNGKrPVip9R6GvW9F+tDJUW18+mgRNnPnk3Q2c2YWo8GRcMrLwgL6438A0jviLHqkYeOpoh+4pKfUDxjD9nOvHiu8sWKMM11EoSSP/P/HtEF+B0Tq2sJWtvulDCq7nYm/0p+apcIho5C1iyGJYesNAY5MJgrGm+HAGBC7THhGhaCnYUrXz3BgI2e5ywVHAbn7+glC49i64B9phtzu6kidU3MRqCzfX3pfNoQG/dkoBTIih63ayj6MNdkXFaOIZw5uCRHH2pp2C+FULLxF3c1mvT3rg2WYxIjCh9d6DrJOcCo8E+mije22HUiQ/xNUbs=", "1; BY2PR0301MB0742;\n\t3:4pyfTmTcuT763kfmdcQakSOkNNii41U/GTIv6cBUbvTZxK75uNXWWcorTdGLIBXEHrWkG7291gDMOei+6SjA028tm7sAhw0Io3kpG66MGrFn/oBrRdqS5/BGfMxjFQD2U7ZD/ODfXNtiyq7cH75D1iKPiCAE/6S84KNpTpOyTumimfhw0lNY06XUtaAzBEWfMmEBP5u+dYbfYxijgVMeIe/TsrGt84/lsYPwO6CMxzb4ShA4zBJksF7Qo+yG7OpbNXsKH0+pAoNNuT0LmiXxI2EW5ZWu1zWIzHq6hiuKIhmo/csz7Q9VL1p+McaaFkRdZA6RsyPbsbr1LJfnYAeXseWPpMx21Oz+/dtPYklJpeBh8CA4wLIfajhNEURvs7e+", "1; BY2PR0301MB0742;\n\t25:mMMCYxvl9B0IbAPoGLDLjzkhqsZSgZ+F4WC1j9sph2a6fp0K3EacIrmdAg2KvjXjzRHxd+LJ0VTJ0P3ds9/zgV/QNIXKXrbCit6jGrOC0M+8AlAWBItBVJpIAYXsIBMxDORPwKre6WrYFQOcTTLv/duYWfCfcQR1U/kbHh5nHv8oRtQ8npCnxHT2h5aDX3bGIsd4ByMhBboH/ozm42/lU57lYi5VNhrE8imnV52KtFHeJ59LWkWmBIcPihYmj3ewmLI+rzHCQ7FOPOuRsaNdV/X3lntgJjG8U3e7JFFCb1YHdeoqd2y8Tgj2Vio9nb3Er1EqWKwsih3YWgdMoj326Nhhy5v6fAyXTSZ+ZD++1TQCX/GBIvoDj1RnCIMQKYhFe4h1/p9OthgqQsY8+xo8/927NTQtoxTgk3ZoMeqVH1slwTBxX8/aseRnWNpTnGt6J1kGODKid/XyXwIG7X/XCppzFBJTODuECpsLbcEgRvVHqIotGat59LQxMVWjb8d9zKc68NQidv+O2lCeXUiwf+Bhk1v5kYMUZSaNAVdfRo/d4ZDiFmunUVWQ83+bUpYGP1GxjnjDvsLNC7VP+gElJnMhal/Q36rDL6xYNWB5st97jJDhL+x7OeqjxxCq/tzPJzuam7zx2ulxGaT/wykTd9IboYOKe5LOzWaqsJNAz4FXsocqd1gKB8KTUS4s5+ZroEzK/u33NBEl5nI5XdH6hVxCHCDBIvZ5Gqi5R0cTUO+gyWAViq6YKm+mmbg320mC", "1; BY2PR0301MB0742;\n\t31:IghRzj9l6xtVFC8JxbZ7E8ftKUc6HXPihJhnHcakeFr7z0HyMEk7zzYaCJUKGI6+szchR8r79L28u3yDJ5HdwxtgEPCUrKH8kMRPL4ABqZMBmX5GT7VpOQjSng1WfALTjDLtRWnBwCOJsnhPSBbvWirHLHlVfWelmK+KrsI+XOutYXNpt/W6GhKqrYqDbGfg7d5NdTDmxyBGvLF9ZUWXzN+KXtlKJK7iqhIQq5G2pIGKhNI4uW3+ClZD0riNCr9kecU04vHzw6xzVWtkJJaZozzfJI12s+29gC0Y3T5Uew4=", "1; BY2PR0301MB0742;\n\t4:0/kDr//YftujgtoQCxbO71ImHeLsmDNb/5VK1Xj83vPV77VvXxAgSqJ8LMARVtjLQ4qL/+zLpPgZ3jMFSy+gGPSDD1dgj/6FJkUR/ZG9suT8DaJUk1h4otbL+MUBmre9Na4Ti/h3wZSBjA8q0VF3H8DBdZg9TBSuHZ4/EzCZvqYwJA2AP3Fzcc5NNuwOD8hjq/Vfcym20pdMPrB20r/tgNPfLs83eWkUdLQdAYbOol07d5UdWQS917kqxmaOJXRgbpMABpBy+7QbDZmsdppyxrykYLWqyf/GFAA8nRnVLw+74NbGKerN2BUnQlCSp0sMWGdOC/ke75wLAeVyjQZ9hKPj34RZ4RgUYcNOGaXo8MBqNFeVwIW13RZiG4YhIt/iVnxO66AixVerGKq4unwvx4F5igavtFCqDSvkH+cEuXIUusFOIY6NzB3C6aPfk7lIR3BrmZmBBuwR7uGL2ZqcYqeNe6vf6B4MZ9P4No7whXnfbbhkcAF0j0N/fB3fKAX3hIkPiYcJsnc6YvT+rDJ+tg4H+d/eKYEsPj5o2ESTH9dPERKQ+GWW3CJ+9rvNIgjPP0jC+FHov/NgywKiR6ptC1nNUGEXsQqgpFwXHfPo0M0UJyRJNdD/+o3DuH1FCpx5ad8E/GeBChOAj+8wpSNu89m5GFD9/q/yw27IpRkc8qwFBoMeNmV8lzrYonzqpM1b4kDaJH03Ziv4knGgVeddtiakU8C6nIMEeW0d0pldGgxZHmNGmkWqrRAWay2mlAlu", "=?us-ascii?Q?1; BY2PR0301MB0742;\n\t23:w4ITSU4oY2gsmw1BsfY2dD91G13hvCh3pr+Zawq?=\n\t=?us-ascii?Q?uMUPRkVKAO8QobEE53hmLO0kJEyo4O45QH0ZRSHJvGBlHGTYYc+H9N94ipH4?=\n\t=?us-ascii?Q?yvU63gLvFCtJn0oj0YyznzRB7RSv4h9CCtNeAia+gDZaARFnIwiUtoWiV855?=\n\t=?us-ascii?Q?Neu8e7sDsq1nGn8kfS7MnbAZ45hI2nVAYePSmjsbZlrMpTn1BXgZrRjiRm8g?=\n\t=?us-ascii?Q?zeffSCqvQ4AoWmFGxfvcR0M+9zrGjB3p1Y20f8xd6I+txGif/5cPKvoGeXb4?=\n\t=?us-ascii?Q?bB9mA6wOLptg3Y4C8l6A0dx6RPm0sPVCz7TY2wXCuDcr9E0QyFDR7QgmoUXE?=\n\t=?us-ascii?Q?WWM2TbtEQWn9b09RX4oyIXFIt3HbUZ7Hr4NNd0nuDaksDykTFDAAywrb9h50?=\n\t=?us-ascii?Q?ezFUPGbW6d07GfJa56VIuRP00321X3Srja+4cLuaf2AqkJImCiIQuUT+Qupc?=\n\t=?us-ascii?Q?A9lLST9zZVj9voppulDSvGgSHOFNkW8tqcC/y3z1wuIuga7trcU0IaOFq7Jp?=\n\t=?us-ascii?Q?1LQNiZ+buAiGmW3f3dMkK4c3CqSa7dW4Q6kwmP8lbvioyulINSG+b3BNj5+2?=\n\t=?us-ascii?Q?jjm6QT4nHyALGOyKrgqqTNfWKI33fqdO7jLbDzU0wKn6Q5vwQnyITz4MniNq?=\n\t=?us-ascii?Q?VQYQFFO26cZe/mzB1MktWIH7+fxEIF1op2YpyVryrNzxuxtuHWkwGQlpPwan?=\n\t=?us-ascii?Q?tyewlZ3QzBUyMZEE06N/TH58ist3B6EMZbwrXxawxV1jCb4l3rrXoYNwIY+O?=\n\t=?us-ascii?Q?7ZT28RH9tTWe5db1U/gpbEo+a7wBzs07LQkZJogqnV/mU54DB7JEd+O/cZ0t?=\n\t=?us-ascii?Q?4S6706zidbXqakx01jgwXr5ep/APjUpisFTw9NsDJVWutldudGMLPk8mZGlG?=\n\t=?us-ascii?Q?HoJ5P0DwotqSmGau0msVOPx7JeMUfZLH1joem7hBVevKzkGWOBTcHtX3cgsA?=\n\t=?us-ascii?Q?2yDHwD/OnixbLVC04O2eigm+PgSytzvbMFyhLUTB+MQDmWesH/W1VpjrNWJJ?=\n\t=?us-ascii?Q?CPTN86i20LgbTYcnQj2m90dXLv+Obnhi81fNdj87SZtROInew061HOahcaWA?=\n\t=?us-ascii?Q?K/Qii3vzpvwcKBV6Od2jIQjVAiIt0sN6qHSr1DvzdPs40wiE+JGRoxiJc+79?=\n\t=?us-ascii?Q?4gKldRFnnKblNWtaiAZgJ3aPk7WixvFhS27HDrX2WRZYWT2dsPr2BjAaCfnX?=\n\t=?us-ascii?Q?LiQicdzn89vpBvwsvUkKyMAz12oO+EHrzBHGGrEGC2zzARvKziGw/SP9eU7g?=\n\t=?us-ascii?Q?RMQAXBXsmebTmiD2pOEU=3D?=", "1; BY2PR0301MB0742;\n\t6:KINEOU5JeXyL15gByrPR0RA/g8whOx4grTItKcXOqOpyG3UL3z9zDmAAkuvZtnLKa3CDFzyiT9s/aujIt0kUEOI5/lRmSz8GLgYpmAa2P+q02HhFMoQRHXBNlAPC/RMXeF/FMzbb+kKPavzbEluXGpSku1aKDQRzOVGIsFzNIaAYwbbxPYQzNSLnhb6/yDFqcL9iCnxOWtDuLLWYq/HO9ZYjBuHnyZdrA38NBDKh59jE6cARqP50Q/1/HmP9ulGwlZxJRhuQYlu5lDvGVk1fSKELT657r78/6mjsx4taL65Unghn+zpETyFWHzsFDxksWuqXhNIwMXcwlCLlkAV9BUBVLFw+BD7pH0DCCAbufkQzLwCcBhvNTuEOSwzclu3/HQ9vmnrKprCp0tVzoDALhcO3BfImlO+/0XBuZGNpJH7mVJi/Pcy9sMDpJvwr0Abq;\n\t5:oFFPOVpYOYpoEm0ac6jn4cGx6p1bMfBpwM0Pr/sn7YlmxOrkqCF+wejWYv41Q0qlwsvLZEJgCHbYT2jVWsjo1o5piC4DSxlNlXKfhbFImMtRKreWg5PSujpDJ63MV5mEp+QG/hRQ5cBRYT/jXpebMFlEzhIbIB7zBcVzvYwFhIyk1cmdJ1IiEzQC6CQJaZUD;\n\t24:3HxPqqASo0HxRegMqAFDHidhiS9eAzPiPNkhQ2hWWk3mtAi+1t7hLqaxfonFGZeRbAnb4Mx9ajtoLLtNLYtpMg8RKiGDXjrPUPMeyJZsu9o=", "1; BY2PR0301MB0742;\n\t7:/9rVmqaG0VqrZhkVhY/j7E1Ty7lpbHM4I4XUuSK2PmIhgSJCustCIKpIQuaS6KgG0dP2UM0fqZCxogmmLCkH1CLlJQbOiw8UHymWGgXSfYfak94CvAgESjTQRrSW+jtS9TeSwO85tlBhdk27LndvfYgBSHoIkt5DWeUa+WYgP9iQuKSuqffmzLaXHp8q+wAXm0nkjIxMfkaPhBvi4xfl0KpfjqiEMhK0jVZYPpuJP+p2fkEBh74WBKicDWKhU+b4mlNtNzlr6XDN7oXDtX3PoRcxo227YxXF7Cx2S3zvLH1379IF7F+KjsJs+oTjXBaex3AhJTiMzZCETLBhRTajEjLa7hNAncD9MQ3w4+yrQmFFKecA/5aby6XjyBkI9adH5ruCra3F0cvv5Fe70kcnCShn9JXTnssQ/CluPgMxMUQN8GfGJg9pR3YJPKZ7P5mqw5bs28FZHrOmMaAIT2FUrw==" ], "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MS-Office365-Filtering-Correlation-Id": "452c2f00-0e6e-427c-42b2-08d41cccfd43", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0; RULEID:(22001);\n\tSRVR:BY2PR0301MB0742; ", "X-Microsoft-Antispam-PRVS": "<BY2PR0301MB07427AE5B05C1CD0DEDF4E4691830@BY2PR0301MB0742.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197);", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(6095060)(601004)(2401047)(13017025)(13023025)(13015025)(13024025)(13018025)(8121501046)(5005006)(10201501046)(3002001)(6055026)(6096035)(20161123565025)(20161123561025)(20161123559025)(20161123556025)(20161123563025);\n\tSRVR:BY2PR0301MB0742; BCL:0; PCL:0; RULEID:(400006);\n\tSRVR:BY2PR0301MB0742; ", "X-Forefront-PRVS": "0147E151B5", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Dec 2016 05:10:11.2316\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY2PR0301MB0742", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "balbi@kernel.org, gregkh@linuxfoundation.org, xiaobo.xie@nxp.com,\n\tlinux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,\n\tZhao Qiang <qiang.zhao@nxp.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "QE was supported on PowerPC, and dependent on PPC,\nNow it is supported on other platforms. so remove PPCisms.\n\nSigned-off-by: Zhao Qiang <qiang.zhao@nxp.com>\n---\nChanges for v2:\n\t- na\nChanges for v3:\n\t- add NO_IRQ\nChanges for v4:\n\t- modify spin_event_timeout to opencoded timeout loop\n\t- remove NO_IRQ\n\t- modify virq_to_hw to opencoed code\nChanges for v5:\n\t- modify commit msg\n\t- modify depends of QUICC_ENGINE\n\t- add kerneldoc header for qe_issue_cmd\nChanges for v6:\n\t- add dependency on FSL_SOC and PPC32 for drivers\n\t depending on QUICC_ENGING but not available on ARM\nChanges for v7:\n\t- split qeic part to another patch\n\t- rebase\nChanges for v8:\n\t- include <asm/cpm.h> in ucc_uart\nChanges for v9:\n\t- fix cast warning\n\n drivers/net/ethernet/freescale/Kconfig | 10 ++---\n drivers/soc/fsl/qe/Kconfig | 2 +-\n drivers/soc/fsl/qe/qe.c | 80 ++++++++++++++++++++--------------\n drivers/soc/fsl/qe/qe_io.c | 42 ++++++++----------\n drivers/soc/fsl/qe/qe_tdm.c | 8 ++--\n drivers/soc/fsl/qe/ucc.c | 10 ++---\n drivers/soc/fsl/qe/ucc_fast.c | 74 ++++++++++++++++---------------\n drivers/tty/serial/Kconfig | 2 +-\n drivers/tty/serial/ucc_uart.c | 1 +\n drivers/usb/gadget/udc/Kconfig | 2 +-\n drivers/usb/host/Kconfig | 2 +-\n include/soc/fsl/qe/qe.h | 1 -\n 12 files changed, 123 insertions(+), 111 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig\nindex d1ca45f..6677aff 100644\n--- a/drivers/net/ethernet/freescale/Kconfig\n+++ b/drivers/net/ethernet/freescale/Kconfig\n@@ -5,10 +5,10 @@\n config NET_VENDOR_FREESCALE\n \tbool \"Freescale devices\"\n \tdefault y\n-\tdepends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \\\n-\t\t M523x || M527x || M5272 || M528x || M520x || M532x || \\\n-\t\t ARCH_MXC || ARCH_MXS || (PPC_MPC52xx && PPC_BESTCOMM) || \\\n-\t\t ARCH_LAYERSCAPE\n+\tdepends on FSL_SOC || (QUICC_ENGINE && PPC32) || CPM1 || CPM2 || \\\n+\t\t PPC_MPC512x || M523x || M527x || M5272 || M528x || M520x || \\\n+\t\t M532x || ARCH_MXC || ARCH_MXS || \\\n+\t\t (PPC_MPC52xx && PPC_BESTCOMM) || ARCH_LAYERSCAPE\n \t---help---\n \t If you have a network (Ethernet) card belonging to this class, say Y.\n \n@@ -72,7 +72,7 @@ config FSL_XGMAC_MDIO\n \n config UCC_GETH\n \ttristate \"Freescale QE Gigabit Ethernet\"\n-\tdepends on QUICC_ENGINE\n+\tdepends on QUICC_ENGINE && FSL_SOC && PPC32\n \tselect FSL_PQ_MDIO\n \tselect PHYLIB\n \t---help---\ndiff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig\nindex 73a2e08..b26b643 100644\n--- a/drivers/soc/fsl/qe/Kconfig\n+++ b/drivers/soc/fsl/qe/Kconfig\n@@ -4,7 +4,7 @@\n \n config QUICC_ENGINE\n \tbool \"Freescale QUICC Engine (QE) Support\"\n-\tdepends on FSL_SOC && PPC32\n+\tdepends on OF && HAS_IOMEM\n \tselect GENERIC_ALLOCATOR\n \tselect CRC32\n \thelp\ndiff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c\nindex 2707a82..2b53e85 100644\n--- a/drivers/soc/fsl/qe/qe.c\n+++ b/drivers/soc/fsl/qe/qe.c\n@@ -33,8 +33,6 @@\n #include <asm/pgtable.h>\n #include <soc/fsl/qe/immap_qe.h>\n #include <soc/fsl/qe/qe.h>\n-#include <asm/prom.h>\n-#include <asm/rheap.h>\n \n static void qe_snums_init(void);\n static int qe_sdma_init(void);\n@@ -109,15 +107,27 @@ void qe_reset(void)\n \t\tpanic(\"sdma init failed!\");\n }\n \n+/* issue commands to QE, return 0 on success while -EIO on error\n+ *\n+ * @cmd: the command code, should be QE_INIT_TX_RX, QE_STOP_TX and so on\n+ * @device: which sub-block will run the command, QE_CR_SUBBLOCK_UCCFAST1 - 8\n+ * , QE_CR_SUBBLOCK_UCCSLOW1 - 8, QE_CR_SUBBLOCK_MCC1 - 3,\n+ * QE_CR_SUBBLOCK_IDMA1 - 4 and such on.\n+ * @mcn_protocol: specifies mode for the command for non-MCC, should be\n+ * QE_CR_PROTOCOL_HDLC_TRANSPARENT, QE_CR_PROTOCOL_QMC, QE_CR_PROTOCOL_UART\n+ * and such on.\n+ * @cmd_input: command related data.\n+ */\n int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)\n {\n \tunsigned long flags;\n \tu8 mcn_shift = 0, dev_shift = 0;\n-\tu32 ret;\n+\tint ret;\n+\tint i;\n \n \tspin_lock_irqsave(&qe_lock, flags);\n \tif (cmd == QE_RESET) {\n-\t\tout_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));\n+\t\tiowrite32be((cmd | QE_CR_FLG), &qe_immr->cp.cecr);\n \t} else {\n \t\tif (cmd == QE_ASSIGN_PAGE) {\n \t\t\t/* Here device is the SNUM, not sub-block */\n@@ -134,20 +144,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)\n \t\t\t\tmcn_shift = QE_CR_MCN_NORMAL_SHIFT;\n \t\t}\n \n-\t\tout_be32(&qe_immr->cp.cecdr, cmd_input);\n-\t\tout_be32(&qe_immr->cp.cecr,\n-\t\t\t (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)\n-\t\t\t mcn_protocol << mcn_shift));\n+\t\tiowrite32be(cmd_input, &qe_immr->cp.cecdr);\n+\t\tiowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) |\n+\t\t\t (u32)mcn_protocol << mcn_shift), &qe_immr->cp.cecr);\n \t}\n \n \t/* wait for the QE_CR_FLG to clear */\n-\tret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,\n-\t\t\t 100, 0);\n+\tret = -EIO;\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif ((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0) {\n+\t\t\tret = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tudelay(1);\n+\t}\n+\n \t/* On timeout (e.g. failure), the expression will be false (ret == 0),\n \t otherwise it will be true (ret == 1). */\n \tspin_unlock_irqrestore(&qe_lock, flags);\n \n-\treturn ret == 1;\n+\treturn ret;\n }\n EXPORT_SYMBOL(qe_issue_cmd);\n \n@@ -166,8 +182,8 @@ static unsigned int brg_clk = 0;\n unsigned int qe_get_brg_clk(void)\n {\n \tstruct device_node *qe;\n-\tint size;\n-\tconst u32 *prop;\n+\tu32 val;\n+\tint ret;\n \n \tif (brg_clk)\n \t\treturn brg_clk;\n@@ -179,9 +195,9 @@ unsigned int qe_get_brg_clk(void)\n \t\t\treturn brg_clk;\n \t}\n \n-\tprop = of_get_property(qe, \"brg-frequency\", &size);\n-\tif (prop && size == sizeof(*prop))\n-\t\tbrg_clk = *prop;\n+\tret = of_property_read_u32(qe, \"brg-frequency\", &val);\n+\tif (!ret)\n+\t\tbrg_clk = val;\n \n \tof_node_put(qe);\n \n@@ -221,7 +237,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)\n \ttempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |\n \t\tQE_BRGC_ENABLE | div16;\n \n-\tout_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);\n+\tiowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);\n \n \treturn 0;\n }\n@@ -355,9 +371,9 @@ static int qe_sdma_init(void)\n \t\t\treturn -ENOMEM;\n \t}\n \n-\tout_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);\n- \tout_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |\n- \t\t\t\t\t(0x1 << QE_SDMR_CEN_SHIFT)));\n+\tiowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK, &sdma->sdebcr);\n+\tiowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),\n+\t\t &sdma->sdmr);\n \n \treturn 0;\n }\n@@ -395,14 +411,14 @@ static void qe_upload_microcode(const void *base,\n \t\t\t\"uploading microcode '%s'\\n\", ucode->id);\n \n \t/* Use auto-increment */\n-\tout_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |\n-\t\tQE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);\n+\tiowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE |\n+\t\t QE_IRAM_IADD_BADDR, &qe_immr->iram.iadd);\n \n \tfor (i = 0; i < be32_to_cpu(ucode->count); i++)\n-\t\tout_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));\n+\t\tiowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);\n \t\n \t/* Set I-RAM Ready Register */\n-\tout_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));\n+\tiowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);\n }\n \n /*\n@@ -487,7 +503,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)\n \t * If the microcode calls for it, split the I-RAM.\n \t */\n \tif (!firmware->split)\n-\t\tsetbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);\n+\t\tqe_setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);\n \n \tif (firmware->soc.model)\n \t\tprintk(KERN_INFO\n@@ -521,11 +537,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)\n \t\t\tu32 trap = be32_to_cpu(ucode->traps[j]);\n \n \t\t\tif (trap)\n-\t\t\t\tout_be32(&qe_immr->rsp[i].tibcr[j], trap);\n+\t\t\t\tiowrite32be(trap, &qe_immr->rsp[i].tibcr[j]);\n \t\t}\n \n \t\t/* Enable traps */\n-\t\tout_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));\n+\t\tiowrite32be(be32_to_cpu(ucode->eccr), &qe_immr->rsp[i].eccr);\n \t}\n \n \tqe_firmware_uploaded = 1;\n@@ -644,9 +660,9 @@ EXPORT_SYMBOL(qe_get_num_of_risc);\n unsigned int qe_get_num_of_snums(void)\n {\n \tstruct device_node *qe;\n-\tint size;\n \tunsigned int num_of_snums;\n-\tconst u32 *prop;\n+\tu32 val;\n+\tint ret;\n \n \tnum_of_snums = 28; /* The default number of snum for threads is 28 */\n \tqe = of_find_compatible_node(NULL, NULL, \"fsl,qe\");\n@@ -660,9 +676,9 @@ unsigned int qe_get_num_of_snums(void)\n \t\t\treturn num_of_snums;\n \t}\n \n-\tprop = of_get_property(qe, \"fsl,qe-num-snums\", &size);\n-\tif (prop && size == sizeof(*prop)) {\n-\t\tnum_of_snums = *prop;\n+\tret = of_property_read_u32(qe, \"fsl,qe-num-snums\", &val);\n+\tif (!ret) {\n+\t\tnum_of_snums = val;\n \t\tif ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {\n \t\t\t/* No QE ever has fewer than 28 SNUMs */\n \t\t\tpr_err(\"QE: number of snum is invalid\\n\");\ndiff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c\nindex 7ae59ab..8966e8b 100644\n--- a/drivers/soc/fsl/qe/qe_io.c\n+++ b/drivers/soc/fsl/qe/qe_io.c\n@@ -22,8 +22,6 @@\n \n #include <asm/io.h>\n #include <soc/fsl/qe/qe.h>\n-#include <asm/prom.h>\n-#include <sysdev/fsl_soc.h>\n \n #undef DEBUG\n \n@@ -61,16 +59,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,\n \tpin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));\n \n \t/* Set open drain, if required */\n-\ttmp_val = in_be32(&par_io->cpodr);\n+\ttmp_val = ioread32be(&par_io->cpodr);\n \tif (open_drain)\n-\t\tout_be32(&par_io->cpodr, pin_mask1bit | tmp_val);\n+\t\tiowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);\n \telse\n-\t\tout_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);\n+\t\tiowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);\n \n \t/* define direction */\n \ttmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?\n-\t\tin_be32(&par_io->cpdir2) :\n-\t\tin_be32(&par_io->cpdir1);\n+\t\tioread32be(&par_io->cpdir2) :\n+\t\tioread32be(&par_io->cpdir1);\n \n \t/* get all bits mask for 2 bit per port */\n \tpin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -\n@@ -82,34 +80,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,\n \n \t/* clear and set 2 bits mask */\n \tif (pin > (QE_PIO_PINS / 2) - 1) {\n-\t\tout_be32(&par_io->cpdir2,\n-\t\t\t ~pin_mask2bits & tmp_val);\n+\t\tiowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);\n \t\ttmp_val &= ~pin_mask2bits;\n-\t\tout_be32(&par_io->cpdir2, new_mask2bits | tmp_val);\n+\t\tiowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);\n \t} else {\n-\t\tout_be32(&par_io->cpdir1,\n-\t\t\t ~pin_mask2bits & tmp_val);\n+\t\tiowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);\n \t\ttmp_val &= ~pin_mask2bits;\n-\t\tout_be32(&par_io->cpdir1, new_mask2bits | tmp_val);\n+\t\tiowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);\n \t}\n \t/* define pin assignment */\n \ttmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?\n-\t\tin_be32(&par_io->cppar2) :\n-\t\tin_be32(&par_io->cppar1);\n+\t\tioread32be(&par_io->cppar2) :\n+\t\tioread32be(&par_io->cppar1);\n \n \tnew_mask2bits = (u32) (assignment << (QE_PIO_PINS -\n \t\t\t(pin % (QE_PIO_PINS / 2) + 1) * 2));\n \t/* clear and set 2 bits mask */\n \tif (pin > (QE_PIO_PINS / 2) - 1) {\n-\t\tout_be32(&par_io->cppar2,\n-\t\t\t ~pin_mask2bits & tmp_val);\n+\t\tiowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);\n \t\ttmp_val &= ~pin_mask2bits;\n-\t\tout_be32(&par_io->cppar2, new_mask2bits | tmp_val);\n+\t\tiowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);\n \t} else {\n-\t\tout_be32(&par_io->cppar1,\n-\t\t\t ~pin_mask2bits & tmp_val);\n+\t\tiowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);\n \t\ttmp_val &= ~pin_mask2bits;\n-\t\tout_be32(&par_io->cppar1, new_mask2bits | tmp_val);\n+\t\tiowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);\n \t}\n }\n EXPORT_SYMBOL(__par_io_config_pin);\n@@ -137,12 +131,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)\n \t/* calculate pin location */\n \tpin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));\n \n-\ttmp_val = in_be32(&par_io[port].cpdata);\n+\ttmp_val = ioread32be(&par_io[port].cpdata);\n \n \tif (val == 0)\t\t/* clear */\n-\t\tout_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);\n+\t\tiowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);\n \telse\t\t\t/* set */\n-\t\tout_be32(&par_io[port].cpdata, pin_mask | tmp_val);\n+\t\tiowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);\n \n \treturn 0;\n }\ndiff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c\nindex a1048b4..818e679 100644\n--- a/drivers/soc/fsl/qe/qe_tdm.c\n+++ b/drivers/soc/fsl/qe/qe_tdm.c\n@@ -227,10 +227,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)\n \t\t\t\t &siram[siram_entry_id * 32 + 0x200 + i]);\n \t}\n \n-\tsetbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],\n-\t\t SIR_LAST);\n-\tsetbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],\n-\t\t SIR_LAST);\n+\tqe_setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],\n+\t\t SIR_LAST);\n+\tqe_setbits16(&siram[(siram_entry_id * 32) + 0x200 +\n+\t\t (utdm->num_of_ts - 1)], SIR_LAST);\n \n \t/* Set SIxMR register */\n \tsixmr = SIMR_SAD(siram_entry_id);\ndiff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c\nindex c646d87..bc64b83 100644\n--- a/drivers/soc/fsl/qe/ucc.c\n+++ b/drivers/soc/fsl/qe/ucc.c\n@@ -39,7 +39,7 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)\n \t\treturn -EINVAL;\n \n \tspin_lock_irqsave(&cmxgcr_lock, flags);\n-\tclrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,\n+\tqe_clrsetbits32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,\n \t\tucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);\n \tspin_unlock_irqrestore(&cmxgcr_lock, flags);\n \n@@ -84,7 +84,7 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)\n \t\treturn -EINVAL;\n \t}\n \n-\tclrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,\n+\tqe_clrsetbits8(guemr, UCC_GUEMR_MODE_MASK,\n \t\tUCC_GUEMR_SET_RESERVED3 | speed);\n \n \treturn 0;\n@@ -113,9 +113,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)\n \tget_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);\n \n \tif (set)\n-\t\tsetbits32(cmxucr, mask << shift);\n+\t\tqe_setbits32(cmxucr, mask << shift);\n \telse\n-\t\tclrbits32(cmxucr, mask << shift);\n+\t\tqe_clrbits32(cmxucr, mask << shift);\n \n \treturn 0;\n }\n@@ -211,7 +211,7 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,\n \tif (mode == COMM_DIR_RX)\n \t\tshift += 4;\n \n-\tclrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,\n+\tqe_clrsetbits32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,\n \t\tclock_bits << shift);\n \n \treturn 0;\ndiff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c\nindex 83d8d16..5115e93 100644\n--- a/drivers/soc/fsl/qe/ucc_fast.c\n+++ b/drivers/soc/fsl/qe/ucc_fast.c\n@@ -33,41 +33,41 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)\n \tprintk(KERN_INFO \"Base address: 0x%p\\n\", uccf->uf_regs);\n \n \tprintk(KERN_INFO \"gumr : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));\n+\t &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));\n \tprintk(KERN_INFO \"upsmr : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));\n+\t\t &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));\n \tprintk(KERN_INFO \"utodr : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));\n+\t\t &uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));\n \tprintk(KERN_INFO \"udsr : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));\n+\t\t &uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));\n \tprintk(KERN_INFO \"ucce : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));\n+\t\t &uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));\n \tprintk(KERN_INFO \"uccm : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));\n+\t\t &uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));\n \tprintk(KERN_INFO \"uccs : addr=0x%p, val=0x%02x\\n\",\n-\t\t &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));\n+\t\t &uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));\n \tprintk(KERN_INFO \"urfb : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));\n+\t\t &uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));\n \tprintk(KERN_INFO \"urfs : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));\n+\t\t &uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));\n \tprintk(KERN_INFO \"urfet : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));\n+\t\t &uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));\n \tprintk(KERN_INFO \"urfset: addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));\n+\t\t &uccf->uf_regs->urfset, ioread16be(&uccf->uf_regs->urfset));\n \tprintk(KERN_INFO \"utfb : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));\n+\t\t &uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));\n \tprintk(KERN_INFO \"utfs : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));\n+\t\t &uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));\n \tprintk(KERN_INFO \"utfet : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));\n+\t\t &uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));\n \tprintk(KERN_INFO \"utftt : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));\n+\t\t &uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));\n \tprintk(KERN_INFO \"utpt : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));\n+\t\t &uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));\n \tprintk(KERN_INFO \"urtry : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));\n+\t\t &uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));\n \tprintk(KERN_INFO \"guemr : addr=0x%p, val=0x%02x\\n\",\n-\t\t &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));\n+\t\t &uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));\n }\n EXPORT_SYMBOL(ucc_fast_dump_regs);\n \n@@ -89,7 +89,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);\n \n void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)\n {\n-\tout_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);\n+\tiowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);\n }\n EXPORT_SYMBOL(ucc_fast_transmit_on_demand);\n \n@@ -101,7 +101,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)\n \tuf_regs = uccf->uf_regs;\n \n \t/* Enable reception and/or transmission on this UCC. */\n-\tgumr = in_be32(&uf_regs->gumr);\n+\tgumr = ioread32be(&uf_regs->gumr);\n \tif (mode & COMM_DIR_TX) {\n \t\tgumr |= UCC_FAST_GUMR_ENT;\n \t\tuccf->enabled_tx = 1;\n@@ -110,7 +110,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)\n \t\tgumr |= UCC_FAST_GUMR_ENR;\n \t\tuccf->enabled_rx = 1;\n \t}\n-\tout_be32(&uf_regs->gumr, gumr);\n+\tiowrite32be(gumr, &uf_regs->gumr);\n }\n EXPORT_SYMBOL(ucc_fast_enable);\n \n@@ -122,7 +122,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)\n \tuf_regs = uccf->uf_regs;\n \n \t/* Disable reception and/or transmission on this UCC. */\n-\tgumr = in_be32(&uf_regs->gumr);\n+\tgumr = ioread32be(&uf_regs->gumr);\n \tif (mode & COMM_DIR_TX) {\n \t\tgumr &= ~UCC_FAST_GUMR_ENT;\n \t\tuccf->enabled_tx = 0;\n@@ -131,7 +131,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)\n \t\tgumr &= ~UCC_FAST_GUMR_ENR;\n \t\tuccf->enabled_rx = 0;\n \t}\n-\tout_be32(&uf_regs->gumr, gumr);\n+\tiowrite32be(gumr, &uf_regs->gumr);\n }\n EXPORT_SYMBOL(ucc_fast_disable);\n \n@@ -263,12 +263,13 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc\n \tgumr |= uf_info->tenc;\n \tgumr |= uf_info->tcrc;\n \tgumr |= uf_info->mode;\n-\tout_be32(&uf_regs->gumr, gumr);\n+\tiowrite32be(gumr, &uf_regs->gumr);\n \n \t/* Allocate memory for Tx Virtual Fifo */\n \tuccf->ucc_fast_tx_virtual_fifo_base_offset =\n \t qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);\n-\tif (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {\n+\tif (IS_ERR_VALUE((unsigned long)uccf->\n+\t\t\t ucc_fast_tx_virtual_fifo_base_offset)) {\n \t\tprintk(KERN_ERR \"%s: cannot allocate MURAM for TX FIFO\\n\",\n \t\t\t__func__);\n \t\tuccf->ucc_fast_tx_virtual_fifo_base_offset = 0;\n@@ -281,7 +282,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc\n \t\tqe_muram_alloc(uf_info->urfs +\n \t\t\t UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,\n \t\t\t UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);\n-\tif (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {\n+\tif (IS_ERR_VALUE((unsigned long)uccf->\n+\t\t\t ucc_fast_rx_virtual_fifo_base_offset)) {\n \t\tprintk(KERN_ERR \"%s: cannot allocate MURAM for RX FIFO\\n\",\n \t\t\t__func__);\n \t\tuccf->ucc_fast_rx_virtual_fifo_base_offset = 0;\n@@ -290,15 +292,15 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc\n \t}\n \n \t/* Set Virtual Fifo registers */\n-\tout_be16(&uf_regs->urfs, uf_info->urfs);\n-\tout_be16(&uf_regs->urfet, uf_info->urfet);\n-\tout_be16(&uf_regs->urfset, uf_info->urfset);\n-\tout_be16(&uf_regs->utfs, uf_info->utfs);\n-\tout_be16(&uf_regs->utfet, uf_info->utfet);\n-\tout_be16(&uf_regs->utftt, uf_info->utftt);\n+\tiowrite16be(uf_info->urfs, &uf_regs->urfs);\n+\tiowrite16be(uf_info->urfet, &uf_regs->urfet);\n+\tiowrite16be(uf_info->urfset, &uf_regs->urfset);\n+\tiowrite16be(uf_info->utfs, &uf_regs->utfs);\n+\tiowrite16be(uf_info->utfet, &uf_regs->utfet);\n+\tiowrite16be(uf_info->utftt, &uf_regs->utftt);\n \t/* utfb, urfb are offsets from MURAM base */\n-\tout_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);\n-\tout_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);\n+\tiowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);\n+\tiowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);\n \n \t/* Mux clocking */\n \t/* Grant Support */\n@@ -366,14 +368,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc\n \t}\n \n \t/* Set interrupt mask register at UCC level. */\n-\tout_be32(&uf_regs->uccm, uf_info->uccm_mask);\n+\tiowrite32be(uf_info->uccm_mask, &uf_regs->uccm);\n \n \t/* First, clear anything pending at UCC level,\n \t * otherwise, old garbage may come through\n \t * as soon as the dam is opened. */\n \n \t/* Writing '1' clears */\n-\tout_be32(&uf_regs->ucce, 0xffffffff);\n+\tiowrite32be(0xffffffff, &uf_regs->ucce);\n \n \t*uccf_ret = uccf;\n \treturn 0;\ndiff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig\nindex 518db24a..d436c5d 100644\n--- a/drivers/tty/serial/Kconfig\n+++ b/drivers/tty/serial/Kconfig\n@@ -1153,7 +1153,7 @@ config SERIAL_LANTIQ\n \n config SERIAL_QE\n \ttristate \"Freescale QUICC Engine serial port support\"\n-\tdepends on QUICC_ENGINE\n+\tdepends on QUICC_ENGINE && FSL_SOC && PPC32\n \tselect SERIAL_CORE\n \tselect FW_LOADER\n \tdefault n\ndiff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c\nindex 481eb29..ee409fd 100644\n--- a/drivers/tty/serial/ucc_uart.c\n+++ b/drivers/tty/serial/ucc_uart.c\n@@ -34,6 +34,7 @@\n #include <soc/fsl/qe/ucc_slow.h>\n \n #include <linux/firmware.h>\n+#include <asm/cpm.h>\n #include <asm/reg.h>\n \n /*\ndiff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig\nindex 658b8da..e18168c 100644\n--- a/drivers/usb/gadget/udc/Kconfig\n+++ b/drivers/usb/gadget/udc/Kconfig\n@@ -277,7 +277,7 @@ config USB_AMD5536UDC\n \n config USB_FSL_QE\n \ttristate \"Freescale QE/CPM USB Device Controller\"\n-\tdepends on FSL_SOC && (QUICC_ENGINE || CPM)\n+\tdepends on (FSL_SOC && QUICC_ENGINE && PPC32) || (FSL_SOC && CPM)\n \thelp\n \t Some of Freescale PowerPC processors have a Full Speed\n \t QE/CPM2 USB controller, which support device mode with 4\ndiff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig\nindex 2e710a4..24019cc 100644\n--- a/drivers/usb/host/Kconfig\n+++ b/drivers/usb/host/Kconfig\n@@ -638,7 +638,7 @@ config USB_UHCI_BIG_ENDIAN_DESC\n \n config USB_FHCI_HCD\n \ttristate \"Freescale QE USB Host Controller support\"\n-\tdepends on OF_GPIO && QE_GPIO && QUICC_ENGINE\n+\tdepends on OF_GPIO && QE_GPIO && QUICC_ENGINE && FSL_SOC && PPC32\n \tselect FSL_GTM\n \tselect QE_USB\n \thelp\ndiff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h\nindex 70339d7..f7a14f2 100644\n--- a/include/soc/fsl/qe/qe.h\n+++ b/include/soc/fsl/qe/qe.h\n@@ -21,7 +21,6 @@\n #include <linux/spinlock.h>\n #include <linux/errno.h>\n #include <linux/err.h>\n-#include <asm/cpm.h>\n #include <soc/fsl/qe/immap_qe.h>\n #include <linux/of.h>\n #include <linux/of_address.h>\n", "prefixes": [ "v9" ] }