Patch Detail
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patch:
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Update a patch.
GET /api/patches/695638/?format=api
{ "id": 695638, "url": "http://patchwork.ozlabs.org/api/patches/695638/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1479307230-16650-18-git-send-email-claudiu.manoil@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1479307230-16650-18-git-send-email-claudiu.manoil@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1479307230-16650-18-git-send-email-claudiu.manoil@nxp.com/", "date": "2016-11-16T14:40:30", "name": "[17/17] soc/qman: Handle endianness of h/w descriptors", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "af460b885d0e2eab96f3dbe3f98fdef4a1c3e302", "submitter": { "id": 68115, "url": "http://patchwork.ozlabs.org/api/people/68115/?format=api", "name": "Claudiu Manoil", "email": "claudiu.manoil@nxp.com" }, "delegate": { "id": 1707, "url": "http://patchwork.ozlabs.org/api/users/1707/?format=api", "username": "scottwood", "first_name": "Scott", "last_name": "Wood", "email": "scottwood@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1479307230-16650-18-git-send-email-claudiu.manoil@nxp.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/695638/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/695638/checks/", "tags": {}, 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h/w descriptors", "Date": "Wed, 16 Nov 2016 16:40:30 +0200", "Message-ID": "<1479307230-16650-18-git-send-email-claudiu.manoil@nxp.com>", "X-Mailer": "git-send-email 1.7.11.7", "In-Reply-To": "<1479307230-16650-1-git-send-email-claudiu.manoil@nxp.com>", "References": "<1479307230-16650-1-git-send-email-claudiu.manoil@nxp.com>", "X-IncomingHeaderCount": "10", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131237808587379650;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; IPV:NLI; CTRY:US; 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PCL:0;\n\tRULEID:(6095035)(601004)(2401047)(13024025)(13015025)(13017025)(13023025)(5005006)(8121501046)(13018025)(10201501046)(3002001)(6055026)(6096035);\n\tSRVR:BY2PR0301MB1574; BCL:0; PCL:0; RULEID:(400006);\n\tSRVR:BY2PR0301MB1574; ", "X-Forefront-PRVS": "01283822F8", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Nov 2016 14:40:58.4883\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY2PR0301MB1574", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Scott Wood <oss@buserror.net>, roy.pledge@nxp.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The hardware descriptors have big endian (BE) format.\nProvide proper endianness handling for the remaining\ndescriptor fields, to ensure they are correctly\naccessed by non-BE CPUs too.\n\nSigned-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>\n---\n drivers/soc/fsl/qbman/qman.c | 65 ++++++++++++++++++---------------\n drivers/soc/fsl/qbman/qman_priv.h | 10 ++---\n drivers/soc/fsl/qbman/qman_test_api.c | 4 +-\n drivers/soc/fsl/qbman/qman_test_stash.c | 5 ++-\n include/soc/fsl/qman.h | 48 ++++++++++++------------\n 5 files changed, 70 insertions(+), 62 deletions(-)", "diff": "diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c\nindex d287ef0..41895078 100644\n--- a/drivers/soc/fsl/qbman/qman.c\n+++ b/drivers/soc/fsl/qbman/qman.c\n@@ -140,10 +140,10 @@ enum qm_mr_cmode {\t\t/* matches QCSP_CFG::MM */\n struct qm_eqcr_entry {\n \tu8 _ncw_verb; /* writes to this are non-coherent */\n \tu8 dca;\n-\tu16 seqnum;\n+\t__be16 seqnum;\n \tu8 __reserved[4];\n-\tu32 fqid;\t/* 24-bit */\n-\tu32 tag;\n+\t__be32 fqid;\t/* 24-bit */\n+\t__be32 tag;\n \tstruct qm_fd fd;\n \tu8 __reserved3[32];\n } __packed;\n@@ -187,7 +187,7 @@ struct qm_mr {\n struct qm_mcc_fq {\n \tu8 _ncw_verb;\n \tu8 __reserved1[3];\n-\tu32 fqid;\t/* 24-bit */\n+\t__be32 fqid;\t/* 24-bit */\n \tu8 __reserved2[56];\n } __packed;\n \n@@ -470,7 +470,7 @@ static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal\n static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)\n {\n \tDPAA_ASSERT(eqcr->busy);\n-\tDPAA_ASSERT(!(eqcr->cursor->fqid & ~QM_FQID_MASK));\n+\tDPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK));\n \tDPAA_ASSERT(eqcr->available >= 1);\n }\n \n@@ -1395,7 +1395,7 @@ static void qm_mr_process_task(struct work_struct *work)\n \t\t\t\tbreak;\n \t\t\tcase QM_MR_VERB_FQPN:\n \t\t\t\t/* Parked */\n-\t\t\t\tfq = tag_to_fq(msg->fq.context_b);\n+\t\t\t\tfq = tag_to_fq(be32_to_cpu(msg->fq.context_b));\n \t\t\t\tfq_state_change(p, fq, msg, verb);\n \t\t\t\tif (fq->cb.fqs)\n \t\t\t\t\tfq->cb.fqs(p, fq, msg);\n@@ -1409,7 +1409,7 @@ static void qm_mr_process_task(struct work_struct *work)\n \t\t\t}\n \t\t} else {\n \t\t\t/* Its a software ERN */\n-\t\t\tfq = tag_to_fq(msg->ern.tag);\n+\t\t\tfq = tag_to_fq(be32_to_cpu(msg->ern.tag));\n \t\t\tfq->cb.ern(p, fq, msg);\n \t\t}\n \t\tnum++;\n@@ -1521,7 +1521,7 @@ static inline unsigned int __poll_portal_fast(struct qman_portal *p,\n \t\t\t\tclear_vdqcr(p, fq);\n \t\t} else {\n \t\t\t/* SDQCR: context_b points to the FQ */\n-\t\t\tfq = tag_to_fq(dq->context_b);\n+\t\t\tfq = tag_to_fq(be32_to_cpu(dq->context_b));\n \t\t\t/* Now let the callback do its stuff */\n \t\t\tres = fq->cb.dqrr(p, fq, dq);\n \t\t\t/*\n@@ -1738,9 +1738,9 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)\n \tif (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))\n \t\treturn -EINVAL;\n #endif\n-\tif (opts && (opts->we_mask & QM_INITFQ_WE_OAC)) {\n+\tif (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) {\n \t\t/* And can't be set at the same time as TDTHRESH */\n-\t\tif (opts->we_mask & QM_INITFQ_WE_TDTHRESH)\n+\t\tif (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH)\n \t\t\treturn -EINVAL;\n \t}\n \t/* Issue an INITFQ_[PARKED|SCHED] management command */\n@@ -1764,14 +1764,16 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)\n \tif (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {\n \t\tdma_addr_t phys_fq;\n \n-\t\tmcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTB;\n-\t\tmcc->initfq.fqd.context_b = fq_to_tag(fq);\n+\t\tmcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB);\n+\t\tmcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq));\n \t\t/*\n \t\t * and the physical address - NB, if the user wasn't trying to\n \t\t * set CONTEXTA, clear the stashing settings.\n \t\t */\n-\t\tif (!(mcc->initfq.we_mask & QM_INITFQ_WE_CONTEXTA)) {\n-\t\t\tmcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTA;\n+\t\tif (!(be16_to_cpu(mcc->initfq.we_mask) &\n+\t\t\t\t QM_INITFQ_WE_CONTEXTA)) {\n+\t\t\tmcc->initfq.we_mask |=\n+\t\t\t\tcpu_to_be16(QM_INITFQ_WE_CONTEXTA);\n \t\t\tmemset(&mcc->initfq.fqd.context_a, 0,\n \t\t\t\tsizeof(mcc->initfq.fqd.context_a));\n \t\t} else {\n@@ -1791,8 +1793,10 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)\n \tif (flags & QMAN_INITFQ_FLAG_LOCAL) {\n \t\tint wq = 0;\n \n-\t\tif (!(mcc->initfq.we_mask & QM_INITFQ_WE_DESTWQ)) {\n-\t\t\tmcc->initfq.we_mask |= QM_INITFQ_WE_DESTWQ;\n+\t\tif (!(be16_to_cpu(mcc->initfq.we_mask) &\n+\t\t\t\t QM_INITFQ_WE_DESTWQ)) {\n+\t\t\tmcc->initfq.we_mask |=\n+\t\t\t\tcpu_to_be16(QM_INITFQ_WE_DESTWQ);\n \t\t\twq = 4;\n \t\t}\n \t\tqm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);\n@@ -1811,13 +1815,13 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)\n \t\tgoto out;\n \t}\n \tif (opts) {\n-\t\tif (opts->we_mask & QM_INITFQ_WE_FQCTRL) {\n-\t\t\tif (opts->fqd.fq_ctrl & QM_FQCTRL_CGE)\n+\t\tif (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) {\n+\t\t\tif (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE)\n \t\t\t\tfq_set(fq, QMAN_FQ_STATE_CGR_EN);\n \t\t\telse\n \t\t\t\tfq_clear(fq, QMAN_FQ_STATE_CGR_EN);\n \t\t}\n-\t\tif (opts->we_mask & QM_INITFQ_WE_CGID)\n+\t\tif (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID)\n \t\t\tfq->cgr_groupid = opts->fqd.cgid;\n \t}\n \tfq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?\n@@ -1937,7 +1941,7 @@ int qman_retire_fq(struct qman_fq *fq, u32 *flags)\n \t\t\tmsg.verb = QM_MR_VERB_FQRNI;\n \t\t\tmsg.fq.fqs = mcr->alterfq.fqs;\n \t\t\tqm_fqid_set(&msg.fq, fq->fqid);\n-\t\t\tmsg.fq.context_b = fq_to_tag(fq);\n+\t\t\tmsg.fq.context_b = cpu_to_be32(fq_to_tag(fq));\n \t\t\tfq->cb.fqs(p, fq, &msg);\n \t\t}\n \t} else if (res == QM_MCR_RESULT_PENDING) {\n@@ -2206,7 +2210,7 @@ int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)\n \t\tgoto out;\n \n \tqm_fqid_set(eq, fq->fqid);\n-\teq->tag = fq_to_tag(fq);\n+\teq->tag = cpu_to_be32(fq_to_tag(fq));\n \teq->fd = *fd;\n \n \tqm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);\n@@ -2253,17 +2257,18 @@ static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags,\n static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val)\n {\n \tif (qman_ip_rev >= QMAN_REV30)\n-\t\tcgr->cscn_targ_upd_ctrl = QM_CGR_TARG_UDP_CTRL_WRITE_BIT | pi;\n+\t\tcgr->cscn_targ_upd_ctrl = cpu_to_be16(pi |\n+\t\t\t\t\tQM_CGR_TARG_UDP_CTRL_WRITE_BIT);\n \telse\n-\t\tcgr->cscn_targ = val | QM_CGR_TARG_PORTAL(pi);\n+\t\tcgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi));\n }\n \n static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val)\n {\n \tif (qman_ip_rev >= QMAN_REV30)\n-\t\tcgr->cscn_targ_upd_ctrl = pi;\n+\t\tcgr->cscn_targ_upd_ctrl = cpu_to_be16(pi);\n \telse\n-\t\tcgr->cscn_targ = val & ~QM_CGR_TARG_PORTAL(pi);\n+\t\tcgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi));\n }\n \n static u8 qman_cgr_cpus[CGR_NUM];\n@@ -2315,8 +2320,8 @@ int qman_create_cgr(struct qman_cgr *cgr, u32 flags,\n \t\t\tgoto out;\n \n \t\tqm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p),\n-\t\t\t\t cgr_state.cgr.cscn_targ);\n-\t\tlocal_opts.we_mask |= QM_CGR_WE_CSCN_TARG;\n+\t\t\t\t be32_to_cpu(cgr_state.cgr.cscn_targ));\n+\t\tlocal_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG);\n \n \t\t/* send init if flags indicate so */\n \t\tif (flags & QMAN_CGR_FLAG_USE_INIT)\n@@ -2383,9 +2388,9 @@ int qman_delete_cgr(struct qman_cgr *cgr)\n \t\tgoto release_lock;\n \t}\n \n-\tlocal_opts.we_mask = QM_CGR_WE_CSCN_TARG;\n+\tlocal_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG);\n \tqm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p),\n-\t\t\t cgr_state.cgr.cscn_targ);\n+\t\t\t be32_to_cpu(cgr_state.cgr.cscn_targ));\n \n \tret = qm_modify_cgr(cgr, 0, &local_opts);\n \tif (ret)\n@@ -2835,7 +2840,7 @@ static int cgr_cleanup(u32 cgrid)\n \t\t\terr = qman_query_fq(&fq, &fqd);\n \t\t\tif (WARN_ON(err))\n \t\t\t\treturn err;\n-\t\t\tif ((fqd.fq_ctrl & QM_FQCTRL_CGE) &&\n+\t\t\tif (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE &&\n \t\t\t fqd.cgid == cgrid) {\n \t\t\t\tpr_err(\"CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\\n\",\n \t\t\t\t cgrid, fq.fqid);\ndiff --git a/drivers/soc/fsl/qbman/qman_priv.h b/drivers/soc/fsl/qbman/qman_priv.h\nindex 5606d74..53685b5 100644\n--- a/drivers/soc/fsl/qbman/qman_priv.h\n+++ b/drivers/soc/fsl/qbman/qman_priv.h\n@@ -73,20 +73,20 @@ struct qm_mcr_querycgr {\n \tstruct __qm_mc_cgr cgr; /* CGR fields */\n \tu8 __reserved2[6];\n \tu8 i_bcnt_hi;\t/* high 8-bits of 40-bit \"Instant\" */\n-\tu32 i_bcnt_lo;\t/* low 32-bits of 40-bit */\n+\t__be32 i_bcnt_lo;\t/* low 32-bits of 40-bit */\n \tu8 __reserved3[3];\n \tu8 a_bcnt_hi;\t/* high 8-bits of 40-bit \"Average\" */\n-\tu32 a_bcnt_lo;\t/* low 32-bits of 40-bit */\n-\tu32 cscn_targ_swp[4];\n+\t__be32 a_bcnt_lo;\t/* low 32-bits of 40-bit */\n+\t__be32 cscn_targ_swp[4];\n } __packed;\n \n static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q)\n {\n-\treturn ((u64)q->i_bcnt_hi << 32) | (u64)q->i_bcnt_lo;\n+\treturn ((u64)q->i_bcnt_hi << 32) | be32_to_cpu(q->i_bcnt_lo);\n }\n static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q)\n {\n-\treturn ((u64)q->a_bcnt_hi << 32) | (u64)q->a_bcnt_lo;\n+\treturn ((u64)q->a_bcnt_hi << 32) | be32_to_cpu(q->a_bcnt_lo);\n }\n \n /* \"Query FQ Non-Programmable Fields\" */\ndiff --git a/drivers/soc/fsl/qbman/qman_test_api.c b/drivers/soc/fsl/qbman/qman_test_api.c\nindex dba6a80..2895d06 100644\n--- a/drivers/soc/fsl/qbman/qman_test_api.c\n+++ b/drivers/soc/fsl/qbman/qman_test_api.c\n@@ -65,7 +65,7 @@ static void fd_init(struct qm_fd *fd)\n {\n \tqm_fd_addr_set64(fd, 0xabdeadbeefLLU);\n \tqm_fd_set_contig_big(fd, 0x0000ffff);\n-\tfd->cmd = 0xfeedf00d;\n+\tfd->cmd = cpu_to_be32(0xfeedf00d);\n }\n \n static void fd_inc(struct qm_fd *fd)\n@@ -86,7 +86,7 @@ static void fd_inc(struct qm_fd *fd)\n \tlen--;\n \tqm_fd_set_param(fd, fmt, off, len);\n \n-\tfd->cmd++;\n+\tfd->cmd = cpu_to_be32(be32_to_cpu(fd->cmd) + 1);\n }\n \n /* The only part of the 'fd' we can't memcmp() is the ppid */\ndiff --git a/drivers/soc/fsl/qbman/qman_test_stash.c b/drivers/soc/fsl/qbman/qman_test_stash.c\nindex f8d25fa..b9795f3 100644\n--- a/drivers/soc/fsl/qbman/qman_test_stash.c\n+++ b/drivers/soc/fsl/qbman/qman_test_stash.c\n@@ -406,8 +406,9 @@ static int init_handler(void *h)\n \t\tgoto failed;\n \t}\n \tmemset(&opts, 0, sizeof(opts));\n-\topts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;\n-\topts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING;\n+\topts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL |\n+\t\t\t\t QM_INITFQ_WE_CONTEXTA);\n+\topts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING);\n \tqm_fqd_set_stashing(&opts.fqd, 0, STASH_DATA_CL, STASH_CTX_CL);\n \terr = qman_init_fq(&handler->rx, QMAN_INITFQ_FLAG_SCHED |\n \t\t\t QMAN_INITFQ_FLAG_LOCAL, &opts);\ndiff --git a/include/soc/fsl/qman.h b/include/soc/fsl/qman.h\nindex d01d5a3..3d4df74 100644\n--- a/include/soc/fsl/qman.h\n+++ b/include/soc/fsl/qman.h\n@@ -244,11 +244,11 @@ static inline int qm_sg_entry_get_off(const struct qm_sg_entry *sg)\n struct qm_dqrr_entry {\n \tu8 verb;\n \tu8 stat;\n-\tu16 seqnum;\t/* 15-bit */\n+\t__be16 seqnum;\t/* 15-bit */\n \tu8 tok;\n \tu8 __reserved2[3];\n-\tu32 fqid;\t/* 24-bit */\n-\tu32 context_b;\n+\t__be32 fqid;\t/* 24-bit */\n+\t__be32 context_b;\n \tstruct qm_fd fd;\n \tu8 __reserved4[32];\n } __packed;\n@@ -264,8 +264,8 @@ struct qm_dqrr_entry {\n \n /* 'fqid' is a 24-bit field in every h/w descriptor */\n #define QM_FQID_MASK\tGENMASK(23, 0)\n-#define qm_fqid_set(p, v) ((p)->fqid = ((v) & QM_FQID_MASK))\n-#define qm_fqid_get(p) ((p)->fqid & QM_FQID_MASK)\n+#define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK))\n+#define qm_fqid_get(p) (be32_to_cpu((p)->fqid) & QM_FQID_MASK)\n \n /* \"ERN Message Response\" */\n /* \"FQ State Change Notification\" */\n@@ -277,11 +277,11 @@ struct qm_dqrr_entry {\n \tstruct {\n \t\tu8 verb;\n \t\tu8 dca;\n-\t\tu16 seqnum;\n+\t\t__be16 seqnum;\n \t\tu8 rc;\t\t/* Rej Code: 8-bit */\n \t\tu8 __reserved[3];\n-\t\tu32 fqid;\t/* 24-bit */\n-\t\tu32 tag;\n+\t\t__be32 fqid;\t/* 24-bit */\n+\t\t__be32 tag;\n \t\tstruct qm_fd fd;\n \t\tu8 __reserved1[32];\n \t} __packed ern;\n@@ -289,8 +289,8 @@ struct qm_dqrr_entry {\n \t\tu8 verb;\n \t\tu8 fqs;\t\t/* Frame Queue Status */\n \t\tu8 __reserved1[6];\n-\t\tu32 fqid;\t/* 24-bit */\n-\t\tu32 context_b;\n+\t\t__be32 fqid;\t/* 24-bit */\n+\t\t__be32 context_b;\n \t\tu8 __reserved2[48];\n \t} __packed fq;\t\t/* FQRN/FQRNI/FQRL/FQPN */\n };\n@@ -409,8 +409,8 @@ static inline u64 qm_fqd_context_a_get64(const struct qm_fqd *fqd)\n \n static inline void qm_fqd_stashing_set64(struct qm_fqd *fqd, u64 addr)\n {\n-\tfqd->context_a.context_hi = upper_32_bits(addr);\n-\tfqd->context_a.context_lo = lower_32_bits(addr);\n+\tfqd->context_a.context_hi = cpu_to_be16(upper_32_bits(addr));\n+\tfqd->context_a.context_lo = cpu_to_be32(lower_32_bits(addr));\n }\n \n static inline void qm_fqd_context_a_set64(struct qm_fqd *fqd, u64 addr)\n@@ -525,7 +525,7 @@ static inline int qm_fqd_get_wq(const struct qm_fqd *fqd)\n */\n struct qm_cgr_wr_parm {\n \t/* MA[24-31], Mn[19-23], SA[12-18], Sn[6-11], Pn[0-5] */\n-\tu32 word;\n+\t__be32 word;\n };\n /*\n * This struct represents the 13-bit \"CS_THRES\" CGR field. In the corresponding\n@@ -536,7 +536,7 @@ struct qm_cgr_wr_parm {\n */\n struct qm_cgr_cs_thres {\n \t/* _res[13-15], TA[5-12], Tn[0-4] */\n-\tu16 word;\n+\t__be16 word;\n };\n /*\n * This identical structure of CGR fields is present in the \"Init/Modify CGR\"\n@@ -553,10 +553,10 @@ struct __qm_mc_cgr {\n \tu8 cscn_en;\t/* boolean, use QM_CGR_EN */\n \tunion {\n \t\tstruct {\n-\t\t\tu16 cscn_targ_upd_ctrl; /* use QM_CGR_TARG_UDP_* */\n-\t\t\tu16 cscn_targ_dcp_low;\n+\t\t\t__be16 cscn_targ_upd_ctrl; /* use QM_CGR_TARG_UDP_* */\n+\t\t\t__be16 cscn_targ_dcp_low;\n \t\t};\n-\t\tu32 cscn_targ;\t/* use QM_CGR_TARG_* */\n+\t\t__be32 cscn_targ;\t/* use QM_CGR_TARG_* */\n \t};\n \tu8 cstd_en;\t/* boolean, use QM_CGR_EN */\n \tu8 cs;\t\t/* boolean, only used in query response */\n@@ -572,7 +572,9 @@ struct __qm_mc_cgr {\n /* Convert CGR thresholds to/from \"cs_thres\" format */\n static inline u64 qm_cgr_cs_thres_get64(const struct qm_cgr_cs_thres *th)\n {\n-\treturn ((th->word >> 5) & 0xff) << (th->word & 0x1f);\n+\tint thres = be16_to_cpu(th->word);\n+\n+\treturn ((thres >> 5) & 0xff) << (thres & 0x1f);\n }\n \n static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val,\n@@ -588,23 +590,23 @@ static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val,\n \t\tif (roundup && oddbit)\n \t\t\tval++;\n \t}\n-\tth->word = ((val & 0xff) << 5) | (e & 0x1f);\n+\tth->word = cpu_to_be16(((val & 0xff) << 5) | (e & 0x1f));\n \treturn 0;\n }\n \n /* \"Initialize FQ\" */\n struct qm_mcc_initfq {\n \tu8 __reserved1[2];\n-\tu16 we_mask;\t/* Write Enable Mask */\n-\tu32 fqid;\t/* 24-bit */\n-\tu16 count;\t/* Initialises 'count+1' FQDs */\n+\t__be16 we_mask;\t/* Write Enable Mask */\n+\t__be32 fqid;\t/* 24-bit */\n+\t__be16 count;\t/* Initialises 'count+1' FQDs */\n \tstruct qm_fqd fqd; /* the FQD fields go here */\n \tu8 __reserved2[30];\n } __packed;\n /* \"Initialize/Modify CGR\" */\n struct qm_mcc_initcgr {\n \tu8 __reserve1[2];\n-\tu16 we_mask;\t/* Write Enable Mask */\n+\t__be16 we_mask;\t/* Write Enable Mask */\n \tstruct __qm_mc_cgr cgr;\t/* CGR fields */\n \tu8 __reserved2[2];\n \tu8 cgid;\n", "prefixes": [ "17/17" ] }