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GET /api/patches/694718/?format=api
{ "id": 694718, "url": "http://patchwork.ozlabs.org/api/patches/694718/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1479157609-30812-2-git-send-email-bimmy.pujari@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1479157609-30812-2-git-send-email-bimmy.pujari@intel.com>", "list_archive_url": null, "date": "2016-11-14T21:06:46", "name": "[next,S53-V2,2/5] i40e: Add support for 25G devices", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "c6b56ef1eff840500bb675e2f24766de3d1ad2e5", "submitter": { "id": 68919, "url": "http://patchwork.ozlabs.org/api/people/68919/?format=api", "name": "Pujari, Bimmy", "email": "bimmy.pujari@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1479157609-30812-2-git-send-email-bimmy.pujari@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/694718/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/694718/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3tHjn233GLz9t3N\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 15 Nov 2016 08:08:54 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id CA7213164C;\n\tMon, 14 Nov 2016 21:08:52 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 3c9qsmoh-z7K; Mon, 14 Nov 2016 21:08:33 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id E79702555C;\n\tMon, 14 Nov 2016 21:08:29 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 3BA4B1C1F38\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 14 Nov 2016 21:08:28 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 375E48A3CD\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 14 Nov 2016 21:08:28 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id QaD1+X3+Di7w for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 14 Nov 2016 21:08:25 +0000 (UTC)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 305788A797\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 14 Nov 2016 21:08:25 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga104.fm.intel.com with ESMTP; 14 Nov 2016 13:08:24 -0800", "from bimmy.jf.intel.com (HELO bimmy.linux1.jf.intel.com)\n\t([134.134.2.167])\n\tby orsmga005.jf.intel.com with ESMTP; 14 Nov 2016 13:08:23 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.31,640,1473145200\"; d=\"scan'208\";a=\"31193139\"", "From": "Bimmy Pujari <bimmy.pujari@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 14 Nov 2016 13:06:46 -0800", "Message-Id": "<1479157609-30812-2-git-send-email-bimmy.pujari@intel.com>", "X-Mailer": "git-send-email 2.4.11", "In-Reply-To": "<1479157609-30812-1-git-send-email-bimmy.pujari@intel.com>", "References": "<1479157609-30812-1-git-send-email-bimmy.pujari@intel.com>", "Cc": "Henry Tieman <henry.w.tieman@intel.com>,\n\tEric Joyner <eric.joyner@intel.com>,\n\tMichal Kosiarz <michal.kosiarz@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S53-V2 2/5] i40e: Add support for 25G\n\tdevices", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Carolyn Wyborny <carolyn.wyborny@intel.com>\n\nAdd support for 25G devices - defines and data structures.\n\nOne tricky part here is that the firmware support for these\nDevices introduces a mismatch between the PHY type enum and\nthe bitfields for the phy types.\n\nThis change creates a macro and uses it to increment the 25G\nPHY values when creating 25G bitfields.\n\nSigned-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>\nSigned-off-by: Michal Kosiarz <michal.kosiarz@intel.com>\nSigned-off-by: Eric Joyner <eric.joyner@intel.com>\nSigned-off-by: Mitch Williams <mitch.a.williams@intel.com>\nSigned-off-by: Henry Tieman <henry.w.tieman@intel.com>\nSigned-off-by: Avinash Dayanand <avinash.dayanand@intel.com>\nChange-ID: I69b24d837d44cf9220bf5cb8dd46c5be89ce490b\n---\nTesting Hints : Check that 25G devices link and report\ncorrect device speed.\n\n drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h | 30 +++++++-\n drivers/net/ethernet/intel/i40e/i40e_common.c | 11 ++-\n drivers/net/ethernet/intel/i40e/i40e_devids.h | 2 +\n drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 20 +++++-\n drivers/net/ethernet/intel/i40e/i40e_main.c | 6 +-\n drivers/net/ethernet/intel/i40e/i40e_type.h | 82 +++++++++++++---------\n drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 3 +\n .../net/ethernet/intel/i40evf/i40e_adminq_cmd.h | 30 +++++++-\n drivers/net/ethernet/intel/i40evf/i40e_common.c | 2 +\n drivers/net/ethernet/intel/i40evf/i40e_devids.h | 2 +\n drivers/net/ethernet/intel/i40evf/i40e_type.h | 82 +++++++++++++---------\n drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c | 8 +++\n .../net/ethernet/intel/i40evf/i40evf_virtchnl.c | 3 +\n 13 files changed, 202 insertions(+), 79 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\nindex 67e396b..c9d1f91 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n@@ -1642,6 +1642,10 @@ enum i40e_aq_phy_type {\n \tI40E_PHY_TYPE_1000BASE_LX\t\t= 0x1C,\n \tI40E_PHY_TYPE_1000BASE_T_OPTICAL\t= 0x1D,\n \tI40E_PHY_TYPE_20GBASE_KR2\t\t= 0x1E,\n+\tI40E_PHY_TYPE_25GBASE_KR\t\t= 0x1F,\n+\tI40E_PHY_TYPE_25GBASE_CR\t\t= 0x20,\n+\tI40E_PHY_TYPE_25GBASE_SR\t\t= 0x21,\n+\tI40E_PHY_TYPE_25GBASE_LR\t\t= 0x22,\n \tI40E_PHY_TYPE_MAX\n };\n \n@@ -1650,6 +1654,7 @@ enum i40e_aq_phy_type {\n #define I40E_LINK_SPEED_10GB_SHIFT\t0x3\n #define I40E_LINK_SPEED_40GB_SHIFT\t0x4\n #define I40E_LINK_SPEED_20GB_SHIFT\t0x5\n+#define I40E_LINK_SPEED_25GB_SHIFT\t0x6\n \n enum i40e_aq_link_speed {\n \tI40E_LINK_SPEED_UNKNOWN\t= 0,\n@@ -1657,7 +1662,8 @@ enum i40e_aq_link_speed {\n \tI40E_LINK_SPEED_1GB\t= BIT(I40E_LINK_SPEED_1000MB_SHIFT),\n \tI40E_LINK_SPEED_10GB\t= BIT(I40E_LINK_SPEED_10GB_SHIFT),\n \tI40E_LINK_SPEED_40GB\t= BIT(I40E_LINK_SPEED_40GB_SHIFT),\n-\tI40E_LINK_SPEED_20GB\t= BIT(I40E_LINK_SPEED_20GB_SHIFT)\n+\tI40E_LINK_SPEED_20GB\t= BIT(I40E_LINK_SPEED_20GB_SHIFT),\n+\tI40E_LINK_SPEED_25GB\t= BIT(I40E_LINK_SPEED_25GB_SHIFT),\n };\n \n struct i40e_aqc_module_desc {\n@@ -1690,7 +1696,13 @@ struct i40e_aq_get_phy_abilities_resp {\n \t__le32\teeer_val;\n \tu8\td3_lpan;\n #define I40E_AQ_SET_PHY_D3_LPAN_ENA\t0x01\n-\tu8\treserved[3];\n+\tu8\tphy_type_ext;\n+#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n+#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n+#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n+#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n+\tu8\tmod_type_ext;\n+\tu8\text_comp_code;\n \tu8\tphy_id[4];\n \tu8\tmodule_type[3];\n \tu8\tqualified_module_count;\n@@ -1712,7 +1724,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */\n \t__le16\teee_capability;\n \t__le32\teeer;\n \tu8\tlow_power_ctrl;\n-\tu8\treserved[3];\n+\tu8\tphy_type_ext;\n+#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n+#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n+#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n+#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n+\tu8\treserved[2];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);\n@@ -1792,6 +1809,13 @@ struct i40e_aqc_get_link_status {\n #define I40E_AQ_LINK_TX_DRAINED\t\t0x01\n #define I40E_AQ_LINK_TX_FLUSHED\t\t0x03\n #define I40E_AQ_LINK_FORCED_40G\t\t0x10\n+/* 25G Error Codes */\n+#define I40E_AQ_25G_NO_ERR\t\t0X00\n+#define I40E_AQ_25G_NOT_PRESENT\t\t0X01\n+#define I40E_AQ_25G_NVM_CRC_ERR\t\t0X02\n+#define I40E_AQ_25G_SBUS_UCODE_ERR\t0X03\n+#define I40E_AQ_25G_SERDES_UCODE_ERR\t0X04\n+#define I40E_AQ_25G_NIMB_UCODE_ERR\t0X05\n \tu8\tloopback; /* use defines from i40e_aqc_set_lb_mode */\n \t__le16\tmax_frame_size;\n \tu8\tconfig;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex d1dcd4f..3961fc2 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -53,6 +53,8 @@ static i40e_status i40e_set_mac_type(struct i40e_hw *hw)\n \t\tcase I40E_DEV_ID_10G_BASE_T4:\n \t\tcase I40E_DEV_ID_20G_KR2:\n \t\tcase I40E_DEV_ID_20G_KR2_A:\n+\t\tcase I40E_DEV_ID_25G_B:\n+\t\tcase I40E_DEV_ID_25G_SFP28:\n \t\t\thw->mac.type = I40E_MAC_XL710;\n \t\t\tbreak;\n \t\tcase I40E_DEV_ID_KX_X722:\n@@ -1183,6 +1185,8 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)\n \tcase I40E_PHY_TYPE_1000BASE_LX:\n \tcase I40E_PHY_TYPE_40GBASE_SR4:\n \tcase I40E_PHY_TYPE_40GBASE_LR4:\n+\tcase I40E_PHY_TYPE_25GBASE_LR:\n+\tcase I40E_PHY_TYPE_25GBASE_SR:\n \t\tmedia = I40E_MEDIA_TYPE_FIBER;\n \t\tbreak;\n \tcase I40E_PHY_TYPE_100BASE_TX:\n@@ -1197,6 +1201,7 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)\n \tcase I40E_PHY_TYPE_10GBASE_SFPP_CU:\n \tcase I40E_PHY_TYPE_40GBASE_AOC:\n \tcase I40E_PHY_TYPE_10GBASE_AOC:\n+\tcase I40E_PHY_TYPE_25GBASE_CR:\n \t\tmedia = I40E_MEDIA_TYPE_DA;\n \t\tbreak;\n \tcase I40E_PHY_TYPE_1000BASE_KX:\n@@ -1204,6 +1209,7 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)\n \tcase I40E_PHY_TYPE_10GBASE_KR:\n \tcase I40E_PHY_TYPE_40GBASE_KR4:\n \tcase I40E_PHY_TYPE_20GBASE_KR2:\n+\tcase I40E_PHY_TYPE_25GBASE_KR:\n \t\tmedia = I40E_MEDIA_TYPE_BACKPLANE;\n \t\tbreak;\n \tcase I40E_PHY_TYPE_SGMII:\n@@ -1608,8 +1614,10 @@ i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,\n \tif (hw->aq.asq_last_status == I40E_AQ_RC_EIO)\n \t\tstatus = I40E_ERR_UNKNOWN_PHY;\n \n-\tif (report_init)\n+\tif (report_init) {\n \t\thw->phy.phy_types = le32_to_cpu(abilities->phy_type);\n+\t\thw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);\n+\t}\n \n \treturn status;\n }\n@@ -1701,6 +1709,7 @@ enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,\n \t\t\tconfig.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;\n \t\t/* Copy over all the old settings */\n \t\tconfig.phy_type = abilities.phy_type;\n+\t\tconfig.phy_type_ext = abilities.phy_type_ext;\n \t\tconfig.link_speed = abilities.link_speed;\n \t\tconfig.eee_capability = abilities.eee_capability;\n \t\tconfig.eeer = abilities.eeer_val;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_devids.h b/drivers/net/ethernet/intel/i40e/i40e_devids.h\nindex dd4457d..8e46098 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_devids.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_devids.h\n@@ -39,6 +39,8 @@\n #define I40E_DEV_ID_20G_KR2\t\t0x1587\n #define I40E_DEV_ID_20G_KR2_A\t\t0x1588\n #define I40E_DEV_ID_10G_BASE_T4\t\t0x1589\n+#define I40E_DEV_ID_25G_B\t\t0x158A\n+#define I40E_DEV_ID_25G_SFP28\t\t0x158B\n #define I40E_DEV_ID_KX_X722\t\t0x37CE\n #define I40E_DEV_ID_QSFP_X722\t\t0x37CF\n #define I40E_DEV_ID_SFP_X722\t\t0x37D0\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\nindex 6ba0035..4b3a71a 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n@@ -265,8 +265,9 @@ static void i40e_partition_setting_complaint(struct i40e_pf *pf)\n static void i40e_phy_type_to_ethtool(struct i40e_pf *pf, u32 *supported,\n \t\t\t\t u32 *advertising)\n {\n-\tenum i40e_aq_capabilities_phy_type phy_types = pf->hw.phy.phy_types;\n \tstruct i40e_link_status *hw_link_info = &pf->hw.phy.link_info;\n+\tu64 phy_types = pf->hw.phy.phy_types;\n+\n \t*supported = 0x0;\n \t*advertising = 0x0;\n \n@@ -369,6 +370,15 @@ static void i40e_phy_type_to_ethtool(struct i40e_pf *pf, u32 *supported,\n \t\t\tif (!(pf->flags & I40E_FLAG_HAVE_CRT_RETIMER))\n \t\t\t\t*advertising |= ADVERTISED_1000baseKX_Full;\n \t}\n+\tif (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||\n+\t phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||\n+\t phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||\n+\t phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR) {\n+\t\t*supported |= SUPPORTED_Autoneg |\n+\t\t\t SUPPORTED_2500baseX_Full;\n+\t\t*advertising |= ADVERTISED_Autoneg |\n+\t\t\t ADVERTISED_2500baseX_Full;\n+\t}\n }\n \n /**\n@@ -491,6 +501,14 @@ static void i40e_get_settings_link_up(struct i40e_hw *hw,\n \t\t\t\t ADVERTISED_1000baseKX_Full |\n \t\t\t\t ADVERTISED_Autoneg;\n \t\tbreak;\n+\tcase I40E_PHY_TYPE_25GBASE_KR:\n+\tcase I40E_PHY_TYPE_25GBASE_CR:\n+\tcase I40E_PHY_TYPE_25GBASE_SR:\n+\tcase I40E_PHY_TYPE_25GBASE_LR:\n+\t\tecmd->supported |= SUPPORTED_2500baseX_Full |\n+\t\t\t\t SUPPORTED_Autoneg;\n+\t\tecmd->advertising |= ADVERTISED_2500baseX_Full |\n+\t\t\t\t ADVERTISED_Autoneg;\n \tdefault:\n \t\t/* if we got here and link is up something bad is afoot */\n \t\tnetdev_info(netdev, \"WARNING: Link is up but PHY type 0x%x is not recognized.\\n\",\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c\nindex a032dfd..849feaa 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_main.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c\n@@ -86,6 +86,8 @@ static const struct pci_device_id i40e_pci_tbl[] = {\n \t{PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},\n \t{PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},\n \t{PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},\n+\t{PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_B), 0},\n+\t{PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_SFP28), 0},\n \t/* required last entry */\n \t{0, }\n };\n@@ -5248,6 +5250,9 @@ void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)\n \tcase I40E_LINK_SPEED_20GB:\n \t\tspeed = \"20 G\";\n \t\tbreak;\n+\tcase I40E_LINK_SPEED_25GB:\n+\t\tspeed = \"25 G\";\n+\t\tbreak;\n \tcase I40E_LINK_SPEED_10GB:\n \t\tspeed = \"10 G\";\n \t\tbreak;\n@@ -11356,7 +11361,6 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n \t\tdev_dbg(&pf->pdev->dev, \"get supported phy types ret = %s last_status = %s\\n\",\n \t\t\ti40e_stat_str(&pf->hw, err),\n \t\t\ti40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));\n-\tpf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);\n \n \t/* Add a filter to drop all Flow control frames from any VSI from being\n \t * transmitted. By doing so we stop a malicious VF from sending out\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h\nindex e02cb73..7272be3 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h\n@@ -213,47 +213,59 @@ struct i40e_link_status {\n #define I40E_MODULE_TYPE_1000BASE_T\t0x08\n };\n \n-enum i40e_aq_capabilities_phy_type {\n-\tI40E_CAP_PHY_TYPE_SGMII\t\t = BIT(I40E_PHY_TYPE_SGMII),\n-\tI40E_CAP_PHY_TYPE_1000BASE_KX\t = BIT(I40E_PHY_TYPE_1000BASE_KX),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KX4\t = BIT(I40E_PHY_TYPE_10GBASE_KX4),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KR\t = BIT(I40E_PHY_TYPE_10GBASE_KR),\n-\tI40E_CAP_PHY_TYPE_40GBASE_KR4\t = BIT(I40E_PHY_TYPE_40GBASE_KR4),\n-\tI40E_CAP_PHY_TYPE_XAUI\t\t = BIT(I40E_PHY_TYPE_XAUI),\n-\tI40E_CAP_PHY_TYPE_XFI\t\t = BIT(I40E_PHY_TYPE_XFI),\n-\tI40E_CAP_PHY_TYPE_SFI\t\t = BIT(I40E_PHY_TYPE_SFI),\n-\tI40E_CAP_PHY_TYPE_XLAUI\t\t = BIT(I40E_PHY_TYPE_XLAUI),\n-\tI40E_CAP_PHY_TYPE_XLPPI\t\t = BIT(I40E_PHY_TYPE_XLPPI),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_AOC\t = BIT(I40E_PHY_TYPE_10GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_40GBASE_AOC\t = BIT(I40E_PHY_TYPE_40GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_100BASE_TX\t = BIT(I40E_PHY_TYPE_100BASE_TX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T\t = BIT(I40E_PHY_TYPE_1000BASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_T\t = BIT(I40E_PHY_TYPE_10GBASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SR\t = BIT(I40E_PHY_TYPE_10GBASE_SR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_LR\t = BIT(I40E_PHY_TYPE_10GBASE_LR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1\t = BIT(I40E_PHY_TYPE_10GBASE_CR1),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4\t = BIT(I40E_PHY_TYPE_40GBASE_CR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_SR4\t = BIT(I40E_PHY_TYPE_40GBASE_SR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_LR4\t = BIT(I40E_PHY_TYPE_40GBASE_LR4),\n-\tI40E_CAP_PHY_TYPE_1000BASE_SX\t = BIT(I40E_PHY_TYPE_1000BASE_SX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_LX\t = BIT(I40E_PHY_TYPE_1000BASE_LX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =\n-\t\t\t\t\t BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),\n-\tI40E_CAP_PHY_TYPE_20GBASE_KR2\t = BIT(I40E_PHY_TYPE_20GBASE_KR2)\n-};\n-\n struct i40e_phy_info {\n \tstruct i40e_link_status link_info;\n \tstruct i40e_link_status link_info_old;\n \tbool get_link_info;\n \tenum i40e_media_type media_type;\n \t/* all the phy types the NVM is capable of */\n-\tenum i40e_aq_capabilities_phy_type phy_types;\n-};\n-\n+\tu64 phy_types;\n+};\n+\n+#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)\n+#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)\n+#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)\n+#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)\n+#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)\n+#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)\n+#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)\n+#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)\n+#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)\n+#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)\n+/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some\n+ * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit\n+ * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,\n+ * a shift is needed to adjust for this with values larger than 31. The\n+ * only affected values are I40E_PHY_TYPE_25GBASE_*.\n+ */\n+#define I40E_PHY_TYPE_OFFSET 1\n+#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n+#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n+#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n+#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n #define I40E_HW_CAP_MAX_GPIO\t\t\t30\n /* Capabilities of a PF or a VF or the whole device */\n struct i40e_hw_capabilities {\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\nindex 05ed49b..d28b684 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\n@@ -2921,6 +2921,9 @@ int i40e_ndo_set_vf_bw(struct net_device *netdev, int vf_id, int min_tx_rate,\n \tcase I40E_LINK_SPEED_40GB:\n \t\tspeed = 40000;\n \t\tbreak;\n+\tcase I40E_LINK_SPEED_25GB:\n+\t\tspeed = 25000;\n+\t\tbreak;\n \tcase I40E_LINK_SPEED_20GB:\n \t\tspeed = 20000;\n \t\tbreak;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\nindex 40b0eaf..f8d7d95 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n@@ -1639,6 +1639,10 @@ enum i40e_aq_phy_type {\n \tI40E_PHY_TYPE_1000BASE_LX\t\t= 0x1C,\n \tI40E_PHY_TYPE_1000BASE_T_OPTICAL\t= 0x1D,\n \tI40E_PHY_TYPE_20GBASE_KR2\t\t= 0x1E,\n+\tI40E_PHY_TYPE_25GBASE_KR\t\t= 0x1F,\n+\tI40E_PHY_TYPE_25GBASE_CR\t\t= 0x20,\n+\tI40E_PHY_TYPE_25GBASE_SR\t\t= 0x21,\n+\tI40E_PHY_TYPE_25GBASE_LR\t\t= 0x22,\n \tI40E_PHY_TYPE_MAX\n };\n \n@@ -1647,6 +1651,7 @@ enum i40e_aq_phy_type {\n #define I40E_LINK_SPEED_10GB_SHIFT\t0x3\n #define I40E_LINK_SPEED_40GB_SHIFT\t0x4\n #define I40E_LINK_SPEED_20GB_SHIFT\t0x5\n+#define I40E_LINK_SPEED_25GB_SHIFT\t0x6\n \n enum i40e_aq_link_speed {\n \tI40E_LINK_SPEED_UNKNOWN\t= 0,\n@@ -1654,7 +1659,8 @@ enum i40e_aq_link_speed {\n \tI40E_LINK_SPEED_1GB\t= BIT(I40E_LINK_SPEED_1000MB_SHIFT),\n \tI40E_LINK_SPEED_10GB\t= BIT(I40E_LINK_SPEED_10GB_SHIFT),\n \tI40E_LINK_SPEED_40GB\t= BIT(I40E_LINK_SPEED_40GB_SHIFT),\n-\tI40E_LINK_SPEED_20GB\t= BIT(I40E_LINK_SPEED_20GB_SHIFT)\n+\tI40E_LINK_SPEED_20GB\t= BIT(I40E_LINK_SPEED_20GB_SHIFT),\n+\tI40E_LINK_SPEED_25GB\t= BIT(I40E_LINK_SPEED_25GB_SHIFT),\n };\n \n struct i40e_aqc_module_desc {\n@@ -1687,7 +1693,13 @@ struct i40e_aq_get_phy_abilities_resp {\n \t__le32\teeer_val;\n \tu8\td3_lpan;\n #define I40E_AQ_SET_PHY_D3_LPAN_ENA\t0x01\n-\tu8\treserved[3];\n+\tu8\tphy_type_ext;\n+#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n+#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n+#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n+#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n+\tu8\tmod_type_ext;\n+\tu8\text_comp_code;\n \tu8\tphy_id[4];\n \tu8\tmodule_type[3];\n \tu8\tqualified_module_count;\n@@ -1709,7 +1721,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */\n \t__le16\teee_capability;\n \t__le32\teeer;\n \tu8\tlow_power_ctrl;\n-\tu8\treserved[3];\n+\tu8\tphy_type_ext;\n+#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n+#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n+#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n+#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n+\tu8\treserved[2];\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);\n@@ -1789,6 +1806,13 @@ struct i40e_aqc_get_link_status {\n #define I40E_AQ_LINK_TX_DRAINED\t\t0x01\n #define I40E_AQ_LINK_TX_FLUSHED\t\t0x03\n #define I40E_AQ_LINK_FORCED_40G\t\t0x10\n+/* 25G Error Codes */\n+#define I40E_AQ_25G_NO_ERR\t\t0X00\n+#define I40E_AQ_25G_NOT_PRESENT\t\t0X01\n+#define I40E_AQ_25G_NVM_CRC_ERR\t\t0X02\n+#define I40E_AQ_25G_SBUS_UCODE_ERR\t0X03\n+#define I40E_AQ_25G_SERDES_UCODE_ERR\t0X04\n+#define I40E_AQ_25G_NIMB_UCODE_ERR\t0X05\n \tu8\tloopback; /* use defines from i40e_aqc_set_lb_mode */\n \t__le16\tmax_frame_size;\n \tu8\tconfig;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/i40evf/i40e_common.c\nindex 7953c13..aa63b7f 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_common.c\n@@ -53,6 +53,8 @@ i40e_status i40e_set_mac_type(struct i40e_hw *hw)\n \t\tcase I40E_DEV_ID_10G_BASE_T4:\n \t\tcase I40E_DEV_ID_20G_KR2:\n \t\tcase I40E_DEV_ID_20G_KR2_A:\n+\t\tcase I40E_DEV_ID_25G_B:\n+\t\tcase I40E_DEV_ID_25G_SFP28:\n \t\t\thw->mac.type = I40E_MAC_XL710;\n \t\t\tbreak;\n \t\tcase I40E_DEV_ID_SFP_X722:\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_devids.h b/drivers/net/ethernet/intel/i40evf/i40e_devids.h\nindex 7023570..21dcaee 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_devids.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_devids.h\n@@ -39,6 +39,8 @@\n #define I40E_DEV_ID_20G_KR2\t\t0x1587\n #define I40E_DEV_ID_20G_KR2_A\t\t0x1588\n #define I40E_DEV_ID_10G_BASE_T4\t\t0x1589\n+#define I40E_DEV_ID_25G_B\t\t0x158A\n+#define I40E_DEV_ID_25G_SFP28\t\t0x158B\n #define I40E_DEV_ID_VF\t\t\t0x154C\n #define I40E_DEV_ID_VF_HV\t\t0x1571\n #define I40E_DEV_ID_SFP_X722\t\t0x37D0\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h\nindex 515484c..c85e8a3 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h\n@@ -187,47 +187,59 @@ struct i40e_link_status {\n #define I40E_MODULE_TYPE_1000BASE_T\t0x08\n };\n \n-enum i40e_aq_capabilities_phy_type {\n-\tI40E_CAP_PHY_TYPE_SGMII\t\t = BIT(I40E_PHY_TYPE_SGMII),\n-\tI40E_CAP_PHY_TYPE_1000BASE_KX\t = BIT(I40E_PHY_TYPE_1000BASE_KX),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KX4\t = BIT(I40E_PHY_TYPE_10GBASE_KX4),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KR\t = BIT(I40E_PHY_TYPE_10GBASE_KR),\n-\tI40E_CAP_PHY_TYPE_40GBASE_KR4\t = BIT(I40E_PHY_TYPE_40GBASE_KR4),\n-\tI40E_CAP_PHY_TYPE_XAUI\t\t = BIT(I40E_PHY_TYPE_XAUI),\n-\tI40E_CAP_PHY_TYPE_XFI\t\t = BIT(I40E_PHY_TYPE_XFI),\n-\tI40E_CAP_PHY_TYPE_SFI\t\t = BIT(I40E_PHY_TYPE_SFI),\n-\tI40E_CAP_PHY_TYPE_XLAUI\t\t = BIT(I40E_PHY_TYPE_XLAUI),\n-\tI40E_CAP_PHY_TYPE_XLPPI\t\t = BIT(I40E_PHY_TYPE_XLPPI),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_AOC\t = BIT(I40E_PHY_TYPE_10GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_40GBASE_AOC\t = BIT(I40E_PHY_TYPE_40GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_100BASE_TX\t = BIT(I40E_PHY_TYPE_100BASE_TX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T\t = BIT(I40E_PHY_TYPE_1000BASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_T\t = BIT(I40E_PHY_TYPE_10GBASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SR\t = BIT(I40E_PHY_TYPE_10GBASE_SR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_LR\t = BIT(I40E_PHY_TYPE_10GBASE_LR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1\t = BIT(I40E_PHY_TYPE_10GBASE_CR1),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4\t = BIT(I40E_PHY_TYPE_40GBASE_CR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_SR4\t = BIT(I40E_PHY_TYPE_40GBASE_SR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_LR4\t = BIT(I40E_PHY_TYPE_40GBASE_LR4),\n-\tI40E_CAP_PHY_TYPE_1000BASE_SX\t = BIT(I40E_PHY_TYPE_1000BASE_SX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_LX\t = BIT(I40E_PHY_TYPE_1000BASE_LX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =\n-\t\t\t\t\t BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),\n-\tI40E_CAP_PHY_TYPE_20GBASE_KR2\t = BIT(I40E_PHY_TYPE_20GBASE_KR2)\n-};\n-\n struct i40e_phy_info {\n \tstruct i40e_link_status link_info;\n \tstruct i40e_link_status link_info_old;\n \tbool get_link_info;\n \tenum i40e_media_type media_type;\n \t/* all the phy types the NVM is capable of */\n-\tenum i40e_aq_capabilities_phy_type phy_types;\n-};\n-\n+\tu64 phy_types;\n+};\n+\n+#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)\n+#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)\n+#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)\n+#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)\n+#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)\n+#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)\n+#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)\n+#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)\n+#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)\n+#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)\n+/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some\n+ * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit\n+ * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,\n+ * a shift is needed to adjust for this with values larger than 31. The\n+ * only affected values are I40E_PHY_TYPE_25GBASE_*.\n+ */\n+#define I40E_PHY_TYPE_OFFSET 1\n+#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n+#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n+#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n+#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n #define I40E_HW_CAP_MAX_GPIO\t\t\t30\n /* Capabilities of a PF or a VF or the whole device */\n struct i40e_hw_capabilities {\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\nindex a994015..272d600 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\n@@ -85,6 +85,14 @@ static int i40evf_get_settings(struct net_device *netdev,\n \tcase I40E_LINK_SPEED_40GB:\n \t\tethtool_cmd_speed_set(ecmd, SPEED_40000);\n \t\tbreak;\n+\tcase I40E_LINK_SPEED_25GB:\n+#ifdef SPEED_25000\n+\t\tethtool_cmd_speed_set(ecmd, SPEED_25000);\n+#else\n+\t\tnetdev_info(netdev,\n+\t\t\t \"Speed is 25G, display not supported by this version of ethtool.\\n\");\n+#endif\n+\t\tbreak;\n \tcase I40E_LINK_SPEED_20GB:\n \t\tethtool_cmd_speed_set(ecmd, SPEED_20000);\n \t\tbreak;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c\nindex ddf478d..2059a8e 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c\n@@ -836,6 +836,9 @@ static void i40evf_print_link_message(struct i40evf_adapter *adapter)\n \tcase I40E_LINK_SPEED_40GB:\n \t\tspeed = \"40 G\";\n \t\tbreak;\n+\tcase I40E_LINK_SPEED_25GB:\n+\t\tspeed = \"25 G\";\n+\t\tbreak;\n \tcase I40E_LINK_SPEED_20GB:\n \t\tspeed = \"20 G\";\n \t\tbreak;\n", "prefixes": [ "next", "S53-V2", "2/5" ] }