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GET /api/patches/694717/?format=api
{ "id": 694717, "url": "http://patchwork.ozlabs.org/api/patches/694717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1479157609-30812-4-git-send-email-bimmy.pujari@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1479157609-30812-4-git-send-email-bimmy.pujari@intel.com>", "list_archive_url": null, "date": "2016-11-14T21:06:48", "name": "[next,S53-V2,4/5] i40e: Add functions which apply correct PHY access method for read and write operation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "3e8420fc26d12f5dae2148ee16c34ca29bfa79bd", "submitter": { "id": 68919, "url": "http://patchwork.ozlabs.org/api/people/68919/?format=api", "name": "Pujari, Bimmy", "email": "bimmy.pujari@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1479157609-30812-4-git-send-email-bimmy.pujari@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/694717/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/694717/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3tHjmr0Qwyz9t10\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 15 Nov 2016 08:08:44 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 7013825301;\n\tMon, 14 Nov 2016 21:08:42 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id K7t8O1DqRdwQ; Mon, 14 Nov 2016 21:08:34 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 378B6318C5;\n\tMon, 14 Nov 2016 21:08:32 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 0FF911C1F38\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 14 Nov 2016 21:08:30 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 0CB988A3CD\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 14 Nov 2016 21:08:30 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id uzOhY9sYJBoh for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 14 Nov 2016 21:08:25 +0000 (UTC)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id F30A78A776\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 14 Nov 2016 21:08:24 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga104.fm.intel.com with ESMTP; 14 Nov 2016 13:08:24 -0800", "from bimmy.jf.intel.com (HELO bimmy.linux1.jf.intel.com)\n\t([134.134.2.167])\n\tby orsmga005.jf.intel.com with ESMTP; 14 Nov 2016 13:08:24 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.31,640,1473145200\"; d=\"scan'208\";a=\"31193145\"", "From": "Bimmy Pujari <bimmy.pujari@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 14 Nov 2016 13:06:48 -0800", "Message-Id": "<1479157609-30812-4-git-send-email-bimmy.pujari@intel.com>", "X-Mailer": "git-send-email 2.4.11", "In-Reply-To": "<1479157609-30812-1-git-send-email-bimmy.pujari@intel.com>", "References": "<1479157609-30812-1-git-send-email-bimmy.pujari@intel.com>", "Cc": "Michal Kosiarz <michal.kosiarz@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S53-V2 4/5] i40e: Add functions which\n\tapply correct PHY access method for read and write operation", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Michal Kosiarz <michal.kosiarz@intel.com>\n\nDepending on external PHY type, register access method should be\ndifferent. Clause22 or Clause45 can be chosen for different PHYs.\nImplemented functions apply correct access method for used device.\n\nSigned-off-by: Michal Kosiarz <michal.kosiarz@intel.com>\nChange-ID: If39d5f0da9c0b905a8cbdc1ab89885535e7d0426\n---\n drivers/net/ethernet/intel/i40e/i40e_common.c | 72 ++++++++++++++++++++++\n drivers/net/ethernet/intel/i40e/i40e_prototype.h | 4 ++\n drivers/net/ethernet/intel/i40evf/i40e_prototype.h | 4 ++\n 3 files changed, 80 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex d9da786..59e766c 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -4676,6 +4676,78 @@ i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, u8 page,\n }\n \n /**\n+ * i40e_write_phy_register\n+ * @hw: pointer to the HW structure\n+ * @page: registers page number\n+ * @reg: register address in the page\n+ * @phy_adr: PHY address on MDIO interface\n+ * @value: PHY register value\n+ *\n+ * Writes value to specified PHY register\n+ **/\n+i40e_status i40e_write_phy_register(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 value)\n+{\n+\ti40e_status status;\n+\n+\tswitch (hw->device_id) {\n+\tcase I40E_DEV_ID_1G_BASE_T_X722:\n+\t\tstatus = i40e_write_phy_register_clause22(hw,\n+\t\t\treg, phy_addr, value);\n+\t\tbreak;\n+\tcase I40E_DEV_ID_10G_BASE_T:\n+\tcase I40E_DEV_ID_10G_BASE_T4:\n+\tcase I40E_DEV_ID_10G_BASE_T_X722:\n+\tcase I40E_DEV_ID_25G_B:\n+\tcase I40E_DEV_ID_25G_SFP28:\n+\t\tstatus = i40e_write_phy_register_clause45(hw,\n+\t\t\tpage, reg, phy_addr, value);\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = I40E_ERR_UNKNOWN_PHY;\n+\t\tbreak;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_read_phy_register\n+ * @hw: pointer to the HW structure\n+ * @page: registers page number\n+ * @reg: register address in the page\n+ * @phy_adr: PHY address on MDIO interface\n+ * @value: PHY register value\n+ *\n+ * Reads specified PHY register value\n+ **/\n+i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 *value)\n+{\n+\ti40e_status status;\n+\n+\tswitch (hw->device_id) {\n+\tcase I40E_DEV_ID_1G_BASE_T_X722:\n+\t\tstatus = i40e_read_phy_register_clause22(hw, reg, phy_addr,\n+\t\t\t\t\t\t\t value);\n+\t\tbreak;\n+\tcase I40E_DEV_ID_10G_BASE_T:\n+\tcase I40E_DEV_ID_10G_BASE_T4:\n+\tcase I40E_DEV_ID_10G_BASE_T_X722:\n+\tcase I40E_DEV_ID_25G_B:\n+\tcase I40E_DEV_ID_25G_SFP28:\n+\t\tstatus = i40e_read_phy_register_clause45(hw, page, reg,\n+\t\t\t\t\t\t\t phy_addr, value);\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = I40E_ERR_UNKNOWN_PHY;\n+\t\tbreak;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n * i40e_get_phy_address\n * @hw: pointer to the HW structure\n * @dev_num: PHY port num that address we want\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\nindex 4e641a6..bb5c982 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n@@ -373,6 +373,10 @@ i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,\n \t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 *value);\n i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,\n \t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 value);\n+i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 *value);\n+i40e_status i40e_write_phy_register(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 value);\n u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);\n i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n \t\t\t\t u32 time, u32 interval);\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\nindex d89d521..ee5d7fe 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n@@ -115,6 +115,10 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,\n \t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,\n \t\t\t\t u16 reg, u8 phy_addr, u16 value);\n+i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 *value);\n+i40e_status i40e_write_phy_register(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 value);\n u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);\n i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n \t\t\t\t u32 time, u32 interval);\n", "prefixes": [ "next", "S53-V2", "4/5" ] }