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GET /api/patches/691367/?format=api
{ "id": 691367, "url": "http://patchwork.ozlabs.org/api/patches/691367/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1478280968-8098-9-git-send-email-bimmy.pujari@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1478280968-8098-9-git-send-email-bimmy.pujari@intel.com>", "list_archive_url": null, "date": "2016-11-04T17:36:05", "name": "[next,S52,08/11] i40e: Fix for new bits set and sizing for 25G support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "f632e68ca44545a6bc120558631faaafca5d2aed", "submitter": { "id": 68919, "url": "http://patchwork.ozlabs.org/api/people/68919/?format=api", "name": "Pujari, Bimmy", "email": "bimmy.pujari@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1478280968-8098-9-git-send-email-bimmy.pujari@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/691367/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/691367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3t9TZS5dvTz9vG1\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 5 Nov 2016 04:38:08 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 3AB9B9635E;\n\tFri, 4 Nov 2016 17:38:07 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id WM7sdhGioCLt; Fri, 4 Nov 2016 17:38:03 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 90FF196376;\n\tFri, 4 Nov 2016 17:38:03 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 324A21C2774\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 4 Nov 2016 17:38:00 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 2BBB026D38\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 4 Nov 2016 17:38:00 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id v8m9Pki3We68 for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 4 Nov 2016 17:37:58 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 8B5A72A0B0\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 4 Nov 2016 17:37:58 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga101.jf.intel.com with ESMTP; 04 Nov 2016 10:37:42 -0700", "from bimmy.jf.intel.com (HELO bimmy.linux1.jf.intel.com)\n\t([134.134.2.167])\n\tby fmsmga002.fm.intel.com with ESMTP; 04 Nov 2016 10:37:42 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.31,444,1473145200\"; d=\"scan'208\";\n\ta=\"1080727999\"", "From": "Bimmy Pujari <bimmy.pujari@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 4 Nov 2016 10:36:05 -0700", "Message-Id": "<1478280968-8098-9-git-send-email-bimmy.pujari@intel.com>", "X-Mailer": "git-send-email 2.4.11", "In-Reply-To": "<1478280968-8098-1-git-send-email-bimmy.pujari@intel.com>", "References": "<1478280968-8098-1-git-send-email-bimmy.pujari@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S52 08/11] i40e: Fix for new bits set\n\tand sizing for 25G support", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Carolyn Wyborny <carolyn.wyborny@intel.com>\n\nThis patch adds FW API changes needed for 25G support\nand changes data type and bit settings defines for new\n25G support.\n\nSigned-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>\nChange-ID: I842dfdb3bb656bd2c79785d06104f955ea3b6f0a\n---\nTesting Hints :Check that code compiles and\n25g devices are recognized, initialized and show correct\nspeed.\n\n drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h | 22 ++++++-\n drivers/net/ethernet/intel/i40e/i40e_common.c | 4 +-\n drivers/net/ethernet/intel/i40e/i40e_type.h | 75 +++++++++++-----------\n .../net/ethernet/intel/i40evf/i40e_adminq_cmd.h | 22 ++++++-\n drivers/net/ethernet/intel/i40evf/i40e_type.h | 75 +++++++++++-----------\n 5 files changed, 115 insertions(+), 83 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\nindex 3016f89..a9f5d7e 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n@@ -1696,7 +1696,13 @@ struct i40e_aq_get_phy_abilities_resp {\n \t__le32\teeer_val;\n \tu8\td3_lpan;\n #define I40E_AQ_SET_PHY_D3_LPAN_ENA\t0x01\n-\tu8\treserved[3];\n+\tu8\tphy_type_ext;\n+#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n+#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n+#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n+#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n+\tu8\tmod_type_ext;\n+\tu8\text_comp_code;\n \tu8\tphy_id[4];\n \tu8\tmodule_type[3];\n \tu8\tqualified_module_count;\n@@ -1718,7 +1724,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */\n \t__le16\teee_capability;\n \t__le32\teeer;\n \tu8\tlow_power_ctrl;\n-\tu8\treserved[3];\n+\tu8\tphy_type_ext;\n+#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n+#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n+#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n+#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n+\tu8\treserved;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);\n@@ -1798,6 +1809,13 @@ struct i40e_aqc_get_link_status {\n #define I40E_AQ_LINK_TX_DRAINED\t\t0x01\n #define I40E_AQ_LINK_TX_FLUSHED\t\t0x03\n #define I40E_AQ_LINK_FORCED_40G\t\t0x10\n+/* 25G Error Codes */\n+#define I40E_AQ_25G_NO_ERR\t\t0X00\n+#define I40E_AQ_25G_NOT_PRESENT\t\t0X01\n+#define I40E_AQ_25G_NVM_CRC_ERR\t\t0X02\n+#define I40E_AQ_25G_SBUS_UCODE_ERR\t0X03\n+#define I40E_AQ_25G_SERDES_UCODE_ERR\t0X04\n+#define I40E_AQ_25G_NIMB_UCODE_ERR\t0X05\n \tu8\tloopback; /* use defines from i40e_aqc_set_lb_mode */\n \t__le16\tmax_frame_size;\n \tu8\tconfig;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex 33051ed..5ef7387 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -1610,8 +1610,10 @@ i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,\n \tif (hw->aq.asq_last_status == I40E_AQ_RC_EIO)\n \t\tstatus = I40E_ERR_UNKNOWN_PHY;\n \n-\tif (report_init)\n+\tif (report_init) {\n \t\thw->phy.phy_types = le32_to_cpu(abilities->phy_type);\n+\t\thw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);\n+\t}\n \n \treturn status;\n }\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h\nindex 49a4928..71795b1 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h\n@@ -213,51 +213,48 @@ struct i40e_link_status {\n #define I40E_MODULE_TYPE_1000BASE_T\t0x08\n };\n \n-enum i40e_aq_capabilities_phy_type {\n-\tI40E_CAP_PHY_TYPE_SGMII\t\t = BIT(I40E_PHY_TYPE_SGMII),\n-\tI40E_CAP_PHY_TYPE_1000BASE_KX\t = BIT(I40E_PHY_TYPE_1000BASE_KX),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KX4\t = BIT(I40E_PHY_TYPE_10GBASE_KX4),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KR\t = BIT(I40E_PHY_TYPE_10GBASE_KR),\n-\tI40E_CAP_PHY_TYPE_40GBASE_KR4\t = BIT(I40E_PHY_TYPE_40GBASE_KR4),\n-\tI40E_CAP_PHY_TYPE_XAUI\t\t = BIT(I40E_PHY_TYPE_XAUI),\n-\tI40E_CAP_PHY_TYPE_XFI\t\t = BIT(I40E_PHY_TYPE_XFI),\n-\tI40E_CAP_PHY_TYPE_SFI\t\t = BIT(I40E_PHY_TYPE_SFI),\n-\tI40E_CAP_PHY_TYPE_XLAUI\t\t = BIT(I40E_PHY_TYPE_XLAUI),\n-\tI40E_CAP_PHY_TYPE_XLPPI\t\t = BIT(I40E_PHY_TYPE_XLPPI),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_AOC\t = BIT(I40E_PHY_TYPE_10GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_40GBASE_AOC\t = BIT(I40E_PHY_TYPE_40GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_100BASE_TX\t = BIT(I40E_PHY_TYPE_100BASE_TX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T\t = BIT(I40E_PHY_TYPE_1000BASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_T\t = BIT(I40E_PHY_TYPE_10GBASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SR\t = BIT(I40E_PHY_TYPE_10GBASE_SR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_LR\t = BIT(I40E_PHY_TYPE_10GBASE_LR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1\t = BIT(I40E_PHY_TYPE_10GBASE_CR1),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4\t = BIT(I40E_PHY_TYPE_40GBASE_CR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_SR4\t = BIT(I40E_PHY_TYPE_40GBASE_SR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_LR4\t = BIT(I40E_PHY_TYPE_40GBASE_LR4),\n-\tI40E_CAP_PHY_TYPE_1000BASE_SX\t = BIT(I40E_PHY_TYPE_1000BASE_SX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_LX\t = BIT(I40E_PHY_TYPE_1000BASE_LX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =\n-\t\t\t\t\t BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),\n-\tI40E_CAP_PHY_TYPE_20GBASE_KR2\t = BIT(I40E_PHY_TYPE_20GBASE_KR2),\n-\tI40E_CAP_PHY_TYPE_25GBASE_KR\t = BIT(I40E_PHY_TYPE_25GBASE_KR),\n-\tI40E_CAP_PHY_TYPE_25GBASE_CR\t = BIT(I40E_PHY_TYPE_25GBASE_CR),\n-\tI40E_CAP_PHY_TYPE_25GBASE_SR\t = BIT(I40E_PHY_TYPE_25GBASE_SR),\n-\tI40E_CAP_PHY_TYPE_25GBASE_LR\t = BIT(I40E_PHY_TYPE_25GBASE_LR),\n-};\n-\n struct i40e_phy_info {\n \tstruct i40e_link_status link_info;\n \tstruct i40e_link_status link_info_old;\n \tbool get_link_info;\n \tenum i40e_media_type media_type;\n \t/* all the phy types the NVM is capable of */\n-\tenum i40e_aq_capabilities_phy_type phy_types;\n-};\n-\n+\tu64 phy_types;\n+};\n+\n+#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)\n+#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)\n+#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)\n+#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)\n+#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)\n+#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)\n+#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)\n+#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)\n+#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)\n+#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)\n+#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)\n+#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)\n+#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)\n+#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)\n #define I40E_HW_CAP_MAX_GPIO\t\t\t30\n /* Capabilities of a PF or a VF or the whole device */\n struct i40e_hw_capabilities {\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\nindex afe3706..7242325 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n@@ -1693,7 +1693,13 @@ struct i40e_aq_get_phy_abilities_resp {\n \t__le32\teeer_val;\n \tu8\td3_lpan;\n #define I40E_AQ_SET_PHY_D3_LPAN_ENA\t0x01\n-\tu8\treserved[3];\n+\tu8\tphy_type_ext;\n+#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n+#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n+#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n+#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n+\tu8\tmod_type_ext;\n+\tu8\text_comp_code;\n \tu8\tphy_id[4];\n \tu8\tmodule_type[3];\n \tu8\tqualified_module_count;\n@@ -1715,7 +1721,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */\n \t__le16\teee_capability;\n \t__le32\teeer;\n \tu8\tlow_power_ctrl;\n-\tu8\treserved[3];\n+\tu8\tphy_type_ext;\n+#define I40E_AQ_PHY_TYPE_EXT_25G_KR\t0X01\n+#define I40E_AQ_PHY_TYPE_EXT_25G_CR\t0X02\n+#define I40E_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n+#define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n+\tu8\treserved;\n };\n \n I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);\n@@ -1795,6 +1806,13 @@ struct i40e_aqc_get_link_status {\n #define I40E_AQ_LINK_TX_DRAINED\t\t0x01\n #define I40E_AQ_LINK_TX_FLUSHED\t\t0x03\n #define I40E_AQ_LINK_FORCED_40G\t\t0x10\n+/* 25G Error Codes */\n+#define I40E_AQ_25G_NO_ERR\t\t0X00\n+#define I40E_AQ_25G_NOT_PRESENT\t\t0X01\n+#define I40E_AQ_25G_NVM_CRC_ERR\t\t0X02\n+#define I40E_AQ_25G_SBUS_UCODE_ERR\t0X03\n+#define I40E_AQ_25G_SERDES_UCODE_ERR\t0X04\n+#define I40E_AQ_25G_NIMB_UCODE_ERR\t0X05\n \tu8\tloopback; /* use defines from i40e_aqc_set_lb_mode */\n \t__le16\tmax_frame_size;\n \tu8\tconfig;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h\nindex f1dc74e..493c803 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h\n@@ -187,51 +187,48 @@ struct i40e_link_status {\n #define I40E_MODULE_TYPE_1000BASE_T\t0x08\n };\n \n-enum i40e_aq_capabilities_phy_type {\n-\tI40E_CAP_PHY_TYPE_SGMII\t\t = BIT(I40E_PHY_TYPE_SGMII),\n-\tI40E_CAP_PHY_TYPE_1000BASE_KX\t = BIT(I40E_PHY_TYPE_1000BASE_KX),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KX4\t = BIT(I40E_PHY_TYPE_10GBASE_KX4),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KR\t = BIT(I40E_PHY_TYPE_10GBASE_KR),\n-\tI40E_CAP_PHY_TYPE_40GBASE_KR4\t = BIT(I40E_PHY_TYPE_40GBASE_KR4),\n-\tI40E_CAP_PHY_TYPE_XAUI\t\t = BIT(I40E_PHY_TYPE_XAUI),\n-\tI40E_CAP_PHY_TYPE_XFI\t\t = BIT(I40E_PHY_TYPE_XFI),\n-\tI40E_CAP_PHY_TYPE_SFI\t\t = BIT(I40E_PHY_TYPE_SFI),\n-\tI40E_CAP_PHY_TYPE_XLAUI\t\t = BIT(I40E_PHY_TYPE_XLAUI),\n-\tI40E_CAP_PHY_TYPE_XLPPI\t\t = BIT(I40E_PHY_TYPE_XLPPI),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_AOC\t = BIT(I40E_PHY_TYPE_10GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_40GBASE_AOC\t = BIT(I40E_PHY_TYPE_40GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_100BASE_TX\t = BIT(I40E_PHY_TYPE_100BASE_TX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T\t = BIT(I40E_PHY_TYPE_1000BASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_T\t = BIT(I40E_PHY_TYPE_10GBASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SR\t = BIT(I40E_PHY_TYPE_10GBASE_SR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_LR\t = BIT(I40E_PHY_TYPE_10GBASE_LR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1\t = BIT(I40E_PHY_TYPE_10GBASE_CR1),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4\t = BIT(I40E_PHY_TYPE_40GBASE_CR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_SR4\t = BIT(I40E_PHY_TYPE_40GBASE_SR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_LR4\t = BIT(I40E_PHY_TYPE_40GBASE_LR4),\n-\tI40E_CAP_PHY_TYPE_1000BASE_SX\t = BIT(I40E_PHY_TYPE_1000BASE_SX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_LX\t = BIT(I40E_PHY_TYPE_1000BASE_LX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =\n-\t\t\t\t\t BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),\n-\tI40E_CAP_PHY_TYPE_20GBASE_KR2\t = BIT(I40E_PHY_TYPE_20GBASE_KR2),\n-\tI40E_CAP_PHY_TYPE_25GBASE_KR\t = BIT(I40E_PHY_TYPE_25GBASE_KR),\n-\tI40E_CAP_PHY_TYPE_25GBASE_CR\t = BIT(I40E_PHY_TYPE_25GBASE_CR),\n-\tI40E_CAP_PHY_TYPE_25GBASE_SR\t = BIT(I40E_PHY_TYPE_25GBASE_SR),\n-\tI40E_CAP_PHY_TYPE_25GBASE_LR\t = BIT(I40E_PHY_TYPE_25GBASE_LR),\n-};\n-\n struct i40e_phy_info {\n \tstruct i40e_link_status link_info;\n \tstruct i40e_link_status link_info_old;\n \tbool get_link_info;\n \tenum i40e_media_type media_type;\n \t/* all the phy types the NVM is capable of */\n-\tenum i40e_aq_capabilities_phy_type phy_types;\n-};\n-\n+\tu64 phy_types;\n+};\n+\n+#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)\n+#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)\n+#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)\n+#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)\n+#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)\n+#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)\n+#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)\n+#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)\n+#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)\n+#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)\n+#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)\n+#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)\n+#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)\n+#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)\n #define I40E_HW_CAP_MAX_GPIO\t\t\t30\n /* Capabilities of a PF or a VF or the whole device */\n struct i40e_hw_capabilities {\n", "prefixes": [ "next", "S52", "08/11" ] }