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GET /api/patches/686802/?format=api
{ "id": 686802, "url": "http://patchwork.ozlabs.org/api/patches/686802/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1477436933-13679-7-git-send-email-bimmy.pujari@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1477436933-13679-7-git-send-email-bimmy.pujari@intel.com>", "list_archive_url": null, "date": "2016-10-25T23:08:51", "name": "[next,S51-V2,6/8] i40e: Add Clause22 implementation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "0633659ea3b09da9c2055e7cb9082491072e65d4", "submitter": { "id": 68919, "url": "http://patchwork.ozlabs.org/api/people/68919/?format=api", "name": "Pujari, Bimmy", "email": "bimmy.pujari@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1477436933-13679-7-git-send-email-bimmy.pujari@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/686802/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/686802/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3t3TQh1ZJzz9sCZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 26 Oct 2016 10:10:36 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 748EB920D8;\n\tTue, 25 Oct 2016 23:10:34 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id xTYfWIl84Ogm; Tue, 25 Oct 2016 23:10:31 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 3E870920BE;\n\tTue, 25 Oct 2016 23:10:30 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 0E79A1CF861\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 25 Oct 2016 23:10:27 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id F054231B5A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 25 Oct 2016 23:10:26 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id vegpO1qE1Wws for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 25 Oct 2016 23:10:24 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 9567831C4B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 25 Oct 2016 23:10:23 +0000 (UTC)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga105.fm.intel.com with ESMTP; 25 Oct 2016 16:10:22 -0700", "from bimmy.jf.intel.com (HELO bimmy.linux1.jf.intel.com)\n\t([134.134.2.167])\n\tby fmsmga006.fm.intel.com with ESMTP; 25 Oct 2016 16:10:22 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.31,399,1473145200\"; d=\"scan'208\";a=\"23607189\"", "From": "Bimmy Pujari <bimmy.pujari@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Tue, 25 Oct 2016 16:08:51 -0700", "Message-Id": "<1477436933-13679-7-git-send-email-bimmy.pujari@intel.com>", "X-Mailer": "git-send-email 2.4.11", "In-Reply-To": "<1477436933-13679-1-git-send-email-bimmy.pujari@intel.com>", "References": "<1477436933-13679-1-git-send-email-bimmy.pujari@intel.com>", "Cc": "Matt Jared <matthew.a.jared@intel.com>,\n\tMichal Kosiarz <michal.kosiarz@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S51-V2 6/8] i40e: Add Clause22\n\timplementation", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Michal Kosiarz <michal.kosiarz@intel.com>\n\nSome external PHYs require Clause22 method for accessing registers.\nThis patch also adds some defines to support blink led on devices using\n10CBaseT PHY.\n\nSigned-off-by: Michal Kosiarz <michal.kosiarz@intel.com>\nSigned-off-by: Matt Jared <matthew.a.jared@intel.com>\nChange-ID: I868a4326911900f6c89e7e522fda4968b0825f14\n---\n drivers/net/ethernet/intel/i40e/i40e_common.c | 180 +++++++++++++++++------\n drivers/net/ethernet/intel/i40e/i40e_prototype.h | 12 +-\n drivers/net/ethernet/intel/i40e/i40e_type.h | 19 ++-\n 3 files changed, 159 insertions(+), 52 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex 98791ba..838dc70 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -4396,7 +4396,99 @@ i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,\n }\n \n /**\n- * i40e_read_phy_register\n+ * i40e_read_phy_register_clause22\n+ * @hw: pointer to the HW structure\n+ * @reg: register address in the page\n+ * @phy_adr: PHY address on MDIO interface\n+ * @value: PHY register value\n+ *\n+ * Reads specified PHY register value\n+ **/\n+i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,\n+\t\t\t\t\tu16 reg, u8 phy_addr, u16 *value)\n+{\n+\ti40e_status status = I40E_ERR_TIMEOUT;\n+\tu8 port_num = (u8)hw->func_caps.mdio_port_num;\n+\tu32 command = 0;\n+\tu16 retry = 1000;\n+\n+\tcommand = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n+\t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n+\t\t (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |\n+\t\t (I40E_MDIO_CLAUSE22_STCODE_MASK) |\n+\t\t (I40E_GLGEN_MSCA_MDICMD_MASK);\n+\twr32(hw, I40E_GLGEN_MSCA(port_num), command);\n+\tdo {\n+\t\tcommand = rd32(hw, I40E_GLGEN_MSCA(port_num));\n+\t\tif (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {\n+\t\t\tstatus = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tudelay(10);\n+\t\tretry--;\n+\t} while (retry);\n+\n+\tif (status) {\n+\t\ti40e_debug(hw, I40E_DEBUG_PHY,\n+\t\t\t \"PHY: Can't write command to external PHY.\\n\");\n+\t\tgoto phy_read_end;\n+\t}\n+\n+\tif (!status) {\n+\t\tcommand = rd32(hw, I40E_GLGEN_MSRWD(port_num));\n+\t\t*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>\n+\t\t\t I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;\n+\t} else {\n+\t\ti40e_debug(hw, I40E_DEBUG_PHY,\n+\t\t\t \"PHY: Can't read register value from external PHY.\\n\");\n+\t}\n+\n+phy_read_end:\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_write_phy_register_clause22\n+ * @hw: pointer to the HW structure\n+ * @reg: register address in the page\n+ * @phy_adr: PHY address on MDIO interface\n+ * @value: PHY register value\n+ *\n+ * Writes specified PHY register value\n+ **/\n+i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,\n+\t\t\t\t\tu16 reg, u8 phy_addr, u16 value)\n+{\n+\ti40e_status status = I40E_ERR_TIMEOUT;\n+\tu8 port_num = (u8)hw->func_caps.mdio_port_num;\n+\tu32 command = 0;\n+\tu16 retry = 1000;\n+\n+\tcommand = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;\n+\twr32(hw, I40E_GLGEN_MSRWD(port_num), command);\n+\n+\tcommand = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n+\t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n+\t\t (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |\n+\t\t (I40E_MDIO_CLAUSE22_STCODE_MASK) |\n+\t\t (I40E_GLGEN_MSCA_MDICMD_MASK);\n+\n+\twr32(hw, I40E_GLGEN_MSCA(port_num), command);\n+\tdo {\n+\t\tcommand = rd32(hw, I40E_GLGEN_MSCA(port_num));\n+\t\tif (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {\n+\t\t\tstatus = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tudelay(10);\n+\t\tretry--;\n+\t} while (retry);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_read_phy_register_clause45\n * @hw: pointer to the HW structure\n * @page: registers page number\n * @reg: register address in the page\n@@ -4405,9 +4497,8 @@ i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,\n *\n * Reads specified PHY register value\n **/\n-i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n-\t\t\t\t u8 page, u16 reg, u8 phy_addr,\n-\t\t\t\t u16 *value)\n+i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 *value)\n {\n \ti40e_status status = I40E_ERR_TIMEOUT;\n \tu32 command = 0;\n@@ -4417,8 +4508,8 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n \tcommand = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |\n \t\t (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n \t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n-\t\t (I40E_MDIO_OPCODE_ADDRESS) |\n-\t\t (I40E_MDIO_STCODE) |\n+\t\t (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |\n+\t\t (I40E_MDIO_CLAUSE45_STCODE_MASK) |\n \t\t (I40E_GLGEN_MSCA_MDICMD_MASK) |\n \t\t (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);\n \twr32(hw, I40E_GLGEN_MSCA(port_num), command);\n@@ -4440,8 +4531,8 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n \n \tcommand = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n \t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n-\t\t (I40E_MDIO_OPCODE_READ) |\n-\t\t (I40E_MDIO_STCODE) |\n+\t\t (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |\n+\t\t (I40E_MDIO_CLAUSE45_STCODE_MASK) |\n \t\t (I40E_GLGEN_MSCA_MDICMD_MASK) |\n \t\t (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);\n \tstatus = I40E_ERR_TIMEOUT;\n@@ -4471,7 +4562,7 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n }\n \n /**\n- * i40e_write_phy_register\n+ * i40e_write_phy_register_clause45\n * @hw: pointer to the HW structure\n * @page: registers page number\n * @reg: register address in the page\n@@ -4480,9 +4571,8 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n *\n * Writes value to specified PHY register\n **/\n-i40e_status i40e_write_phy_register(struct i40e_hw *hw,\n-\t\t\t\t u8 page, u16 reg, u8 phy_addr,\n-\t\t\t\t u16 value)\n+i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 value)\n {\n \ti40e_status status = I40E_ERR_TIMEOUT;\n \tu32 command = 0;\n@@ -4492,8 +4582,8 @@ i40e_status i40e_write_phy_register(struct i40e_hw *hw,\n \tcommand = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |\n \t\t (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n \t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n-\t\t (I40E_MDIO_OPCODE_ADDRESS) |\n-\t\t (I40E_MDIO_STCODE) |\n+\t\t (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |\n+\t\t (I40E_MDIO_CLAUSE45_STCODE_MASK) |\n \t\t (I40E_GLGEN_MSCA_MDICMD_MASK) |\n \t\t (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);\n \twr32(hw, I40E_GLGEN_MSCA(port_num), command);\n@@ -4517,8 +4607,8 @@ i40e_status i40e_write_phy_register(struct i40e_hw *hw,\n \n \tcommand = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n \t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n-\t\t (I40E_MDIO_OPCODE_WRITE) |\n-\t\t (I40E_MDIO_STCODE) |\n+\t\t (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |\n+\t\t (I40E_MDIO_CLAUSE45_STCODE_MASK) |\n \t\t (I40E_GLGEN_MSCA_MDICMD_MASK) |\n \t\t (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);\n \tstatus = I40E_ERR_TIMEOUT;\n@@ -4580,14 +4670,16 @@ i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n \n \tfor (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,\n \t led_addr++) {\n-\t\tstatus = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\tled_addr, phy_addr, &led_reg);\n+\t\tstatus = i40e_read_phy_register_clause45(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t\t &led_reg);\n \t\tif (status)\n \t\t\tgoto phy_blinking_end;\n \t\tled_ctl = led_reg;\n \t\tif (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {\n \t\t\tled_reg = 0;\n-\t\t\tstatus = i40e_write_phy_register(hw,\n+\t\t\tstatus = i40e_write_phy_register_clause45(hw,\n \t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n \t\t\t\t\t\t\t led_addr, phy_addr,\n \t\t\t\t\t\t\t led_reg);\n@@ -4599,20 +4691,18 @@ i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n \n \tif (time > 0 && interval > 0) {\n \t\tfor (i = 0; i < time * 1000; i += interval) {\n-\t\t\tstatus = i40e_read_phy_register(hw,\n-\t\t\t\t\t\t\tI40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t\tled_addr, phy_addr,\n-\t\t\t\t\t\t\t&led_reg);\n+\t\t\tstatus = i40e_read_phy_register_clause45(hw,\n+\t\t\t\t\t\tI40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\tled_addr, phy_addr, &led_reg);\n \t\t\tif (status)\n \t\t\t\tgoto restore_config;\n \t\t\tif (led_reg & I40E_PHY_LED_MANUAL_ON)\n \t\t\t\tled_reg = 0;\n \t\t\telse\n \t\t\t\tled_reg = I40E_PHY_LED_MANUAL_ON;\n-\t\t\tstatus = i40e_write_phy_register(hw,\n-\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t\t led_addr, phy_addr,\n-\t\t\t\t\t\t\t led_reg);\n+\t\t\tstatus = i40e_write_phy_register_clause45(hw,\n+\t\t\t\t\t\tI40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\tled_addr, phy_addr, led_reg);\n \t\t\tif (status)\n \t\t\t\tgoto restore_config;\n \t\t\tmsleep(interval);\n@@ -4620,8 +4710,9 @@ i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n \t}\n \n restore_config:\n-\tstatus = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,\n-\t\t\t\t\t phy_addr, led_ctl);\n+\tstatus = i40e_write_phy_register_clause45(hw,\n+\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t led_addr, phy_addr, led_ctl);\n \n phy_blinking_end:\n \treturn status;\n@@ -4652,8 +4743,10 @@ i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,\n \n \tfor (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,\n \t temp_addr++) {\n-\t\tstatus = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\ttemp_addr, phy_addr, ®_val);\n+\t\tstatus = i40e_read_phy_register_clause45(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t temp_addr, phy_addr,\n+\t\t\t\t\t\t\t ®_val);\n \t\tif (status)\n \t\t\treturn status;\n \t\t*val = reg_val;\n@@ -4686,41 +4779,42 @@ i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,\n \ti = rd32(hw, I40E_PFGEN_PORTNUM);\n \tport_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);\n \tphy_addr = i40e_get_phy_address(hw, port_num);\n-\n-\tstatus = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,\n-\t\t\t\t\tphy_addr, &led_reg);\n+\tstatus = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t led_addr, phy_addr, &led_reg);\n \tif (status)\n \t\treturn status;\n \tled_ctl = led_reg;\n \tif (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {\n \t\tled_reg = 0;\n-\t\tstatus = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t\t led_addr, phy_addr, led_reg);\n+\t\tstatus = i40e_write_phy_register_clause45(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t\t led_reg);\n \t\tif (status)\n \t\t\treturn status;\n \t}\n-\tstatus = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\tled_addr, phy_addr, &led_reg);\n+\tstatus = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t led_addr, phy_addr, &led_reg);\n \tif (status)\n \t\tgoto restore_config;\n \tif (on)\n \t\tled_reg = I40E_PHY_LED_MANUAL_ON;\n \telse\n \t\tled_reg = 0;\n-\tstatus = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n-\t\t\t\t\t led_addr, phy_addr, led_reg);\n+\tstatus = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t led_addr, phy_addr, led_reg);\n \tif (status)\n \t\tgoto restore_config;\n \tif (mode & I40E_PHY_LED_MODE_ORIG) {\n \t\tled_ctl = (mode & I40E_PHY_LED_MODE_MASK);\n-\t\tstatus = i40e_write_phy_register(hw,\n+\t\tstatus = i40e_write_phy_register_clause45(hw,\n \t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n \t\t\t\t\t\t led_addr, phy_addr, led_ctl);\n \t}\n \treturn status;\n restore_config:\n-\tstatus = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,\n-\t\t\t\t\t phy_addr, led_ctl);\n+\tstatus = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t led_addr, phy_addr, led_ctl);\n \treturn status;\n }\n \ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\nindex 4660c5a..b1bf64e 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n@@ -362,10 +362,14 @@ i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,\n \t\t\t\tu32 reg_addr, u32 reg_val,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);\n-i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,\n-\t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n-i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,\n-\t\t\t\t u16 reg, u8 phy_addr, u16 value);\n+i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,\n+\t\t\t\t\tu16 reg, u8 phy_addr, u16 *value);\n+i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,\n+\t\t\t\t\tu16 reg, u8 phy_addr, u16 value);\n+i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 *value);\n+i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,\n+\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 value);\n u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);\n i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n \t\t\t\t u32 time, u32 interval);\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h\nindex d9a2660..cf085cd 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h\n@@ -90,14 +90,23 @@ enum i40e_debug_mask {\n \tI40E_DEBUG_ALL\t\t\t= 0xFFFFFFFF\n };\n \n-#define I40E_MDIO_STCODE 0\n-#define I40E_MDIO_OPCODE_ADDRESS 0\n-#define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \\\n+#define I40E_MDIO_CLAUSE22_STCODE_MASK\tI40E_MASK(1, \\\n+\t\t\t\t\t\t I40E_GLGEN_MSCA_STCODE_SHIFT)\n+#define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK\tI40E_MASK(1, \\\n \t\t\t\t\t\t I40E_GLGEN_MSCA_OPCODE_SHIFT)\n-#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \\\n+#define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK\tI40E_MASK(2, \\\n \t\t\t\t\t\t I40E_GLGEN_MSCA_OPCODE_SHIFT)\n-#define I40E_MDIO_OPCODE_READ I40E_MASK(3, \\\n+\n+#define I40E_MDIO_CLAUSE45_STCODE_MASK\tI40E_MASK(0, \\\n+\t\t\t\t\t\t I40E_GLGEN_MSCA_STCODE_SHIFT)\n+#define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK\tI40E_MASK(0, \\\n+\t\t\t\t\t\t I40E_GLGEN_MSCA_OPCODE_SHIFT)\n+#define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK\tI40E_MASK(1, \\\n \t\t\t\t\t\t I40E_GLGEN_MSCA_OPCODE_SHIFT)\n+#define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK\tI40E_MASK(2, \\\n+\t\t\t\t\t\tI40E_GLGEN_MSCA_OPCODE_SHIFT)\n+#define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \\\n+\t\t\t\t\t\tI40E_GLGEN_MSCA_OPCODE_SHIFT)\n \n #define I40E_PHY_COM_REG_PAGE 0x1E\n #define I40E_PHY_LED_LINK_MODE_MASK 0xF0\n", "prefixes": [ "next", "S51-V2", "6/8" ] }