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GET /api/patches/680575/?format=api
{ "id": 680575, "url": "http://patchwork.ozlabs.org/api/patches/680575/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20161010215403.27440.5694.stgit@localhost6.localdomain6/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20161010215403.27440.5694.stgit@localhost6.localdomain6>", "list_archive_url": null, "date": "2016-10-10T21:54:03", "name": "[v3] ixgbe: use link instead of I2C combined abstraction", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "29c302c10bc9adbcad10e76e683b2955da3ee82e", "submitter": { "id": 1670, "url": "http://patchwork.ozlabs.org/api/people/1670/?format=api", "name": "Tantilov, Emil S", "email": "emil.s.tantilov@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20161010215403.27440.5694.stgit@localhost6.localdomain6/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/680575/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/680575/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3stDL210Rvz9s9N\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 11 Oct 2016 08:49:29 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 6D5E18AF33;\n\tMon, 10 Oct 2016 21:49:28 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id REfqntOY4ykO; Mon, 10 Oct 2016 21:49:26 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id A6D648ADAB;\n\tMon, 10 Oct 2016 21:49:26 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id E0E0B1C2011\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 10 Oct 2016 21:49:23 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D918A8ADAB\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 10 Oct 2016 21:49:23 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id MV5nl1+peUES for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 10 Oct 2016 21:49:22 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id 9991E8A6BA\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 10 Oct 2016 21:49:22 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga105.fm.intel.com with ESMTP; 10 Oct 2016 14:49:22 -0700", "from estantil-desk3.jf.intel.com (HELO localhost6.localdomain6)\n\t([134.134.3.186])\n\tby orsmga005.jf.intel.com with ESMTP; 10 Oct 2016 14:49:22 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.31,474,1473145200\"; d=\"scan'208\";a=\"18247847\"", "From": "Emil Tantilov <emil.s.tantilov@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 10 Oct 2016 14:54:03 -0700", "Message-ID": "<20161010215403.27440.5694.stgit@localhost6.localdomain6>", "User-Agent": "StGit/0.17.1-17-ge4e0", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH v3] ixgbe: use link instead of I2C\n\tcombined abstraction", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "Introduce ixgbe_link_operations struct with the following changes:\n\n\tread_i2c_combined\t\t=> read_link\n\tread_i2c_combined_unlocked\t=> read_link_unlocked\n\twrite_i2c_combined\t\t=> write_link\n\twrite_i2c_combined_unlocked\t=> write_link_unlocked\n\nThis will allow X550EM_a to override these methods for MDIO access\nwhile X550EM_x provides methods to use I2C combined access. This\nalso adds a new structure, ixgbe_link_info, to hold information\nabout the link. Initially this is just method pointers and a bus\naddress.\n\nThe functions involved in combined I2C accesses were moved from\nixgbe_phy.c to ixgbe_x550.c. The underlying functions that carry\nout the combined I2C accesses were left in ixgbe_phy.c because\nthey share some functions with other I2C methods.\n\nv2 - set hw->link.ops in probe.\nv3 - check ii->link_ops before setting it since we don't have it\nfor all devices.\n\nSigned-off-by: Emil Tantilov <emil.s.tantilov@intel.com>\n---\n drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 2 \n drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c | 68 +---------------\n drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | 12 +--\n drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 26 +++++-\n drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c | 106 ++++++++++++++++++++++---\n 5 files changed, 124 insertions(+), 90 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\nindex f6f18ca..5227b61 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\n@@ -9480,6 +9480,8 @@ static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n \thw->mac.ops = *ii->mac_ops;\n \thw->mac.type = ii->mac;\n \thw->mvals = ii->mvals;\n+\tif (ii->link_ops)\n+\t\thw->link.ops = *ii->link_ops;\n \n \t/* EEPROM */\n \thw->eeprom.ops = *ii->eeprom_ops;\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c\nindex b883b31..78edf5b 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c\n@@ -109,8 +109,8 @@ static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)\n *\n * Returns an error code on error.\n */\n-static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,\n-\t\t\t\t\t u16 reg, u16 *val, bool lock)\n+s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,\n+\t\t\t\t\tu16 reg, u16 *val, bool lock)\n {\n \tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n \tint max_retry = 10;\n@@ -178,36 +178,6 @@ fail:\n }\n \n /**\n- * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation\n- * @hw: pointer to the hardware structure\n- * @addr: I2C bus address to read from\n- * @reg: I2C device register to read from\n- * @val: pointer to location to receive read value\n- *\n- * Returns an error code on error.\n- */\n-s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,\n-\t\t\t\t u16 reg, u16 *val)\n-{\n-\treturn ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);\n-}\n-\n-/**\n- * ixgbe_read_i2c_combined_generic_unlocked - Unlocked I2C read combined\n- * @hw: pointer to the hardware structure\n- * @addr: I2C bus address to read from\n- * @reg: I2C device register to read from\n- * @val: pointer to location to receive read value\n- *\n- * Returns an error code on error.\n- */\n-s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,\n-\t\t\t\t\t u16 reg, u16 *val)\n-{\n-\treturn ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);\n-}\n-\n-/**\n * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to write to\n@@ -217,8 +187,8 @@ s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,\n *\n * Returns an error code on error.\n */\n-static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,\n-\t\t\t\t\t\tu16 reg, u16 val, bool lock)\n+s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,\n+\t\t\t\t\t u16 reg, u16 val, bool lock)\n {\n \tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n \tint max_retry = 1;\n@@ -273,36 +243,6 @@ fail:\n }\n \n /**\n- * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation\n- * @hw: pointer to the hardware structure\n- * @addr: I2C bus address to write to\n- * @reg: I2C device register to write to\n- * @val: value to write\n- *\n- * Returns an error code on error.\n- */\n-s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,\n-\t\t\t\t u8 addr, u16 reg, u16 val)\n-{\n-\treturn ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);\n-}\n-\n-/**\n- * ixgbe_write_i2c_combined_generic_unlocked - Unlocked I2C write combined\n- * @hw: pointer to the hardware structure\n- * @addr: I2C bus address to write to\n- * @reg: I2C device register to write to\n- * @val: value to write\n- *\n- * Returns an error code on error.\n- */\n-s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,\n-\t\t\t\t\t u8 addr, u16 reg, u16 val)\n-{\n-\treturn ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);\n-}\n-\n-/**\n * ixgbe_identify_phy_generic - Get physical layer module\n * @hw: pointer to hardware structure\n *\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h\nindex cc735ec..ecf05f8 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h\n@@ -195,12 +195,8 @@ s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 *sff8472_data);\n s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t u8 eeprom_data);\n-s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,\n-\t\t\t\t u16 reg, u16 *val);\n-s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,\n-\t\t\t\t\t u16 reg, u16 *val);\n-s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,\n-\t\t\t\t u16 reg, u16 val);\n-s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,\n-\t\t\t\t\t u16 reg, u16 val);\n+s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,\n+\t\t\t\t\tu16 *val, bool lock);\n+s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,\n+\t\t\t\t\t u16 val, bool lock);\n #endif /* _IXGBE_PHY_H_ */\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\nindex 998708c..fe1d13e 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\n@@ -3395,16 +3395,28 @@ struct ixgbe_phy_operations {\n \ts32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);\n \ts32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);\n \ts32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);\n-\ts32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);\n-\ts32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);\n \ts32 (*check_overtemp)(struct ixgbe_hw *);\n \ts32 (*set_phy_power)(struct ixgbe_hw *, bool on);\n \ts32 (*enter_lplu)(struct ixgbe_hw *);\n \ts32 (*handle_lasi)(struct ixgbe_hw *hw);\n-\ts32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,\n-\t\t\t\t\t u16 *value);\n-\ts32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,\n-\t\t\t\t\t u16 value);\n+\ts32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,\n+\t\t\t\t u8 *value);\n+\ts32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,\n+\t\t\t\t u8 value);\n+};\n+\n+struct ixgbe_link_operations {\n+\ts32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);\n+\ts32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,\n+\t\t\t\t u16 *val);\n+\ts32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);\n+\ts32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,\n+\t\t\t\t u16 val);\n+};\n+\n+struct ixgbe_link_info {\n+\tstruct ixgbe_link_operations ops;\n+\tu8 addr;\n };\n \n struct ixgbe_eeprom_info {\n@@ -3508,6 +3520,7 @@ struct ixgbe_hw {\n \tstruct ixgbe_addr_filter_info\taddr_ctrl;\n \tstruct ixgbe_fc_info\t\tfc;\n \tstruct ixgbe_phy_info\t\tphy;\n+\tstruct ixgbe_link_info\t\tlink;\n \tstruct ixgbe_eeprom_info\teeprom;\n \tstruct ixgbe_bus_info\t\tbus;\n \tstruct ixgbe_mbx_info\t\tmbx;\n@@ -3531,6 +3544,7 @@ struct ixgbe_info {\n \tconst struct ixgbe_eeprom_operations\t*eeprom_ops;\n \tconst struct ixgbe_phy_operations\t*phy_ops;\n \tconst struct ixgbe_mbx_operations\t*mbx_ops;\n+\tconst struct ixgbe_link_operations\t*link_ops;\n \tconst u32\t\t\t*mvals;\n };\n \ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\nindex d81c35f..6206b51 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\n@@ -36,6 +36,23 @@ static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)\n {\n \tstruct ixgbe_mac_info *mac = &hw->mac;\n \tstruct ixgbe_phy_info *phy = &hw->phy;\n+\tstruct ixgbe_link_info *link = &hw->link;\n+\n+\t/* Start with X540 invariants, since so simular */\n+\tixgbe_get_invariants_X540(hw);\n+\n+\tif (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)\n+\t\tphy->ops.set_phy_power = NULL;\n+\n+\tlink->addr = IXGBE_CS4227;\n+\n+\treturn 0;\n+}\n+\n+static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_mac_info *mac = &hw->mac;\n+\tstruct ixgbe_phy_info *phy = &hw->phy;\n \n \t/* Start with X540 invariants, since so simular */\n \tixgbe_get_invariants_X540(hw);\n@@ -72,8 +89,7 @@ static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)\n */\n static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)\n {\n-\treturn hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,\n-\t\t\t\t\t\t value);\n+\treturn hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);\n }\n \n /**\n@@ -86,8 +102,7 @@ static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)\n */\n static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)\n {\n-\treturn hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,\n-\t\t\t\t\t\t value);\n+\treturn hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);\n }\n \n /**\n@@ -325,6 +340,68 @@ static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,\n \treturn IXGBE_NOT_IMPLEMENTED;\n }\n \n+/**\n+ * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation\n+ * @hw: pointer to the hardware structure\n+ * @addr: I2C bus address to read from\n+ * @reg: I2C device register to read from\n+ * @val: pointer to location to receive read value\n+ *\n+ * Returns an error code on error.\n+ **/\n+static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,\n+\t\t\t\t\t u16 reg, u16 *val)\n+{\n+\treturn ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);\n+}\n+\n+/**\n+ * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation\n+ * @hw: pointer to the hardware structure\n+ * @addr: I2C bus address to read from\n+ * @reg: I2C device register to read from\n+ * @val: pointer to location to receive read value\n+ *\n+ * Returns an error code on error.\n+ **/\n+static s32\n+ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,\n+\t\t\t\t\t u16 reg, u16 *val)\n+{\n+\treturn ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);\n+}\n+\n+/**\n+ * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation\n+ * @hw: pointer to the hardware structure\n+ * @addr: I2C bus address to write to\n+ * @reg: I2C device register to write to\n+ * @val: value to write\n+ *\n+ * Returns an error code on error.\n+ **/\n+static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,\n+\t\t\t\t\t u8 addr, u16 reg, u16 val)\n+{\n+\treturn ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);\n+}\n+\n+/**\n+ * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation\n+ * @hw: pointer to the hardware structure\n+ * @addr: I2C bus address to write to\n+ * @reg: I2C device register to write to\n+ * @val: value to write\n+ *\n+ * Returns an error code on error.\n+ **/\n+static s32\n+ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,\n+\t\t\t\t\t u8 addr, u16 reg, u16 val)\n+{\n+\treturn ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);\n+}\n+\n /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params\n * @hw: pointer to hardware structure\n *\n@@ -1338,8 +1415,10 @@ ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,\n \t\treg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n \telse\n \t\treg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n-\tstatus = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,\n-\t\t\t\t\t\t reg_slice, reg_val);\n+\n+\tstatus = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,\n+\t\t\t\t\t reg_val);\n+\n \treturn status;\n }\n \n@@ -3211,11 +3290,6 @@ static const struct ixgbe_phy_operations phy_ops_X550EM_x = {\n \t.identify\t\t= &ixgbe_identify_phy_x550em,\n \t.read_reg\t\t= &ixgbe_read_phy_reg_generic,\n \t.write_reg\t\t= &ixgbe_write_phy_reg_generic,\n-\t.read_i2c_combined\t= &ixgbe_read_i2c_combined_generic,\n-\t.write_i2c_combined\t= &ixgbe_write_i2c_combined_generic,\n-\t.read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,\n-\t.write_i2c_combined_unlocked =\n-\t\t\t\t &ixgbe_write_i2c_combined_generic_unlocked,\n };\n \n static const struct ixgbe_phy_operations phy_ops_x550em_a = {\n@@ -3228,6 +3302,13 @@ static const struct ixgbe_phy_operations phy_ops_x550em_a = {\n \t.write_reg_mdi\t\t= &ixgbe_write_phy_reg_mdi,\n };\n \n+static const struct ixgbe_link_operations link_ops_x550em_x = {\n+\t.read_link\t\t= &ixgbe_read_i2c_combined_generic,\n+\t.read_link_unlocked\t= &ixgbe_read_i2c_combined_generic_unlocked,\n+\t.write_link\t\t= &ixgbe_write_i2c_combined_generic,\n+\t.write_link_unlocked\t= &ixgbe_write_i2c_combined_generic_unlocked,\n+};\n+\n static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {\n \tIXGBE_MVALS_INIT(X550)\n };\n@@ -3258,11 +3339,12 @@ const struct ixgbe_info ixgbe_X550EM_x_info = {\n \t.phy_ops\t\t= &phy_ops_X550EM_x,\n \t.mbx_ops\t\t= &mbx_ops_generic,\n \t.mvals\t\t\t= ixgbe_mvals_X550EM_x,\n+\t.link_ops\t\t= &link_ops_x550em_x,\n };\n \n const struct ixgbe_info ixgbe_x550em_a_info = {\n \t.mac\t\t\t= ixgbe_mac_x550em_a,\n-\t.get_invariants\t\t= &ixgbe_get_invariants_X550_x,\n+\t.get_invariants\t\t= &ixgbe_get_invariants_X550_a,\n \t.mac_ops\t\t= &mac_ops_x550em_a,\n \t.eeprom_ops\t\t= &eeprom_ops_X550EM_x,\n \t.phy_ops\t\t= &phy_ops_x550em_a,\n", "prefixes": [ "v3" ] }