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GET /api/patches/677369/?format=api
{ "id": 677369, "url": "http://patchwork.ozlabs.org/api/patches/677369/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20161001141931.32354-27-paul.burton@imgtec.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20161001141931.32354-27-paul.burton@imgtec.com>", "list_archive_url": null, "date": "2016-10-01T14:19:29", "name": "[U-Boot,26/27] mips: Use a physical CONFIG_SYS_SDRAM_BASE for remaining boards", "commit_ref": null, "pull_url": null, "state": "deferred", "archived": false, "hash": "6ad4a27905c35dc77fe16aca56f383a30fd98c91", "submitter": { "id": 33698, "url": "http://patchwork.ozlabs.org/api/people/33698/?format=api", "name": "Paul Burton", "email": "paul.burton@imgtec.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20161001141931.32354-27-paul.burton@imgtec.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/677369/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/677369/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 3smVx20FSHz9s2G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSun, 2 Oct 2016 00:26:30 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 92009B3826;\n\tSat, 1 Oct 2016 16:26:28 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id WslxSBI310US; Sat, 1 Oct 2016 16:26:28 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id ECF15B381E;\n\tSat, 1 Oct 2016 16:26:27 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 46426B381E\n\tfor <u-boot@lists.denx.de>; Sat, 1 Oct 2016 16:26:24 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id CIXn43CIx2zL for <u-boot@lists.denx.de>;\n\tSat, 1 Oct 2016 16:26:24 +0200 (CEST)", "from mailapp01.imgtec.com (mailapp02.imgtec.com [217.156.133.132])\n\tby theia.denx.de (Postfix) with ESMTP id 1773EB3814\n\tfor <u-boot@lists.denx.de>; Sat, 1 Oct 2016 16:26:24 +0200 (CEST)", "from HHMAIL03.hh.imgtec.org (unknown [10.44.0.21])\n\tby Forcepoint Email with ESMTPS id 1D8A8D6923DF4;\n\tSat, 1 Oct 2016 15:26:19 +0100 (IST)", "from localhost (192.168.159.74) by HHMAIL03.hh.imgtec.org\n\t(10.44.0.22) with Microsoft SMTP Server (TLS) id 14.3.294.0;\n\tSat, 1 Oct 2016 15:26:22 +0100" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Paul Burton <paul.burton@imgtec.com>", "To": "<u-boot@lists.denx.de>", "Date": "Sat, 1 Oct 2016 15:19:29 +0100", "Message-ID": "<20161001141931.32354-27-paul.burton@imgtec.com>", "X-Mailer": "git-send-email 2.10.0", "In-Reply-To": "<20161001141931.32354-1-paul.burton@imgtec.com>", "References": "<20161001141931.32354-1-paul.burton@imgtec.com>", "MIME-Version": "1.0", "X-Originating-IP": "[192.168.159.74]", "Cc": "Marek Vasut <marex@denx.de>,\n\tPurna Chandra Mandal <purna.mandal@microchip.com>,\n\tWills Wang <wills.wang@live.com>", "Subject": "[U-Boot] [PATCH 26/27] mips: Use a physical CONFIG_SYS_SDRAM_BASE\n\tfor remaining boards", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "README states that CONFIG_SYS_SDRAM_BASE should the physical base\naddress of SDRAM, whilst up until now various pieces of generic code\nhave presumed that it can be directly accessed by the CPU & MIPS has\nprovided a virtual address for CONFIG_SYS_SDRAM_BASE. Other generic code\nexpects CONFIG_SYS_SDRAM_BASE to be a physical address, which makes the\ninconsistency a mess.\n\nNow that the preceding patches have prepared us to handle using a\nphysical CONFIG_SYS_SDRAM_BASE, clean up the inconsistency for the\nremaining MIPS boards by providing a physical CONFIG_SYS_SDRAM_BASE.\n\nNone of these boards use CONFIG_SYS_SDRAM_BASE in their code, so they're\nhandled together.\n\nThis has only been build-tested, feedback welcome.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\nCc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nCc: Marek Vasut <marex@denx.de>\nCc: Purna Chandra Mandal <purna.mandal@microchip.com>\nCc: Wills Wang <wills.wang@live.com>\n---\n\n include/configs/ap121.h | 2 +-\n include/configs/ap143.h | 2 +-\n include/configs/dbau1x00.h | 2 +-\n include/configs/pb1x00.h | 2 +-\n include/configs/pic32mzdask.h | 2 +-\n include/configs/qemu-mips.h | 2 +-\n include/configs/qemu-mips64.h | 2 +-\n include/configs/tplink_wdr4300.h | 2 +-\n include/configs/vct.h | 2 +-\n 9 files changed, 9 insertions(+), 9 deletions(-)", "diff": "diff --git a/include/configs/ap121.h b/include/configs/ap121.h\nindex bf5746f..63e0015 100644\n--- a/include/configs/ap121.h\n+++ b/include/configs/ap121.h\n@@ -20,7 +20,7 @@\n #define CONFIG_SYS_MALLOC_LEN 0x40000\n #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000\n \n-#define CONFIG_SYS_SDRAM_BASE 0x80000000\n+#define CONFIG_SYS_SDRAM_BASE 0x0\n #define CONFIG_SYS_LOAD_ADDR 0x81000000\n \n #define CONFIG_SYS_NO_FLASH\ndiff --git a/include/configs/ap143.h b/include/configs/ap143.h\nindex 5d7e49e..a8721e6 100644\n--- a/include/configs/ap143.h\n+++ b/include/configs/ap143.h\n@@ -20,7 +20,7 @@\n #define CONFIG_SYS_MALLOC_LEN 0x40000\n #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000\n \n-#define CONFIG_SYS_SDRAM_BASE 0x80000000\n+#define CONFIG_SYS_SDRAM_BASE 0x0\n #define CONFIG_SYS_LOAD_ADDR 0x81000000\n \n #define CONFIG_SYS_NO_FLASH\ndiff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h\nindex dbd2bb3..b369d71 100644\n--- a/include/configs/dbau1x00.h\n+++ b/include/configs/dbau1x00.h\n@@ -105,7 +105,7 @@\n \n #define CONFIG_SYS_MIPS_TIMER_FREQ\t(CONFIG_SYS_MHZ * 1000000)\n \n-#define CONFIG_SYS_SDRAM_BASE\t\t0x80000000 /* Cached addr */\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x0 /* Cached addr */\n \n #define\tCONFIG_SYS_LOAD_ADDR\t\t0x81000000 /* default load address\t*/\n \ndiff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h\nindex fb5278f..8ef334f 100644\n--- a/include/configs/pb1x00.h\n+++ b/include/configs/pb1x00.h\n@@ -61,7 +61,7 @@\n \n #define CONFIG_SYS_MIPS_TIMER_FREQ\t396000000\n \n-#define CONFIG_SYS_SDRAM_BASE\t\t0x80000000 /* Cached addr */\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x0 /* Cached addr */\n \n #define\tCONFIG_SYS_LOAD_ADDR\t\t0x81000000 /* default load address\t*/\n \ndiff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h\nindex 49c98d8..5b80b46 100644\n--- a/include/configs/pic32mzdask.h\n+++ b/include/configs/pic32mzdask.h\n@@ -35,7 +35,7 @@\n \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)\n \n /* SDRAM Configuration (for final code, data, stack, heap) */\n-#define CONFIG_SYS_SDRAM_BASE\t\t0x88000000\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x08000000\n #define CONFIG_SYS_MALLOC_LEN\t\t(256 << 10)\n #define CONFIG_SYS_BOOTPARAMS_LEN\t(4 << 10)\n #define CONFIG_STACKSIZE\t\t(4 << 10) /* regular stack */\ndiff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h\nindex 546c508..7e839a8 100644\n--- a/include/configs/qemu-mips.h\n+++ b/include/configs/qemu-mips.h\n@@ -94,7 +94,7 @@\n #define CONFIG_SYS_MIPS_TIMER_FREQ\t(CONFIG_SYS_MHZ * 1000000)\n \n /* Cached addr */\n-#define CONFIG_SYS_SDRAM_BASE\t\t0x80000000\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x0\n \n /* default load address */\n #define CONFIG_SYS_LOAD_ADDR\t\t0x81000000\ndiff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h\nindex 6cab719..18e3294 100644\n--- a/include/configs/qemu-mips64.h\n+++ b/include/configs/qemu-mips64.h\n@@ -94,7 +94,7 @@\n #define CONFIG_SYS_MIPS_TIMER_FREQ\t(CONFIG_SYS_MHZ * 1000000)\n \n /* Cached addr */\n-#define CONFIG_SYS_SDRAM_BASE\t\t0xffffffff80000000\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x0\n \n /* default load address */\n #define CONFIG_SYS_LOAD_ADDR\t\t0xffffffff81000000\ndiff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h\nindex 7bf8e4c..5a6a0d4 100644\n--- a/include/configs/tplink_wdr4300.h\n+++ b/include/configs/tplink_wdr4300.h\n@@ -20,7 +20,7 @@\n #define CONFIG_SYS_MALLOC_LEN\t\t0x40000\n #define CONFIG_SYS_BOOTPARAMS_LEN\t0x20000\n \n-#define CONFIG_SYS_SDRAM_BASE\t\t0xa0000000\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x0\n #define CONFIG_SYS_LOAD_ADDR\t\t0xa1000000\n #define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n \ndiff --git a/include/configs/vct.h b/include/configs/vct.h\nindex f2e0e5c..3e50619 100644\n--- a/include/configs/vct.h\n+++ b/include/configs/vct.h\n@@ -63,7 +63,7 @@\n /*\n * SDRAM\n */\n-#define CONFIG_SYS_SDRAM_BASE\t\t0x80000000\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x0\n #define CONFIG_SYS_MBYTES_SDRAM\t\t128\n #define CONFIG_SYS_MEMTEST_START\t0x80200000\n #define CONFIG_SYS_MEMTEST_END\t\t0x80400000\n", "prefixes": [ "U-Boot", "26/27" ] }