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GET /api/patches/675780/?format=api
{ "id": 675780, "url": "http://patchwork.ozlabs.org/api/patches/675780/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1475000934-27335-4-git-send-email-bimmy.pujari@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1475000934-27335-4-git-send-email-bimmy.pujari@intel.com>", "list_archive_url": null, "date": "2016-09-27T18:28:50", "name": "[next,S48,3/7] i40e: Drop redundant Rx descriptor processing code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "813929ec1b2e5a96952b7559c6f8bca20482b36d", "submitter": { "id": 68919, "url": "http://patchwork.ozlabs.org/api/people/68919/?format=api", "name": "Pujari, Bimmy", "email": "bimmy.pujari@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1475000934-27335-4-git-send-email-bimmy.pujari@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/675780/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/675780/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3sk8XM4KHPz9sBr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 28 Sep 2016 04:30:27 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id B0BD88BF1E;\n\tTue, 27 Sep 2016 18:30:25 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 82CFouKtPGA7; Tue, 27 Sep 2016 18:30:20 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 28FF68BED5;\n\tTue, 27 Sep 2016 18:30:20 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id C5E701C1005\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 27 Sep 2016 18:30:16 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id C39F62F75B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 27 Sep 2016 18:30:16 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 7z2uHnkr2Eoo for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 27 Sep 2016 18:30:15 +0000 (UTC)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby silver.osuosl.org (Postfix) with ESMTPS id E82BD2FE88\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 27 Sep 2016 18:30:14 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga104.fm.intel.com with ESMTP; 27 Sep 2016 11:30:15 -0700", "from bimmy.jf.intel.com (HELO bimmy.linux1.jf.intel.com)\n\t([134.134.2.167])\n\tby orsmga004.jf.intel.com with ESMTP; 27 Sep 2016 11:30:13 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.30,406,1470726000\"; d=\"scan'208\";a=\"14319715\"", "From": "Bimmy Pujari <bimmy.pujari@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Tue, 27 Sep 2016 11:28:50 -0700", "Message-Id": "<1475000934-27335-4-git-send-email-bimmy.pujari@intel.com>", "X-Mailer": "git-send-email 2.4.11", "In-Reply-To": "<1475000934-27335-1-git-send-email-bimmy.pujari@intel.com>", "References": "<1475000934-27335-1-git-send-email-bimmy.pujari@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S48 3/7] i40e: Drop redundant Rx\n\tdescriptor processing code", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Alexander Duyck <alexander.h.duyck@intel.com>\n\nThis patch cleans up several pieces of redundant code in the Rx clean-up\npaths.\n\nThe first bit is that hdr_addr and the status_err_len portions of the Rx\ndescriptor represent the same value. As such there is no point in setting\nthem to 0 before setting them to 0. I'm dropping the second spot where we\nare updating the value to 0 so that we only have 1 write for this value\ninstead of 2.\n\nThe second piece is the checking for the DD bit in the packet. We only\nneed to check for a non-zero value for the status_err_len because if the\ndevice is done with the descriptor it will have written something back and\nthe DD is just one piece of it. In addition I have moved the reading of\nthe Rx descriptor bits related to rx_ptype down so that they are actually\nbelow the dma_rmb() call so that we are guaranteed that we don't have any\nfunky 64b on 32b calls causing any ordering issues.\n\nSigned-off-by: Alexander Duyck <alexander.h.duyck@intel.com>\nChange-ID: I256e44a025d3c64a7224aaaec37c852bfcb1871b\n---\nTesting Hints:\n We should still receive packets normally. This change could impact\n the Rx hashing, but I don't know of any tests for skb->hash. The\n only possibility I can think of would be to add a trace point.\n\n drivers/net/ethernet/intel/i40e/i40e_txrx.c | 18 ++++++------------\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 18 ++++++------------\n 2 files changed, 12 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\nindex 7d5a462..54764dd 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n@@ -1217,7 +1217,6 @@ bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)\n \t\t * because each write-back erases this info.\n \t\t */\n \t\trx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);\n-\t\trx_desc->read.hdr_addr = 0;\n \n \t\trx_desc++;\n \t\tbi++;\n@@ -1738,7 +1737,6 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \twhile (likely(total_rx_packets < budget)) {\n \t\tunion i40e_rx_desc *rx_desc;\n \t\tstruct sk_buff *skb;\n-\t\tu32 rx_status;\n \t\tu16 vlan_tag;\n \t\tu8 rx_ptype;\n \t\tu64 qword;\n@@ -1752,21 +1750,13 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \n \t\trx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);\n \n-\t\tqword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);\n-\t\trx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>\n-\t\t\t I40E_RXD_QW1_PTYPE_SHIFT;\n-\t\trx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>\n-\t\t\t I40E_RXD_QW1_STATUS_SHIFT;\n-\n-\t\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))\n-\t\t\tbreak;\n-\n \t\t/* status_error_len will always be zero for unused descriptors\n \t\t * because it's cleared in cleanup, and overlaps with hdr_addr\n \t\t * which is always zero because packet split isn't used, if the\n \t\t * hardware wrote DD then it will be non-zero\n \t\t */\n-\t\tif (!rx_desc->wb.qword1.status_error_len)\n+\t\tif (!i40e_test_staterr(rx_desc,\n+\t\t\t\t BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))\n \t\t\tbreak;\n \n \t\t/* This memory barrier is needed to keep us from reading\n@@ -1800,6 +1790,10 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \t\t/* probably a little skewed due to removing CRC */\n \t\ttotal_rx_bytes += skb->len;\n \n+\t\tqword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);\n+\t\trx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>\n+\t\t\t I40E_RXD_QW1_PTYPE_SHIFT;\n+\n \t\t/* populate checksum, VLAN, and protocol */\n \t\ti40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);\n \ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex dd8ad6b..e2d3622 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -705,7 +705,6 @@ bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)\n \t\t * because each write-back erases this info.\n \t\t */\n \t\trx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);\n-\t\trx_desc->read.hdr_addr = 0;\n \n \t\trx_desc++;\n \t\tbi++;\n@@ -1209,7 +1208,6 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \twhile (likely(total_rx_packets < budget)) {\n \t\tunion i40e_rx_desc *rx_desc;\n \t\tstruct sk_buff *skb;\n-\t\tu32 rx_status;\n \t\tu16 vlan_tag;\n \t\tu8 rx_ptype;\n \t\tu64 qword;\n@@ -1223,21 +1221,13 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \n \t\trx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);\n \n-\t\tqword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);\n-\t\trx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>\n-\t\t\t I40E_RXD_QW1_PTYPE_SHIFT;\n-\t\trx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>\n-\t\t\t I40E_RXD_QW1_STATUS_SHIFT;\n-\n-\t\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))\n-\t\t\tbreak;\n-\n \t\t/* status_error_len will always be zero for unused descriptors\n \t\t * because it's cleared in cleanup, and overlaps with hdr_addr\n \t\t * which is always zero because packet split isn't used, if the\n \t\t * hardware wrote DD then it will be non-zero\n \t\t */\n-\t\tif (!rx_desc->wb.qword1.status_error_len)\n+\t\tif (!i40e_test_staterr(rx_desc,\n+\t\t\t\t BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))\n \t\t\tbreak;\n \n \t\t/* This memory barrier is needed to keep us from reading\n@@ -1271,6 +1261,10 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \t\t/* probably a little skewed due to removing CRC */\n \t\ttotal_rx_bytes += skb->len;\n \n+\t\tqword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);\n+\t\trx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>\n+\t\t\t I40E_RXD_QW1_PTYPE_SHIFT;\n+\n \t\t/* populate checksum, VLAN, and protocol */\n \t\ti40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);\n \n", "prefixes": [ "next", "S48", "3/7" ] }