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GET /api/patches/675291/?format=api
{ "id": 675291, "url": "http://patchwork.ozlabs.org/api/patches/675291/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20160926182917.27531-16-paul.burton@imgtec.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20160926182917.27531-16-paul.burton@imgtec.com>", "list_archive_url": null, "date": "2016-09-26T18:29:09", "name": "[U-Boot,15/23] gpio: eg20t: Add driver for Intel EG20T GPIO controllers", "commit_ref": null, "pull_url": null, "state": "deferred", "archived": false, "hash": "bd690d8c420c0b43b1e9f4890004956d2d7626f0", "submitter": { "id": 33698, "url": "http://patchwork.ozlabs.org/api/people/33698/?format=api", "name": "Paul Burton", "email": "paul.burton@imgtec.com" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20160926182917.27531-16-paul.burton@imgtec.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/675291/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/675291/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 3sjXfP2zdXz9sXR\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 27 Sep 2016 04:33:33 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 9C3F3A7663;\n\tMon, 26 Sep 2016 20:33:20 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id qLxucibozr2D; Mon, 26 Sep 2016 20:33:20 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id EE01AA75E6;\n\tMon, 26 Sep 2016 20:33:19 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 6460AA7663\n\tfor <u-boot@lists.denx.de>; Mon, 26 Sep 2016 20:33:17 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id yB3K9uBu2oMj for <u-boot@lists.denx.de>;\n\tMon, 26 Sep 2016 20:33:17 +0200 (CEST)", "from mailapp01.imgtec.com (mailapp02.imgtec.com [217.156.133.132])\n\tby theia.denx.de (Postfix) with ESMTP id 24DC7A75E6\n\tfor <u-boot@lists.denx.de>; Mon, 26 Sep 2016 20:33:15 +0200 (CEST)", "from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19])\n\tby Forcepoint Email with ESMTPS id 8591A73D5D637;\n\tMon, 26 Sep 2016 19:33:10 +0100 (IST)", "from localhost (10.100.200.111) by HHMAIL01.hh.imgtec.org\n\t(10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0;\n\tMon, 26 Sep 2016 19:33:13 +0100" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Paul Burton <paul.burton@imgtec.com>", "To": "<u-boot@lists.denx.de>, Daniel Schwierzeck <daniel.schwierzeck@gmail.com>", "Date": "Mon, 26 Sep 2016 19:29:09 +0100", "Message-ID": "<20160926182917.27531-16-paul.burton@imgtec.com>", "X-Mailer": "git-send-email 2.10.0", "In-Reply-To": "<20160926182917.27531-1-paul.burton@imgtec.com>", "References": "<20160926182917.27531-1-paul.burton@imgtec.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.100.200.111]", "Subject": "[U-Boot] [PATCH 15/23] gpio: eg20t: Add driver for Intel EG20T GPIO\n\tcontrollers", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add a driver for the GPIO controller found in the Intel EG20T Platform\nController Hub. This is used on the MIPS Boston development board to\nprovide GPIOs including ethernet PHY reset.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\n\n---\n\n drivers/gpio/Kconfig | 8 +++\n drivers/gpio/Makefile | 1 +\n drivers/gpio/eg20t-gpio.c | 133 ++++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 142 insertions(+)\n create mode 100644 drivers/gpio/eg20t-gpio.c", "diff": "diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig\nindex 8d9ab52..4a6a22f 100644\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -221,4 +221,12 @@ config MPC85XX_GPIO\n \n \t The driver has been tested on MPC85XX, but it is likely that other\n \t PowerQUICC III devices will work as well.\n+\n+config EG20T_GPIO\n+\tbool \"Intel EG20T GPIO driver\"\n+\tdepends on DM_GPIO && DM_PCI\n+\thelp\n+\t Enable this to support the GPIO controller found in the Intel EG20T\n+\t Platform Controller Hub.\n+\n endmenu\ndiff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile\nindex 8939226..a94aeb1 100644\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -58,3 +58,4 @@ obj-$(CONFIG_MVEBU_GPIO)\t+= mvebu_gpio.o\n obj-$(CONFIG_MSM_GPIO)\t\t+= msm_gpio.o\n obj-$(CONFIG_$(SPL_)PCF8575_GPIO)\t+= pcf8575_gpio.o\n obj-$(CONFIG_PM8916_GPIO)\t+= pm8916_gpio.o\n+obj-$(CONFIG_EG20T_GPIO)\t+= eg20t-gpio.o\ndiff --git a/drivers/gpio/eg20t-gpio.c b/drivers/gpio/eg20t-gpio.c\nnew file mode 100644\nindex 0000000..05db771\n--- /dev/null\n+++ b/drivers/gpio/eg20t-gpio.c\n@@ -0,0 +1,133 @@\n+/*\n+ * Copyright (C) 2016 Imagination Technologies\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <pci.h>\n+#include <asm/io.h>\n+#include <asm/gpio.h>\n+\n+enum {\n+\tREG_IEN\t\t= 0x00,\n+\tREG_ISTATUS\t= 0x04,\n+\tREG_IDISP\t= 0x08,\n+\tREG_ICLR\t= 0x0c,\n+\tREG_IMASK\t= 0x10,\n+\tREG_IMASKCLR\t= 0x14,\n+\tREG_PO\t\t= 0x18,\n+\tREG_PI\t\t= 0x1c,\n+\tREG_PM\t\t= 0x20,\n+};\n+\n+struct eg20t_gpio_priv {\n+\tvoid *base;\n+};\n+\n+static int eg20t_gpio_get_value(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tuint32_t pm, pval;\n+\n+\tpm = readl(priv->base + REG_PM);\n+\tif ((pm >> offset) & 0x1)\n+\t\tpval = readl(priv->base + REG_PO);\n+\telse\n+\t\tpval = readl(priv->base + REG_PI);\n+\n+\treturn (pval >> offset) & 0x1;\n+}\n+\n+static int eg20t_gpio_set_value(struct udevice *dev, unsigned int offset,\n+\t\t\t\tint value)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tuint32_t po;\n+\n+\tpo = readl(priv->base + REG_PO);\n+\tif (value)\n+\t\tpo |= 1 << offset;\n+\telse\n+\t\tpo &= ~(1 << offset);\n+\twritel(po, priv->base + REG_PO);\n+\treturn 0;\n+}\n+\n+static int eg20t_gpio_direction_input(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tuint32_t pm;\n+\n+\tpm = readl(priv->base + REG_PM);\n+\tpm &= ~(1 << offset);\n+\twritel(pm, priv->base + REG_PM);\n+\treturn 0;\n+}\n+\n+static int eg20t_gpio_direction_output(struct udevice *dev, unsigned int offset,\n+\t\t\t\t int value)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tuint32_t pm;\n+\n+\tpm = readl(priv->base + REG_PM);\n+\tpm |= 1 << offset;\n+\twritel(pm, priv->base + REG_PM);\n+\n+\treturn eg20t_gpio_set_value(dev, offset, value);\n+}\n+\n+static int eg20t_gpio_get_function(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tuint32_t pm;\n+\n+\tpm = readl(priv->base + REG_PM);\n+\n+\tif ((pm >> offset) & 0x1)\n+\t\treturn GPIOF_OUTPUT;\n+\n+\treturn GPIOF_INPUT;\n+}\n+\n+static const struct dm_gpio_ops eg20t_gpio_ops = {\n+\t.direction_input\t= eg20t_gpio_direction_input,\n+\t.direction_output\t= eg20t_gpio_direction_output,\n+\t.get_value\t\t= eg20t_gpio_get_value,\n+\t.set_value\t\t= eg20t_gpio_set_value,\n+\t.get_function\t\t= eg20t_gpio_get_function,\n+};\n+\n+static int eg20t_gpio_probe(struct udevice *dev)\n+{\n+\tstruct eg20t_gpio_priv *priv = dev_get_priv(dev);\n+\tstruct gpio_dev_priv *uc_priv = dev->uclass_priv;\n+\n+\tpriv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);\n+\tif (!priv->base) {\n+\t\tdebug(\"failed to map GPIO registers\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tuc_priv->gpio_count = 12;\n+\tuc_priv->bank_name = \"eg20t\";\n+\treturn 0;\n+}\n+\n+U_BOOT_DRIVER(eg20t_gpio) = {\n+\t.name\t= \"eg20t-gpio\",\n+\t.id\t= UCLASS_GPIO,\n+\t.probe\t= eg20t_gpio_probe,\n+\t.priv_auto_alloc_size = sizeof(struct eg20t_gpio_priv),\n+\t.ops\t= &eg20t_gpio_ops,\n+};\n+\n+static struct pci_device_id eg20t_gpio_supported[] = {\n+\t{ PCI_VENDOR_ID_INTEL, 0x8803 },\n+\t{ },\n+};\n+\n+U_BOOT_PCI_DEVICE(eg20t_gpio, eg20t_gpio_supported);\n", "prefixes": [ "U-Boot", "15/23" ] }