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GET /api/patches/675285/?format=api
{ "id": 675285, "url": "http://patchwork.ozlabs.org/api/patches/675285/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20160926182917.27531-10-paul.burton@imgtec.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20160926182917.27531-10-paul.burton@imgtec.com>", "list_archive_url": null, "date": "2016-09-26T18:29:03", "name": "[U-Boot,09/23] boston: Disable PCI bridge memory space alignment", "commit_ref": null, "pull_url": null, "state": "deferred", "archived": false, "hash": "be25fbf996d7c329530f88f510fd38fa0f563fe4", "submitter": { "id": 33698, "url": "http://patchwork.ozlabs.org/api/people/33698/?format=api", "name": "Paul Burton", "email": "paul.burton@imgtec.com" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20160926182917.27531-10-paul.burton@imgtec.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/675285/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/675285/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 3sjXcr3Kppz9sXR\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 27 Sep 2016 04:32:12 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 8DA79A7613;\n\tMon, 26 Sep 2016 20:31:50 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id EAvnN0JSQIkT; Mon, 26 Sep 2016 20:31:50 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 09D43A756F;\n\tMon, 26 Sep 2016 20:31:50 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 5E4C9A756F\n\tfor <u-boot@lists.denx.de>; Mon, 26 Sep 2016 20:31:47 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id leW39zjBMH8G for <u-boot@lists.denx.de>;\n\tMon, 26 Sep 2016 20:31:47 +0200 (CEST)", "from mailapp01.imgtec.com (mailapp02.imgtec.com [217.156.133.132])\n\tby theia.denx.de (Postfix) with ESMTP id 2BDCAA7558\n\tfor <u-boot@lists.denx.de>; Mon, 26 Sep 2016 20:31:47 +0200 (CEST)", "from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19])\n\tby Forcepoint Email with ESMTPS id 848126CD2830B;\n\tMon, 26 Sep 2016 19:31:42 +0100 (IST)", "from localhost (10.100.200.111) by HHMAIL01.hh.imgtec.org\n\t(10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0;\n\tMon, 26 Sep 2016 19:31:45 +0100" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Paul Burton <paul.burton@imgtec.com>", "To": "<u-boot@lists.denx.de>, Daniel Schwierzeck <daniel.schwierzeck@gmail.com>", "Date": "Mon, 26 Sep 2016 19:29:03 +0100", "Message-ID": "<20160926182917.27531-10-paul.burton@imgtec.com>", "X-Mailer": "git-send-email 2.10.0", "In-Reply-To": "<20160926182917.27531-1-paul.burton@imgtec.com>", "References": "<20160926182917.27531-1-paul.burton@imgtec.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.100.200.111]", "Subject": "[U-Boot] [PATCH 09/23] boston: Disable PCI bridge memory space\n\talignment", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "On the MIPS Boston development board we have an Intel EG20T Platform\nController Hub connected to a Xilinx AXI to PCIe root port which is only\nassigned a 1MB memory region. The Intel EG20T contains a bridge device\nbeneath which all of its peripheral devices can be found, and that\nbridge device contains a ROM. If we align to 1MB when we encounter each\nbridge device we therefore do something like this:\n\n - Start with bus_lower at 0x16000000.\n\n - Find the Xilinx root bridge, which has no visible BARs so we do very\n little to it.\n\n - Probe the bus beneath the Xilinx bridge device, aligning bus_lower\n to a 1MB boundary first. That leaves it still at 0x16000000.\n\n - Find the EG20T bridge device, which we find has a 64KiB ROM. We\n assign it the address range 0x16000000-0x1600ffff which leaves\n bus_lower at 0x16010000.\n\n - Probe the bus beneath the EG20T bridge device, aligning bus_lower to\n a 1MB boundary first. This leaves bus_lower at 0x16100000, which is\n the end of the available memory space.\n\n - Find the various peripheral devices the EG20T contains, but fail to\n assign any memory space to them since bus_lower is at the end of the\n memory space available to the PCI bus.\n\nFix this by disabling that 1MB alignment, which allows all of the EG20T\nperipheral devices to be assigned memory space within the 1MB region\navailable.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\n\n---\n\n configs/boston32r2_defconfig | 1 +\n configs/boston32r2el_defconfig | 1 +\n configs/boston64r2_defconfig | 1 +\n configs/boston64r2el_defconfig | 1 +\n 4 files changed, 4 insertions(+)", "diff": "diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig\nindex ca66248..e5f61b8 100644\n--- a/configs/boston32r2_defconfig\n+++ b/configs/boston32r2_defconfig\n@@ -36,6 +36,7 @@ CONFIG_CFI_FLASH=y\n CONFIG_DM_ETH=y\n CONFIG_PCH_GBE=y\n CONFIG_DM_PCI=y\n+CONFIG_DM_PCI_BRIDGE_MEM_ALIGN=0x0\n CONFIG_PCI_XILINX=y\n CONFIG_SYS_NS16550=y\n CONFIG_LZ4=y\ndiff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig\nindex 67f54bf..e9a23b8 100644\n--- a/configs/boston32r2el_defconfig\n+++ b/configs/boston32r2el_defconfig\n@@ -37,6 +37,7 @@ CONFIG_CFI_FLASH=y\n CONFIG_DM_ETH=y\n CONFIG_PCH_GBE=y\n CONFIG_DM_PCI=y\n+CONFIG_DM_PCI_BRIDGE_MEM_ALIGN=0x0\n CONFIG_PCI_XILINX=y\n CONFIG_SYS_NS16550=y\n CONFIG_LZ4=y\ndiff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig\nindex 1245d1b..55943c5 100644\n--- a/configs/boston64r2_defconfig\n+++ b/configs/boston64r2_defconfig\n@@ -36,6 +36,7 @@ CONFIG_CFI_FLASH=y\n CONFIG_DM_ETH=y\n CONFIG_PCH_GBE=y\n CONFIG_DM_PCI=y\n+CONFIG_DM_PCI_BRIDGE_MEM_ALIGN=0x0\n CONFIG_PCI_XILINX=y\n CONFIG_SYS_NS16550=y\n CONFIG_LZ4=y\ndiff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig\nindex 9b5fa5a..865177d 100644\n--- a/configs/boston64r2el_defconfig\n+++ b/configs/boston64r2el_defconfig\n@@ -37,6 +37,7 @@ CONFIG_CFI_FLASH=y\n CONFIG_DM_ETH=y\n CONFIG_PCH_GBE=y\n CONFIG_DM_PCI=y\n+CONFIG_DM_PCI_BRIDGE_MEM_ALIGN=0x0\n CONFIG_PCI_XILINX=y\n CONFIG_SYS_NS16550=y\n CONFIG_LZ4=y\n", "prefixes": [ "U-Boot", "09/23" ] }