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GET /api/patches/675284/?format=api
{ "id": 675284, "url": "http://patchwork.ozlabs.org/api/patches/675284/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20160926182917.27531-9-paul.burton@imgtec.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20160926182917.27531-9-paul.burton@imgtec.com>", "list_archive_url": null, "date": "2016-09-26T18:29:02", "name": "[U-Boot,08/23] pci: Make PCI bridge memory alignment configurable", "commit_ref": null, "pull_url": null, "state": "deferred", "archived": false, "hash": "bff63bd897eba4c88615d76da893566e2faf1af4", "submitter": { "id": 33698, "url": "http://patchwork.ozlabs.org/api/people/33698/?format=api", "name": "Paul Burton", "email": "paul.burton@imgtec.com" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20160926182917.27531-9-paul.burton@imgtec.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/675284/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/675284/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 3sjXcW57Swz9s3T\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 27 Sep 2016 04:31:55 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 93589A7629;\n\tMon, 26 Sep 2016 20:31:35 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 9Zq8iNwRWZIx; Mon, 26 Sep 2016 20:31:35 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id A788EA75E6;\n\tMon, 26 Sep 2016 20:31:34 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 057FDA75E9\n\tfor <u-boot@lists.denx.de>; Mon, 26 Sep 2016 20:31:33 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id gMnEK6l-5xII for <u-boot@lists.denx.de>;\n\tMon, 26 Sep 2016 20:31:32 +0200 (CEST)", "from mailapp01.imgtec.com (mailapp02.imgtec.com [217.156.133.132])\n\tby theia.denx.de (Postfix) with ESMTP id C74DEA7580\n\tfor <u-boot@lists.denx.de>; Mon, 26 Sep 2016 20:31:32 +0200 (CEST)", "from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19])\n\tby Forcepoint Email with ESMTPS id 7B0566DB89586;\n\tMon, 26 Sep 2016 19:31:27 +0100 (IST)", "from localhost (10.100.200.111) by HHMAIL01.hh.imgtec.org\n\t(10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0;\n\tMon, 26 Sep 2016 19:31:30 +0100" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Paul Burton <paul.burton@imgtec.com>", "To": "<u-boot@lists.denx.de>, Daniel Schwierzeck <daniel.schwierzeck@gmail.com>", "Date": "Mon, 26 Sep 2016 19:29:02 +0100", "Message-ID": "<20160926182917.27531-9-paul.burton@imgtec.com>", "X-Mailer": "git-send-email 2.10.0", "In-Reply-To": "<20160926182917.27531-1-paul.burton@imgtec.com>", "References": "<20160926182917.27531-1-paul.burton@imgtec.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.100.200.111]", "Subject": "[U-Boot] [PATCH 08/23] pci: Make PCI bridge memory alignment\n\tconfigurable", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "On some systems aligning PCI memory to a 1MB boundary every time a\nbridge is encountered may lead to exhausting the available memory space\nbefore all devices have been assigned addresses.\n\nFor example on the MIPS Boston development board we have an Intel EG20T\nPlatform Controller Hub connected to a Xilinx AXI to PCIe root port\nwhich is only assigned a 1MB memory region. The Intel EG20T contains a\nbridge device beneath which all of its peripheral devices can be found,\nand that bridge device contains a ROM. If we align to 1MB when we\nencounter each bridge device we therefore do something like this:\n\n - Start with bus_lower at 0x16000000.\n\n - Find the Xilinx root bridge, which has no visible BARs so we do very\n little to it.\n\n - Probe the bus beneath the Xilinx bridge device, aligning bus_lower\n to a 1MB boundary first. That leaves it still at 0x16000000.\n\n - Find the EG20T bridge device, which we find has a 64KiB ROM. We\n assign it the address range 0x16000000-0x1600ffff which leaves\n bus_lower at 0x16010000.\n\n - Probe the bus beneath the EG20T bridge device, aligning bus_lower to\n a 1MB boundary first. This leaves bus_lower at 0x16100000, which is\n the end of the available memory space.\n\n - Find the various peripheral devices the EG20T contains, but fail to\n assign any memory space to them since bus_lower is at the end of the\n memory space available to the PCI bus.\n\nThis patch allows that 1MB alignment to be changed or disabled via\nKconfig, so that systems such as this can select an alignment which\nworks for them.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\n\n---\n\n drivers/pci/Kconfig | 7 +++++++\n drivers/pci/pci_auto.c | 24 ++++++++++++++++--------\n 2 files changed, 23 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\nindex 9a7c187..35bf8fe 100644\n--- a/drivers/pci/Kconfig\n+++ b/drivers/pci/Kconfig\n@@ -18,6 +18,13 @@ config DM_PCI_COMPAT\n \t measure when porting a board to use driver model for PCI. Once the\n \t board is fully supported, this option should be disabled.\n \n+config DM_PCI_BRIDGE_MEM_ALIGN\n+\thex \"PCI bridge memory alignment\"\n+\tdefault 0x100000\n+\thelp\n+\t PCI memory space will be aligned to be a multiple of this value\n+\t whenever a PCI-to-PCI bridge is encountered.\n+\n config PCI_SANDBOX\n \tbool \"Sandbox PCI support\"\n \tdepends on SANDBOX && DM_PCI\ndiff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c\nindex ee9a854..0326316 100644\n--- a/drivers/pci/pci_auto.c\n+++ b/drivers/pci/pci_auto.c\n@@ -186,8 +186,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)\n \tdm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);\n \n \tif (pci_mem) {\n-\t\t/* Round memory allocator to 1MB boundary */\n-\t\tpciauto_region_align(pci_mem, 0x100000);\n+\t\t/* Round memory allocator to a suitable boundary */\n+\t\tif (CONFIG_DM_PCI_BRIDGE_MEM_ALIGN)\n+\t\t\tpciauto_region_align(pci_mem,\n+\t\t\t\t\t CONFIG_DM_PCI_BRIDGE_MEM_ALIGN);\n \n \t\t/*\n \t\t * Set up memory and I/O filter limits, assume 32-bit\n@@ -200,8 +202,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)\n \t}\n \n \tif (pci_prefetch) {\n-\t\t/* Round memory allocator to 1MB boundary */\n-\t\tpciauto_region_align(pci_prefetch, 0x100000);\n+\t\t/* Round memory allocator to a suitable boundary */\n+\t\tif (CONFIG_DM_PCI_BRIDGE_MEM_ALIGN)\n+\t\t\tpciauto_region_align(pci_prefetch,\n+\t\t\t\t\t CONFIG_DM_PCI_BRIDGE_MEM_ALIGN);\n \n \t\t/*\n \t\t * Set up memory and I/O filter limits, assume 32-bit\n@@ -260,8 +264,10 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)\n \tdm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus);\n \n \tif (pci_mem) {\n-\t\t/* Round memory allocator to 1MB boundary */\n-\t\tpciauto_region_align(pci_mem, 0x100000);\n+\t\t/* Round memory allocator to a suitable boundary */\n+\t\tif (CONFIG_DM_PCI_BRIDGE_MEM_ALIGN)\n+\t\t\tpciauto_region_align(pci_mem,\n+\t\t\t\t\t CONFIG_DM_PCI_BRIDGE_MEM_ALIGN);\n \n \t\tdm_pci_write_config16(dev, PCI_MEMORY_LIMIT,\n \t\t\t\t (pci_mem->bus_lower - 1) >> 16);\n@@ -274,8 +280,10 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)\n \t\t\t\t &prefechable_64);\n \t\tprefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;\n \n-\t\t/* Round memory allocator to 1MB boundary */\n-\t\tpciauto_region_align(pci_prefetch, 0x100000);\n+\t\t/* Round memory allocator to a suitable boundary */\n+\t\tif (CONFIG_DM_PCI_BRIDGE_MEM_ALIGN)\n+\t\t\tpciauto_region_align(pci_prefetch,\n+\t\t\t\t\t CONFIG_DM_PCI_BRIDGE_MEM_ALIGN);\n \n \t\tdm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,\n \t\t\t\t (pci_prefetch->bus_lower - 1) >> 16);\n", "prefixes": [ "U-Boot", "08/23" ] }