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GET /api/patches/675281/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 675281,
    "url": "http://patchwork.ozlabs.org/api/patches/675281/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20160926182917.27531-6-paul.burton@imgtec.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20160926182917.27531-6-paul.burton@imgtec.com>",
    "list_archive_url": null,
    "date": "2016-09-26T18:28:59",
    "name": "[U-Boot,05/23] pci: xilinx: Avoid writing memory base or limit registers",
    "commit_ref": null,
    "pull_url": null,
    "state": "deferred",
    "archived": false,
    "hash": "123735270300bea08dce46d7a4607a3459a66652",
    "submitter": {
        "id": 33698,
        "url": "http://patchwork.ozlabs.org/api/people/33698/?format=api",
        "name": "Paul Burton",
        "email": "paul.burton@imgtec.com"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20160926182917.27531-6-paul.burton@imgtec.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/675281/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/675281/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Received": [
            "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 3sjXbj0NDfz9s3T\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 27 Sep 2016 04:31:13 +1000 (AEST)",
            "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id D6581A75E4;\n\tMon, 26 Sep 2016 20:30:54 +0200 (CEST)",
            "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 5AilNFg-4Hrp; Mon, 26 Sep 2016 20:30:54 +0200 (CEST)",
            "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 50CF7A756F;\n\tMon, 26 Sep 2016 20:30:54 +0200 (CEST)",
            "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 0F1AFA7577\n\tfor <u-boot@lists.denx.de>; Mon, 26 Sep 2016 20:30:52 +0200 (CEST)",
            "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Ne9oAw7PB6r0 for <u-boot@lists.denx.de>;\n\tMon, 26 Sep 2016 20:30:51 +0200 (CEST)",
            "from mailapp01.imgtec.com (mailapp02.imgtec.com [217.156.133.132])\n\tby theia.denx.de (Postfix) with ESMTP id 646DCA75FD\n\tfor <u-boot@lists.denx.de>; Mon, 26 Sep 2016 20:30:48 +0200 (CEST)",
            "from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19])\n\tby Forcepoint Email with ESMTPS id 1FFD55D56B556;\n\tMon, 26 Sep 2016 19:30:44 +0100 (IST)",
            "from localhost (10.100.200.111) by HHMAIL01.hh.imgtec.org\n\t(10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0;\n\tMon, 26 Sep 2016 19:30:47 +0100"
        ],
        "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)",
        "From": "Paul Burton <paul.burton@imgtec.com>",
        "To": "<u-boot@lists.denx.de>, Daniel Schwierzeck <daniel.schwierzeck@gmail.com>",
        "Date": "Mon, 26 Sep 2016 19:28:59 +0100",
        "Message-ID": "<20160926182917.27531-6-paul.burton@imgtec.com>",
        "X-Mailer": "git-send-email 2.10.0",
        "In-Reply-To": "<20160926182917.27531-1-paul.burton@imgtec.com>",
        "References": "<20160926182917.27531-1-paul.burton@imgtec.com>",
        "MIME-Version": "1.0",
        "X-Originating-IP": "[10.100.200.111]",
        "Subject": "[U-Boot] [PATCH 05/23] pci: xilinx: Avoid writing memory base or\n\tlimit registers",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>",
        "List-Post": "<mailto:u-boot@lists.denx.de>",
        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "Content-Type": "text/plain; charset=\"us-ascii\"",
        "Content-Transfer-Encoding": "7bit",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>"
    },
    "content": "Writing the PCI memory base & limit registers leads to the root bridge\nreporting a PCI_MEMORY_BASE value of 0 & a PCI_MEMORY_LIMIT value of\n0x1600. If we then boot Linux, it sees that the bridge device needs\n0x16000000 bytes of memory space & fails to assign it.\n\nIt's unclear to me why this happens, and poking values from the shell\ndoesn't seem to make anything clearer, but this workaround allows a MIPS\nBoston board to boot Linux & let Linux successfully probe the PCIe bus &\nall devices connected to it.\n\nSigned-off-by: Paul Burton <paul.burton@imgtec.com>\n---\n\n drivers/pci/pcie_xilinx.c | 9 +++++++++\n 1 file changed, 9 insertions(+)",
    "diff": "diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c\nindex 9059c41..0237bec 100644\n--- a/drivers/pci/pcie_xilinx.c\n+++ b/drivers/pci/pcie_xilinx.c\n@@ -160,6 +160,15 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,\n \tif (err < 0)\n \t\treturn 0;\n \n+\tif (bdf == PCI_BDF(bus->seq, 0, 0)) {\n+\t\tswitch (offset) {\n+\t\tcase PCI_MEMORY_BASE:\n+\t\tcase PCI_MEMORY_LIMIT:\n+\t\t\t/* Writing the memory base or limit causes problems */\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n \tswitch (size) {\n \tcase PCI_SIZE_8:\n \t\t__raw_writeb(value, address);\n",
    "prefixes": [
        "U-Boot",
        "05/23"
    ]
}