Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/660294/?format=api
{ "id": 660294, "url": "http://patchwork.ozlabs.org/api/patches/660294/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1471475048-25835-2-git-send-email-bimmy.pujari@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1471475048-25835-2-git-send-email-bimmy.pujari@intel.com>", "list_archive_url": null, "date": "2016-08-17T23:04:07", "name": "[next,S43,2/3] i40e/i40evf: Fix indentation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "9327d5e4b4b18162d71e9ea542b801526f28259a", "submitter": { "id": 68919, "url": "http://patchwork.ozlabs.org/api/people/68919/?format=api", "name": "Pujari, Bimmy", "email": "bimmy.pujari@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1471475048-25835-2-git-send-email-bimmy.pujari@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/660294/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/660294/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3sF4b40xD2z9t1b\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 18 Aug 2016 09:05:52 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id B593B8A02B;\n\tWed, 17 Aug 2016 23:05:50 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id AZKXWT9WJqWK; Wed, 17 Aug 2016 23:05:48 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 8C1DA89FDD;\n\tWed, 17 Aug 2016 23:05:48 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id D8D081C11F2\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 17 Aug 2016 23:05:46 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D50D78B873\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 17 Aug 2016 23:05:46 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id RNiPCL77YegN for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 17 Aug 2016 23:05:45 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id CB9208B73E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 17 Aug 2016 23:05:45 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga101.jf.intel.com with ESMTP; 17 Aug 2016 16:05:08 -0700", "from bimmy.jf.intel.com (HELO bimmy.linux1.jf.intel.com)\n\t([134.134.2.177])\n\tby fmsmga002.fm.intel.com with ESMTP; 17 Aug 2016 16:04:40 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.28,536,1464678000\"; d=\"scan'208\";\n\ta=\"1043087066\"", "From": "Bimmy Pujari <bimmy.pujari@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 17 Aug 2016 16:04:07 -0700", "Message-Id": "<1471475048-25835-2-git-send-email-bimmy.pujari@intel.com>", "X-Mailer": "git-send-email 2.4.11", "In-Reply-To": "<1471475048-25835-1-git-send-email-bimmy.pujari@intel.com>", "References": "<1471475048-25835-1-git-send-email-bimmy.pujari@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S43 2/3] i40e/i40evf: Fix indentation", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>\n\nSeveral defines and code comments were indented with spaces instead\nof tabs, correct the issue to make indentation consistent.\n\nSigned-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>\nChange-ID: I0dc6bbb990ec4a9e856acc9ec526d876181f092c\n---\n drivers/net/ethernet/intel/i40e/i40e.h | 127 +++++++++++++++--------------\n drivers/net/ethernet/intel/i40evf/i40evf.h | 57 +++++++------\n 2 files changed, 94 insertions(+), 90 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h\nindex 03f4c97..13682b4 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e.h\n@@ -66,36 +66,36 @@\n #include \"i40e_dcb.h\"\n \n /* Useful i40e defaults */\n-#define I40E_MAX_VEB 16\n-\n-#define I40E_MAX_NUM_DESCRIPTORS 4096\n-#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)\n-#define I40E_DEFAULT_NUM_DESCRIPTORS 512\n-#define I40E_REQ_DESCRIPTOR_MULTIPLE 32\n-#define I40E_MIN_NUM_DESCRIPTORS 64\n-#define I40E_MIN_MSIX 2\n-#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */\n-#define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */\n+#define I40E_MAX_VEB\t\t16\n+\n+#define I40E_MAX_NUM_DESCRIPTORS\t4096\n+#define I40E_MAX_CSR_SPACE\t\t(4 * 1024 * 1024 - 64 * 1024)\n+#define I40E_DEFAULT_NUM_DESCRIPTORS\t512\n+#define I40E_REQ_DESCRIPTOR_MULTIPLE\t32\n+#define I40E_MIN_NUM_DESCRIPTORS\t64\n+#define I40E_MIN_MSIX\t\t\t2\n+#define I40E_DEFAULT_NUM_VMDQ_VSI\t8 /* max 256 VSIs */\n+#define I40E_MIN_VSI_ALLOC\t\t51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */\n /* max 16 qps */\n #define i40e_default_queues_per_vmdq(pf) \\\n \t\t(((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)\n-#define I40E_DEFAULT_QUEUES_PER_VF 4\n-#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */\n+#define I40E_DEFAULT_QUEUES_PER_VF\t4\n+#define I40E_DEFAULT_QUEUES_PER_TC\t1 /* should be a power of 2 */\n #define i40e_pf_get_max_q_per_tc(pf) \\\n \t\t(((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)\n-#define I40E_FDIR_RING 0\n-#define I40E_FDIR_RING_COUNT 32\n #ifdef I40E_FCOE\n #define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */\n #define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */\n #endif /* I40E_FCOE */\n-#define I40E_MAX_AQ_BUF_SIZE 4096\n-#define I40E_AQ_LEN 256\n-#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */\n-#define I40E_MAX_USER_PRIORITY 8\n-#define I40E_DEFAULT_MSG_ENABLE 4\n-#define I40E_QUEUE_WAIT_RETRY_LIMIT 10\n-#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)\n+#define I40E_FDIR_RING\t\t\t0\n+#define I40E_FDIR_RING_COUNT\t\t32\n+#define I40E_MAX_AQ_BUF_SIZE\t\t4096\n+#define I40E_AQ_LEN\t\t\t256\n+#define I40E_AQ_WORK_LIMIT\t\t66 /* max number of VFs + a little */\n+#define I40E_MAX_USER_PRIORITY\t\t8\n+#define I40E_DEFAULT_MSG_ENABLE\t\t4\n+#define I40E_QUEUE_WAIT_RETRY_LIMIT\t10\n+#define I40E_INT_NAME_STR_LEN\t\t(IFNAMSIZ + 16)\n \n /* Ethtool Private Flags */\n #define\tI40E_PRIV_FLAGS_MFP_FLAG\t\tBIT(0)\n@@ -105,37 +105,37 @@\n #define I40E_PRIV_FLAGS_HW_ATR_EVICT\t\tBIT(4)\n #define I40E_PRIV_FLAGS_TRUE_PROMISC_SUPPORT\tBIT(5)\n \n-#define I40E_NVM_VERSION_LO_SHIFT 0\n-#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)\n-#define I40E_NVM_VERSION_HI_SHIFT 12\n-#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)\n-#define I40E_OEM_VER_BUILD_MASK 0xffff\n-#define I40E_OEM_VER_PATCH_MASK 0xff\n-#define I40E_OEM_VER_BUILD_SHIFT 8\n-#define I40E_OEM_VER_SHIFT 24\n+#define I40E_NVM_VERSION_LO_SHIFT\t0\n+#define I40E_NVM_VERSION_LO_MASK\t(0xff << I40E_NVM_VERSION_LO_SHIFT)\n+#define I40E_NVM_VERSION_HI_SHIFT\t12\n+#define I40E_NVM_VERSION_HI_MASK\t(0xf << I40E_NVM_VERSION_HI_SHIFT)\n+#define I40E_OEM_VER_BUILD_MASK\t\t0xffff\n+#define I40E_OEM_VER_PATCH_MASK\t\t0xff\n+#define I40E_OEM_VER_BUILD_SHIFT\t8\n+#define I40E_OEM_VER_SHIFT\t\t24\n #define I40E_PHY_DEBUG_ALL \\\n \t(I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \\\n \tI40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)\n \n /* The values in here are decimal coded as hex as is the case in the NVM map*/\n-#define I40E_CURRENT_NVM_VERSION_HI 0x2\n-#define I40E_CURRENT_NVM_VERSION_LO 0x40\n+#define I40E_CURRENT_NVM_VERSION_HI\t0x2\n+#define I40E_CURRENT_NVM_VERSION_LO\t0x40\n \n /* magic for getting defines into strings */\n-#define STRINGIFY(foo) #foo\n-#define XSTRINGIFY(bar) STRINGIFY(bar)\n+#define STRINGIFY(foo)\t#foo\n+#define XSTRINGIFY(bar)\tSTRINGIFY(bar)\n \n-#define I40E_RX_DESC(R, i)\t\t\t\\\n+#define I40E_RX_DESC(R, i)\t\t\\\n \t(&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))\n-#define I40E_TX_DESC(R, i)\t\t\t\\\n+#define I40E_TX_DESC(R, i)\t\t\\\n \t(&(((struct i40e_tx_desc *)((R)->desc))[i]))\n-#define I40E_TX_CTXTDESC(R, i)\t\t\t\\\n+#define I40E_TX_CTXTDESC(R, i)\t\t\\\n \t(&(((struct i40e_tx_context_desc *)((R)->desc))[i]))\n-#define I40E_TX_FDIRDESC(R, i)\t\t\t\\\n+#define I40E_TX_FDIRDESC(R, i)\t\t\\\n \t(&(((struct i40e_filter_program_desc *)((R)->desc))[i]))\n \n /* default to trying for four seconds */\n-#define I40E_TRY_LINK_TIMEOUT (4 * HZ)\n+#define I40E_TRY_LINK_TIMEOUT\t(4 * HZ)\n \n /**\n * i40e_is_mac_710 - Return true if MAC is X710/XL710\n@@ -200,9 +200,9 @@ struct i40e_lump_tracking {\n #define I40E_FDIR_BUFFER_HEAD_ROOM\t32\n #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)\n \n-#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)\n-#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)\n-#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)\n+#define I40E_HKEY_ARRAY_SIZE\t((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)\n+#define I40E_HLUT_ARRAY_SIZE\t((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)\n+#define I40E_VF_HLUT_ARRAY_SIZE\t((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)\n \n enum i40e_fd_stat_idx {\n \tI40E_FD_STAT_ATR,\n@@ -388,8 +388,8 @@ struct i40e_pf {\n \tstruct mutex switch_mutex;\n \tu16 lan_vsi; /* our default LAN VSI */\n \tu16 lan_veb; /* initial relay, if exists */\n-#define I40E_NO_VEB 0xffff\n-#define I40E_NO_VSI 0xffff\n+#define I40E_NO_VEB\t0xffff\n+#define I40E_NO_VSI\t0xffff\n \tu16 next_vsi; /* Next unallocated VSI - 0-based! */\n \tstruct i40e_vsi **vsi;\n \tstruct i40e_veb *veb[I40E_MAX_VEB];\n@@ -424,8 +424,8 @@ struct i40e_pf {\n \t */\n \tu16 dcbx_cap;\n \n-\tu32\tfcoe_hmc_filt_num;\n-\tu32\tfcoe_hmc_cntx_num;\n+\tu32 fcoe_hmc_filt_num;\n+\tu32 fcoe_hmc_cntx_num;\n \tstruct i40e_filter_control_settings filter_settings;\n \n \tstruct ptp_clock *ptp_clock;\n@@ -486,10 +486,10 @@ struct i40e_mac_filter {\n struct i40e_veb {\n \tstruct i40e_pf *pf;\n \tu16 idx;\n-\tu16 veb_idx; /* index of VEB parent */\n+\tu16 veb_idx;\t\t/* index of VEB parent */\n \tu16 seid;\n \tu16 uplink_seid;\n-\tu16 stats_idx; /* index of VEB parent */\n+\tu16 stats_idx;\t\t/* index of VEB parent */\n \tu8 enabled_tc;\n \tu16 bridge_mode;\t/* Bridge Mode (VEB/VEPA) */\n \tu16 flags;\n@@ -552,12 +552,13 @@ struct i40e_vsi {\n \tu32 promisc_threshold;\n \n \tu16 work_limit;\n-\tu16 int_rate_limit; /* value in usecs */\n+\tu16 int_rate_limit;\t/* value in usecs */\n+\n+\tu16 rss_table_size;\t/* HW RSS table size */\n+\tu16 rss_size;\t\t/* Allocated RSS queues */\n+\tu8 *rss_hkey_user;\t/* User configured hash keys */\n+\tu8 *rss_lut_user;\t/* User configured lookup table entries */\n \n-\tu16 rss_table_size; /* HW RSS table size */\n-\tu16 rss_size; /* Allocated RSS queues */\n-\tu8 *rss_hkey_user; /* User configured hash keys */\n-\tu8 *rss_lut_user; /* User configured lookup table entries */\n \n \tu16 max_frame;\n \tu16 rx_buf_len;\n@@ -568,14 +569,14 @@ struct i40e_vsi {\n \tint base_vector;\n \tbool irqs_ready;\n \n-\tu16 seid; /* HW index of this VSI (absolute index) */\n-\tu16 id; /* VSI number */\n+\tu16 seid;\t\t/* HW index of this VSI (absolute index) */\n+\tu16 id;\t\t\t/* VSI number */\n \tu16 uplink_seid;\n \n-\tu16 base_queue; /* vsi's first queue in hw array */\n-\tu16 alloc_queue_pairs; /* Allocated Tx/Rx queues */\n-\tu16 req_queue_pairs; /* User requested queue pairs */\n-\tu16 num_queue_pairs; /* Used tx and rx pairs */\n+\tu16 base_queue;\t\t/* vsi's first queue in hw array */\n+\tu16 alloc_queue_pairs;\t/* Allocated Tx/Rx queues */\n+\tu16 req_queue_pairs;\t/* User requested queue pairs */\n+\tu16 num_queue_pairs;\t/* Used tx and rx pairs */\n \tu16 num_desc;\n \tenum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */\n \ts16 vf_id;\t\t/* Virtual function ID for SRIOV VSIs */\n@@ -594,11 +595,11 @@ struct i40e_vsi {\n \t/* TC BW limit max quanta within VSI */\n \tu8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];\n \n-\tstruct i40e_pf *back; /* Backreference to associated PF */\n-\tu16 idx; /* index in pf->vsi[] */\n-\tu16 veb_idx; /* index of VEB parent */\n-\tstruct kobject *kobj; /* sysfs object */\n-\tbool current_isup; /* Sync 'link up' logging */\n+\tstruct i40e_pf *back;\t/* Backreference to associated PF */\n+\tu16 idx;\t\t/* index in pf->vsi[] */\n+\tu16 veb_idx;\t\t/* index of VEB parent */\n+\tstruct kobject *kobj;\t/* sysfs object */\n+\tbool current_isup;\t/* Sync 'link up' logging */\n \n \tvoid *priv;\t/* client driver data reference. */\n \ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf.h b/drivers/net/ethernet/intel/i40evf/i40evf.h\nindex be1ca4c..c5fd724 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf.h\n@@ -64,20 +64,20 @@ struct i40e_vsi {\n \n /* How many Rx Buffers do we bundle into one write to the hardware ? */\n #define I40EVF_RX_BUFFER_WRITE\t16\t/* Must be power of 2 */\n-#define I40EVF_DEFAULT_TXD 512\n-#define I40EVF_DEFAULT_RXD 512\n-#define I40EVF_MAX_TXD 4096\n-#define I40EVF_MIN_TXD 64\n-#define I40EVF_MAX_RXD 4096\n-#define I40EVF_MIN_RXD 64\n-#define I40EVF_REQ_DESCRIPTOR_MULTIPLE 32\n+#define I40EVF_DEFAULT_TXD\t512\n+#define I40EVF_DEFAULT_RXD\t512\n+#define I40EVF_MAX_TXD\t\t4096\n+#define I40EVF_MIN_TXD\t\t64\n+#define I40EVF_MAX_RXD\t\t4096\n+#define I40EVF_MIN_RXD\t\t64\n+#define I40EVF_REQ_DESCRIPTOR_MULTIPLE\t32\n \n /* Supported Rx Buffer Sizes */\n-#define I40EVF_RXBUFFER_2048 2048\n-#define I40EVF_MAX_RXBUFFER 16384 /* largest size for single descriptor */\n-#define I40EVF_MAX_AQ_BUF_SIZE 4096\n-#define I40EVF_AQ_LEN 32\n-#define I40EVF_AQ_MAX_ERR 20 /* times to try before resetting AQ */\n+#define I40EVF_RXBUFFER_2048\t2048\n+#define I40EVF_MAX_RXBUFFER\t16384 /* largest size for single descriptor */\n+#define I40EVF_MAX_AQ_BUF_SIZE\t4096\n+#define I40EVF_AQ_LEN\t\t32\n+#define I40EVF_AQ_MAX_ERR\t20 /* times to try before resetting AQ */\n \n #define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)\n \n@@ -104,7 +104,7 @@ struct i40e_q_vector {\n \tu8 num_ringpairs;\t/* total number of ring pairs in vector */\n #define ITR_COUNTDOWN_START 100\n \tu8 itr_countdown;\t/* when 0 or 1 update ITR */\n-\tint v_idx;\t /* vector index in list */\n+\tint v_idx;\t/* vector index in list */\n \tchar name[IFNAMSIZ + 9];\n \tbool arm_wb_state;\n \tcpumask_var_t affinity_mask;\n@@ -122,11 +122,11 @@ struct i40e_q_vector {\n \t((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \\\n \t(R)->next_to_clean - (R)->next_to_use - 1)\n \n-#define I40EVF_RX_DESC_ADV(R, i)\t \\\n+#define I40EVF_RX_DESC_ADV(R, i)\t\\\n \t(&(((union i40e_adv_rx_desc *)((R).desc))[i]))\n-#define I40EVF_TX_DESC_ADV(R, i)\t \\\n+#define I40EVF_TX_DESC_ADV(R, i)\t\\\n \t(&(((union i40e_adv_tx_desc *)((R).desc))[i]))\n-#define I40EVF_TX_CTXTDESC_ADV(R, i)\t \\\n+#define I40EVF_TX_CTXTDESC_ADV(R, i)\t\\\n \t(&(((struct i40e_adv_tx_context_desc *)((R).desc))[i]))\n \n #define OTHER_VECTOR 1\n@@ -197,22 +197,25 @@ struct i40evf_adapter {\n \tstruct msix_entry *msix_entries;\n \n \tu32 flags;\n-#define I40EVF_FLAG_RX_CSUM_ENABLED BIT(0)\n-#define I40EVF_FLAG_IMIR_ENABLED BIT(5)\n-#define I40EVF_FLAG_MQ_CAPABLE BIT(6)\n-#define I40EVF_FLAG_NEED_LINK_UPDATE BIT(7)\n-#define I40EVF_FLAG_PF_COMMS_FAILED BIT(8)\n-#define I40EVF_FLAG_RESET_PENDING BIT(9)\n-#define I40EVF_FLAG_RESET_NEEDED BIT(10)\n+#define I40EVF_FLAG_RX_CSUM_ENABLED\t\tBIT(0)\n+#define I40EVF_FLAG_IN_NETPOLL\t\t\tBIT(4)\n+#define I40EVF_FLAG_IMIR_ENABLED\t\tBIT(5)\n+#define I40EVF_FLAG_MQ_CAPABLE\t\t\tBIT(6)\n+#define I40EVF_FLAG_NEED_LINK_UPDATE\t\tBIT(7)\n+#define I40EVF_FLAG_PF_COMMS_FAILED\t\tBIT(8)\n+#define I40EVF_FLAG_RESET_PENDING\t\tBIT(9)\n+#define I40EVF_FLAG_RESET_NEEDED\t\tBIT(10)\n #define I40EVF_FLAG_WB_ON_ITR_CAPABLE\t\tBIT(11)\n #define I40EVF_FLAG_OUTER_UDP_CSUM_CAPABLE\tBIT(12)\n #define I40EVF_FLAG_ADDR_SET_BY_PF\t\tBIT(13)\n+#define I40EVF_FLAG_SERVICE_CLIENT_REQUESTED\tBIT(14)\n #define I40EVF_FLAG_PROMISC_ON\t\t\tBIT(15)\n #define I40EVF_FLAG_ALLMULTI_ON\t\t\tBIT(16)\n /* duplicates for common code */\n-#define I40E_FLAG_FDIR_ATR_ENABLED\t\t 0\n-#define I40E_FLAG_DCB_ENABLED\t\t\t 0\n-#define I40E_FLAG_RX_CSUM_ENABLED I40EVF_FLAG_RX_CSUM_ENABLED\n+#define I40E_FLAG_FDIR_ATR_ENABLED\t\t0\n+#define I40E_FLAG_DCB_ENABLED\t\t\t0\n+#define I40E_FLAG_IN_NETPOLL\t\t\tI40EVF_FLAG_IN_NETPOLL\n+#define I40E_FLAG_RX_CSUM_ENABLED\t\tI40EVF_FLAG_RX_CSUM_ENABLED\n #define I40E_FLAG_WB_ON_ITR_CAPABLE\t\tI40EVF_FLAG_WB_ON_ITR_CAPABLE\n #define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE\tI40EVF_FLAG_OUTER_UDP_CSUM_CAPABLE\n \t/* flags for admin queue service task */\n@@ -226,7 +229,7 @@ struct i40evf_adapter {\n #define I40EVF_FLAG_AQ_CONFIGURE_QUEUES\t\tBIT(6)\n #define I40EVF_FLAG_AQ_MAP_VECTORS\t\tBIT(7)\n #define I40EVF_FLAG_AQ_HANDLE_RESET\t\tBIT(8)\n-#define I40EVF_FLAG_AQ_CONFIGURE_RSS\t\tBIT(9)\t/* direct AQ config */\n+#define I40EVF_FLAG_AQ_CONFIGURE_RSS\t\tBIT(9) /* direct AQ config */\n #define I40EVF_FLAG_AQ_GET_CONFIG\t\tBIT(10)\n /* Newer style, RSS done by the PF so we can ignore hardware vagaries. */\n #define I40EVF_FLAG_AQ_GET_HENA\t\t\tBIT(11)\n", "prefixes": [ "next", "S43", "2/3" ] }