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GET /api/patches/633523/?format=api
{ "id": 633523, "url": "http://patchwork.ozlabs.org/api/patches/633523/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/1465535032-26749-24-git-send-email-gwshan@linux.vnet.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1465535032-26749-24-git-send-email-gwshan@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2016-06-10T05:03:52", "name": "[v12,23/23] doc: PCI slot", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "68c4c0df14c92121abc4ab3796e43b7b7486d781", "submitter": { "id": 63923, "url": "http://patchwork.ozlabs.org/api/people/63923/?format=api", "name": "Gavin Shan", "email": "gwshan@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/1465535032-26749-24-git-send-email-gwshan@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/633523/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/633523/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3rQqvC1DKDz9sD3\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Jun 2016 15:08:23 +1000 (AEST)", "from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3rQqvC0TJDzDqfM\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Jun 2016 15:08:23 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3rQqrt5hmdzDqQW\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:06:22 +1000 (AEST)", "from pps.filterd (m0049461.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id\n\tu5A53rl7013164\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 01:06:20 -0400", "from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 23fa5xy89g-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 01:06:20 -0400", "from localhost\n\tby e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Fri, 10 Jun 2016 15:04:00 +1000 (AEST)" ], "X-IBM-Helo": "d23dlp03.au.ibm.com", "X-IBM-MailFrom": "gwshan@linux.vnet.ibm.com", "X-IBM-RcptTo": "skiboot@lists.ozlabs.org", "From": "Gavin Shan <gwshan@linux.vnet.ibm.com>", "To": "skiboot@lists.ozlabs.org", "Date": "Fri, 10 Jun 2016 15:03:52 +1000", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1465535032-26749-1-git-send-email-gwshan@linux.vnet.ibm.com>", "References": "<1465535032-26749-1-git-send-email-gwshan@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "16061005-0008-0000-0000-000000971711", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "16061005-0009-0000-0000-0000076DBDE1", "Message-Id": "<1465535032-26749-24-git-send-email-gwshan@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2016-06-10_04:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000\n\tdefinitions=main-1606100058", "Subject": "[Skiboot] [PATCH v12 23/23] doc: PCI slot", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.22", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Cc": "alistair@popple.id.au", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "This renames document pci-slot-properties.txt to pci-slot.txt and\nmore description added regarding the new introduced functionalities\nto PCI slot by the series of patches.\n\nSigned-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>\n---\n doc/pci-slot-properties.txt | 17 -------\n doc/pci-slot.txt | 119 ++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 119 insertions(+), 17 deletions(-)\n delete mode 100644 doc/pci-slot-properties.txt\n create mode 100644 doc/pci-slot.txt", "diff": "diff --git a/doc/pci-slot-properties.txt b/doc/pci-slot-properties.txt\ndeleted file mode 100644\nindex 2ee34ea..0000000\n--- a/doc/pci-slot-properties.txt\n+++ /dev/null\n@@ -1,17 +0,0 @@\n-\n-PCI Slot Properties Description\n-===============================\n-\n-The following properties have been added to the PCI Device Tree Node\n-for the PCI Slot:\n-\n-ibm,slot-location-code\t\tSystem location code string for the slot connector\n-ibm,slot-pluggable Boolean indicating whether the slot is pluggable\n-ibm,slot-power-ctl\t\tBoolean indicating whether the slot has power control\n-ibm,slot-wired-lanes The number of hardware lanes that are wired (optional)\n-ibm,slot-connector-type\t\tThe type of connector present (optional)\n-ibm,slot-card-desc\t\tThe height/length of the slot (optional)\n-ibm,slot-card-mech Value indicating slot mechanicals and orientation (optional)\n-ibm,slot-pwr-led-ctl Presence of slot power led, and controlling entity (optional)\n-ibm,slot-attn-led-ctl \tPresence of slot ATTN led, and controlling entity (optional)\n-\ndiff --git a/doc/pci-slot.txt b/doc/pci-slot.txt\nnew file mode 100644\nindex 0000000..1b64f69\n--- /dev/null\n+++ b/doc/pci-slot.txt\n@@ -0,0 +1,119 @@\n+Overview\n+========\n+\n+The PCI slots are instantiated to represent their associated properties and\n+operations. The slot properties are exported to OS through the device tree\n+node of the corresponding parent PCI device. The slot operations are used\n+to accomodate requests from OS regarding the indicated PCI slot:\n+\n+ * PCI slot reset\n+ * PCI slot property retrival\n+\n+The PCI slots are expected to be created by individual platforms based on\n+the given templates, which are classified to PHB slot or normal one currently.\n+The PHB slot is instantiated based on PHB types like P7IOC and PHB3. However,\n+the normal PCI slots are created based on general RC (Root Complex), PCIE switch\n+ports, PCIE-to-PCIx bridge. Individual platform may create PCI slot, which doesn't\n+have existing template.\n+\n+The PCI slots are created at different stages according to their types. PHB slots\n+are expected to be created once the PHB is register (struct platform::pci_setup_phb())\n+because the PHB slot reset operations are required at early stage of PCI enumeration.\n+The normal slots are populated after their parent PCI devices are instantiated at\n+struct platform::pci_get_slot_info().\n+\n+The operation set supplied by the template might be overrided and reimplemented, or\n+partially. It's usually done according to the VPD figured out by individual platforms.\n+\n+PCI Slot Operations\n+===================\n+\n+The following operations are supported to one particular PCI slot. More details\n+could be found from the definition of struct pci_slot_ops:\n+\n+get_presence_state Check if any adapter connected to slot\n+get_link_state Retrieve PCIE link status: up, down, link width\n+get_power_state Retrieve the power status: on, off\n+get_attention_state Retrieve attention status: on, off, blinking\n+get_latch_state Retrieve latch status\n+set_power_state Configure the power status: on, off\n+set_attention_state Configure attention status: on, off, blinking\n+\n+prepare_link_change Prepare PCIE link status change\n+poll_link Poll PCIE link until it's up or down permanently\n+creset Complete reset, only available to PHB slot\n+freset Fundamental reset\n+pfreset Post fundamental reset\n+hreset Hot reset\n+poll Interface for OPAL API to drive internal state machine\n+\n+add_properties Additional PCI slot properties seen by platform\n+\n+PCI Slot Properties\n+===================\n+\n+The following PCI slot properties have been exported through PCI device tree\n+node for a root port, a PCIE switch port, or a PCIE to PCIx bridge. If the\n+individual platforms (e.g. Firenze and Apollo) have VPD for the PCI slot, they\n+should extract the PCI slot properties from VPD and export them accordingly.\n+\n+ibm,reset-by-firmware Boolean indicating whether the slot reset should be\n+ done in firmware\n+ibm,slot-pluggable Boolean indicating whether the slot is pluggable\n+ibm,slot-power-ctl Boolean indicating whether the slot has power control\n+ibm,slot-wired-lanes The number of hardware lanes that are wired\n+ibm,slot-pwr-led-ctl Presence of slot power led, and controlling entity\n+ibm,slot-attn-led-ctl Presence of slot ATTN led, and controlling entity\n+\n+PCI Hotplug\n+===========\n+\n+The implementation of PCI slot hotplug heavily relies on its power state.\n+Initially, the slot is powered off if there are no adapters behind it.\n+Otherwise, the slot should be powered on.\n+\n+In hot add scenario, the adapter is physically inserted to PCI slot. Then\n+the PCI slot is powered on by OPAL API opal_pci_set_power_state(). The\n+power is supplied to the PCI slot, the adapter behind the PCI slot is\n+probed and the device sub-tree (for hot added devices) is populated. A\n+OPAL message is sent to OS on completion. The OS needs retrieve the device\n+sub-tree through OPAL API opal_get_device_tree(), unflatten it and populate\n+the device sub-tree. After that, the adapter behind the PCI slot should\n+be probed and added to the system.\n+\n+On the other hand, the OS removes the adapter behind the PCI slot before\n+calling opal_pci_set_power_state(). Skiboot cuts off the power supply to\n+the PCI slot, removes the adapter behind the PCI slot and the corresponding\n+device sub-tree. A OPAL message (OPAL_MSG_ASYNC_COMP) is sent to OS. The\n+OS removes the device sub-tree for the adapter behind the PCI slot.\n+\n+The OPAL message used in PCI hotplug is comprised of 4 dwords in sequence:\n+asychronous token from OS, PCI slot device node's phandle, OPAL_PCI_SLOT_POWER_{ON,\n+OFF}, OPAL_SUCCESS or errcode.\n+\n+The states OPAL_PCI_SLOT_OFFLINE and OPAL_PCI_SLOT_ONLINE are used for removing\n+or adding devices behind the slot. The device nodes in the device tree are\n+removed or added accordingly, without actually changing the slot's power state.\n+The API call will return OPAL_SUCCESS immediately and no further asynchronous\n+message will be sent.\n+\n+PCI Slot on Apollo and Firenze\n+==============================\n+\n+On IBM's Apollo and Firenze platform, the PCI VPD is fetched from dedicated LID,\n+which is organized in so-called 1004, 1005, or 1006 format. 1006 mapping format\n+isn't supported currently. The PCI slot properties are figured out from the VPD.\n+On the other hand, there might have external power management entity hooked to\n+I2C buses for one PCI slot. The fundamental reset operation of the PCI slot should\n+be implemented based on the external power management entity for that case.\n+\n+On Firenze platform, PERST pin is accessible through bit#10 of PCI config register\n+(offset: 0x80) for those PCI slots behind some PLX switch downstream ports. For\n+those PCI slots, PERST pin is utilized to implement fundamental reset if external\n+power management entity doesn't exist.\n+\n+For Apollo and Firenze platform, following PCI slot properties are exported through\n+PCI device tree node except those generic properties (as above):\n+\n+ibm,slot-location-code System location code string for the slot connector\n+ibm,slot-label Slot label, part of \"ibm,slot-location-code\"\n", "prefixes": [ "v12", "23/23" ] }