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GET /api/patches/633513/?format=api
{ "id": 633513, "url": "http://patchwork.ozlabs.org/api/patches/633513/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/1465535032-26749-18-git-send-email-gwshan@linux.vnet.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1465535032-26749-18-git-send-email-gwshan@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2016-06-10T05:03:46", "name": "[v12,17/23] hw/npu: Support PHB slot", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "edb57e2b5578ef1b1f61354b01389244044877ef", "submitter": { "id": 63923, "url": "http://patchwork.ozlabs.org/api/people/63923/?format=api", "name": "Gavin Shan", "email": "gwshan@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/1465535032-26749-18-git-send-email-gwshan@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/633513/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/633513/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3rQqsY1Mjhz9sD3\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Jun 2016 15:06:57 +1000 (AEST)", "from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3rQqsY0YFCzDqYn\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Jun 2016 15:06:57 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3rQqqw40t9zDqJp\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:05:32 +1000 (AEST)", "from pps.filterd (m0098399.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id\n\tu5A53svv067761\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 01:05:31 -0400", "from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 23e9m55u9w-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 01:05:30 -0400", "from localhost\n\tby e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tFri, 10 Jun 2016 15:05:26 +1000", "from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37])\n\tby d23dlp03.au.ibm.com (Postfix) with ESMTP id A24983578058\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:05:20 +1000 (EST)", "from d23av05.au.ibm.com (d23av05.au.ibm.com [9.190.234.119])\n\tby d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tu5A555Vv11665720\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:05:10 +1000", "from d23av05.au.ibm.com (localhost [127.0.0.1])\n\tby d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tu5A54x18024764\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:04:59 +1000", "from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14])\n\tby d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tu5A54xLD024623; Fri, 10 Jun 2016 15:04:59 +1000", "from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114])\n\tby ozlabs.au.ibm.com (Postfix) with ESMTP id 048DCA0211;\n\tFri, 10 Jun 2016 15:03:59 +1000 (AEST)", "from gwshan (shangw.ozlabs.ibm.com [10.61.2.199])\n\tby bran.ozlabs.ibm.com (Postfix) with ESMTP id 00BB4E3B1A;\n\tFri, 10 Jun 2016 15:03:59 +1000 (AEST)", "by gwshan (Postfix, from userid 1000)\n\tid DAFFC942CA3; Fri, 10 Jun 2016 15:03:58 +1000 (AEST)" ], "X-IBM-Helo": "d23dlp03.au.ibm.com", "X-IBM-MailFrom": "gwshan@linux.vnet.ibm.com", "X-IBM-RcptTo": "skiboot@lists.ozlabs.org", "From": "Gavin Shan <gwshan@linux.vnet.ibm.com>", "To": "skiboot@lists.ozlabs.org", "Date": "Fri, 10 Jun 2016 15:03:46 +1000", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1465535032-26749-1-git-send-email-gwshan@linux.vnet.ibm.com>", "References": "<1465535032-26749-1-git-send-email-gwshan@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "16061005-0048-0000-0000-000001904997", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "16061005-0049-0000-0000-000045E8DBD3", "Message-Id": "<1465535032-26749-18-git-send-email-gwshan@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2016-06-10_04:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000\n\tdefinitions=main-1606100058", "Subject": "[Skiboot] [PATCH v12 17/23] hw/npu: Support PHB slot", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.22", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Cc": "alistair@popple.id.au", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "This creates PCI slot before the PHB is registered. Nothing has\nbeen done in the PCI slot operations except to keep the PCI probe\ncode going.\n\nSigned-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>\nReviewed-by: Russell Currey <ruscur@russell.cc>\n---\n hw/npu.c | 57 ++++++++++++++++++++++++++++++++++++++++++---------------\n 1 file changed, 42 insertions(+), 15 deletions(-)", "diff": "diff --git a/hw/npu.c b/hw/npu.c\nindex f57d34d..c371f4c 100644\n--- a/hw/npu.c\n+++ b/hw/npu.c\n@@ -18,6 +18,7 @@\n #include <timebase.h>\n #include <pci.h>\n #include <pci-cfg.h>\n+#include <pci-slot.h>\n #include <interrupts.h>\n #include <opal.h>\n #include <opal-api.h>\n@@ -972,27 +973,29 @@ static int64_t npu_set_pe(struct phb *phb,\n \treturn OPAL_SUCCESS;\n }\n \n-static int64_t npu_link_state(struct phb *phb __unused)\n+static int64_t npu_get_link_state(struct pci_slot *slot __unused, uint8_t *val)\n {\n \t/* As we're emulating all PCI stuff, the link bandwidth\n \t * isn't big deal anyway.\n \t */\n-\treturn OPAL_SHPC_LINK_UP_x1;\n+\t*val = OPAL_SHPC_LINK_UP_x1;\n+\treturn OPAL_SUCCESS;\n }\n \n-static int64_t npu_power_state(struct phb *phb __unused)\n+static int64_t npu_get_power_state(struct pci_slot *slot __unused, uint8_t *val)\n {\n-\treturn OPAL_SHPC_POWER_ON;\n+\t*val = PCI_SLOT_POWER_ON;\n+\treturn OPAL_SUCCESS;\n }\n \n-static int64_t npu_hreset(struct phb *phb __unused)\n+static int64_t npu_hreset(struct pci_slot *slot __unused)\n {\n \tprlog(PR_DEBUG, \"NPU: driver should call reset procedure here\\n\");\n \n \treturn OPAL_SUCCESS;\n }\n \n-static int64_t npu_freset(struct phb *phb __unused)\n+static int64_t npu_freset(struct pci_slot *slot __unused)\n {\n \t/* FIXME: PHB fundamental reset, which need to be\n \t * figured out later. It's used by EEH recovery\n@@ -1001,6 +1004,33 @@ static int64_t npu_freset(struct phb *phb __unused)\n \treturn OPAL_SUCCESS;\n }\n \n+static struct pci_slot *npu_slot_create(struct phb *phb)\n+{\n+\tstruct pci_slot *slot;\n+\n+\tslot = pci_slot_alloc(phb, NULL);\n+\tif (!slot)\n+\t\treturn slot;\n+\n+\t/* Elementary functions */\n+\tslot->ops.get_presence_state = NULL;\n+\tslot->ops.get_link_state = npu_get_link_state;\n+\tslot->ops.get_power_state = npu_get_power_state;\n+\tslot->ops.get_attention_state = NULL;\n+\tslot->ops.get_latch_state = NULL;\n+\tslot->ops.set_power_state = NULL;\n+\tslot->ops.set_attention_state = NULL;\n+\n+\tslot->ops.prepare_link_change = NULL;\n+\tslot->ops.poll_link = NULL;\n+\tslot->ops.hreset = npu_hreset;\n+\tslot->ops.freset = npu_freset;\n+\tslot->ops.pfreset = NULL;\n+\tslot->ops.creset = NULL;\n+\n+\treturn slot;\n+}\n+\n static int64_t npu_freeze_status(struct phb *phb,\n \t\t\t\t uint64_t pe_number __unused,\n \t\t\t\t uint8_t *freeze_state,\n@@ -1106,7 +1136,6 @@ static const struct phb_ops npu_ops = {\n \t.get_reserved_pe_number\t= NULL,\n \t.device_init\t\t= NULL,\n \t.phb_final_fixup\t= npu_phb_final_fixup,\n-\t.presence_detect\t= NULL,\n \t.ioda_reset\t\t= npu_ioda_reset,\n \t.papr_errinjct_reset\t= NULL,\n \t.pci_reinit\t\t= NULL,\n@@ -1121,14 +1150,6 @@ static const struct phb_ops npu_ops = {\n \t.get_msi_64\t\t= NULL,\n \t.set_pe\t\t\t= npu_set_pe,\n \t.set_peltv\t\t= NULL,\n-\t.link_state\t\t= npu_link_state,\n-\t.power_state\t\t= npu_power_state,\n-\t.slot_power_off\t\t= NULL,\n-\t.slot_power_on\t\t= NULL,\n-\t.hot_reset\t\t= npu_hreset,\n-\t.fundamental_reset\t= npu_freset,\n-\t.complete_reset\t\t= NULL,\n-\t.poll\t\t\t= NULL,\n \t.eeh_freeze_status\t= npu_freeze_status,\n \t.eeh_freeze_clear\t= NULL,\n \t.eeh_freeze_set\t\t= NULL,\n@@ -1749,6 +1770,7 @@ static void npu_create_phb(struct dt_node *dn)\n {\n \tconst struct dt_property *prop;\n \tstruct npu *p;\n+\tstruct pci_slot *slot;\n \tuint32_t links;\n \tvoid *pmem;\n \n@@ -1793,6 +1815,11 @@ static void npu_create_phb(struct dt_node *dn)\n \t/* Populate extra properties */\n \tnpu_add_phb_properties(p);\n \n+\t/* Create PHB slot */\n+\tslot = npu_slot_create(&p->phb);\n+\tif (!slot)\n+\t\tprlog(PR_ERR, \"NPU: Cannot create PHB slot\\n\");\n+\n \t/* Register PHB */\n \tpci_register_phb(&p->phb, OPAL_DYNAMIC_PHB_ID);\n \n", "prefixes": [ "v12", "17/23" ] }