Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/633505/?format=api
{ "id": 633505, "url": "http://patchwork.ozlabs.org/api/patches/633505/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/1465535032-26749-10-git-send-email-gwshan@linux.vnet.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1465535032-26749-10-git-send-email-gwshan@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2016-06-10T05:03:38", "name": "[v12,09/23] core/pci: Fix wrong reserved PE# in enumeration", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "e4dab97150ba01d68c8e0ed726f210b9514b89eb", "submitter": { "id": 63923, "url": "http://patchwork.ozlabs.org/api/people/63923/?format=api", "name": "Gavin Shan", "email": "gwshan@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/1465535032-26749-10-git-send-email-gwshan@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/633505/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/633505/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3rQqrD5qw6z9sD3\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Jun 2016 15:05:48 +1000 (AEST)", "from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3rQqrD4ZdlzDqP9\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Jun 2016 15:05:48 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3rQqqP3wCxzDqJ1\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:05:05 +1000 (AEST)", "from pps.filterd (m0098399.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id\n\tu5A53nXn067577\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 01:05:03 -0400", "from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 23e9m55txp-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 01:05:03 -0400", "from localhost\n\tby e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <skiboot@lists.ozlabs.org> from <gwshan@linux.vnet.ibm.com>;\n\tFri, 10 Jun 2016 15:05:00 +1000", "from d23dlp02.au.ibm.com (202.81.31.213)\n\tby e23smtp07.au.ibm.com (202.81.31.204) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tFri, 10 Jun 2016 15:04:59 +1000", "from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219])\n\tby d23dlp02.au.ibm.com (Postfix) with ESMTP id 8B8B02BB0064\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:04:48 +1000 (EST)", "from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138])\n\tby d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tu5A54h9v43646978\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:04:43 +1000", "from d23av02.au.ibm.com (localhost [127.0.0.1])\n\tby d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tu5A54bw2024812\n\tfor <skiboot@lists.ozlabs.org>; Fri, 10 Jun 2016 15:04:38 +1000", "from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14])\n\tby d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tu5A54bQi024687; Fri, 10 Jun 2016 15:04:37 +1000", "from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114])\n\tby ozlabs.au.ibm.com (Postfix) with ESMTP id 40EABA0199;\n\tFri, 10 Jun 2016 15:03:57 +1000 (AEST)", "from gwshan (shangw.ozlabs.ibm.com [10.61.2.199])\n\tby bran.ozlabs.ibm.com (Postfix) with ESMTP id 3F206E3B1A;\n\tFri, 10 Jun 2016 15:03:57 +1000 (AEST)", "by gwshan (Postfix, from userid 1000)\n\tid 24EF4942CA3; Fri, 10 Jun 2016 15:03:57 +1000 (AEST)" ], "X-IBM-Helo": "d23dlp02.au.ibm.com", "X-IBM-MailFrom": "gwshan@linux.vnet.ibm.com", "X-IBM-RcptTo": "skiboot@lists.ozlabs.org", "From": "Gavin Shan <gwshan@linux.vnet.ibm.com>", "To": "skiboot@lists.ozlabs.org", "Date": "Fri, 10 Jun 2016 15:03:38 +1000", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1465535032-26749-1-git-send-email-gwshan@linux.vnet.ibm.com>", "References": "<1465535032-26749-1-git-send-email-gwshan@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "16061005-0044-0000-0000-000001B2CACA", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "16061005-0045-0000-0000-000004E7256B", "Message-Id": "<1465535032-26749-10-git-send-email-gwshan@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2016-06-10_04:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000\n\tdefinitions=main-1606100058", "Subject": "[Skiboot] [PATCH v12 09/23] core/pci: Fix wrong reserved PE# in\n\tenumeration", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.22", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Cc": "alistair@popple.id.au", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "When scanning to non-existing PCI device, EEH (frozen) error is\nusually happening. We clear the unexpected frozen PE state after\nit. The reserved PE number is assumed to be 0 wrongly. So the\nfrozen state on the reserved PE number isn't cleared properly.\n\nThis introduces struct phb_ops::get_reserved_pe_number() to\nretrieve the reserved PE number from platforms. Then the EEH\nfrozen state checking and clearing are applied to the reserved\nPE number.\n\nSigned-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>\n---\n core/pci.c | 15 ++++++++++++---\n hw/npu.c | 1 +\n hw/p7ioc-phb.c | 6 ++++++\n hw/phb3.c | 6 ++++++\n include/pci.h | 1 +\n 5 files changed, 26 insertions(+), 3 deletions(-)", "diff": "diff --git a/core/pci.c b/core/pci.c\nindex 9b238d0..3d4f639 100644\n--- a/core/pci.c\n+++ b/core/pci.c\n@@ -274,11 +274,19 @@ static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *paren\n */\n static void pci_check_clear_freeze(struct phb *phb)\n {\n-\tint64_t rc;\n \tuint8_t freeze_state;\n \tuint16_t pci_error_type, sev;\n+\tint64_t pe_number, rc;\n+\n+\t/* Retrieve the reserved PE number */\n+\tpe_number = OPAL_PARAMETER;\n+\tif (phb->ops->get_reserved_pe_number)\n+\t\tpe_number = phb->ops->get_reserved_pe_number();\n+\tif (pe_number < 0)\n+\t\treturn;\n \n-\trc = phb->ops->eeh_freeze_status(phb, 0, &freeze_state,\n+\t/* Retrieve the frozen state */\n+\trc = phb->ops->eeh_freeze_status(phb, pe_number, &freeze_state,\n \t\t\t\t\t &pci_error_type, &sev, NULL);\n \tif (rc)\n \t\treturn;\n@@ -290,7 +298,8 @@ static void pci_check_clear_freeze(struct phb *phb)\n \t\tPCIERR(phb, 0, \"Fatal probe in %s error !\\n\", __func__);\n \t\treturn;\n \t}\n-\tphb->ops->eeh_freeze_clear(phb, 0, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);\n+\tphb->ops->eeh_freeze_clear(phb, pe_number,\n+\t\t\t\t OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);\n }\n \n /* pci_enable_bridge - Called before scanning a bridge\ndiff --git a/hw/npu.c b/hw/npu.c\nindex 79b232a..a8f9f06 100644\n--- a/hw/npu.c\n+++ b/hw/npu.c\n@@ -1103,6 +1103,7 @@ static const struct phb_ops npu_ops = {\n \t.cfg_write16\t\t= npu_dev_cfg_write16,\n \t.cfg_write32\t\t= npu_dev_cfg_write32,\n \t.choose_bus\t\t= NULL,\n+\t.get_reserved_pe_number\t= NULL,\n \t.device_init\t\t= NULL,\n \t.phb_final_fixup\t= npu_phb_final_fixup,\n \t.presence_detect\t= NULL,\ndiff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c\nindex bad7d0a..591c9ec 100644\n--- a/hw/p7ioc-phb.c\n+++ b/hw/p7ioc-phb.c\n@@ -2304,6 +2304,11 @@ static uint8_t p7ioc_choose_bus(struct phb *phb __unused,\n \treturn al;\n }\n \n+static int64_t p7ioc_get_reserved_pe_number(void)\n+{\n+\treturn 127;\n+}\n+\n /* p7ioc_phb_init_ioda_cache - Reset the IODA cache values\n */\n static void p7ioc_phb_init_ioda_cache(struct p7ioc_phb *p)\n@@ -2558,6 +2563,7 @@ static const struct phb_ops p7ioc_phb_ops = {\n \t.cfg_write16\t\t= p7ioc_pcicfg_write16,\n \t.cfg_write32\t\t= p7ioc_pcicfg_write32,\n \t.choose_bus\t\t= p7ioc_choose_bus,\n+\t.get_reserved_pe_number\t= p7ioc_get_reserved_pe_number,\n \t.device_init\t\t= p7ioc_device_init,\n \t.pci_reinit\t\t= p7ioc_pci_reinit,\n \t.eeh_freeze_status\t= p7ioc_eeh_freeze_status,\ndiff --git a/hw/phb3.c b/hw/phb3.c\nindex ab9d117..ab6922c 100644\n--- a/hw/phb3.c\n+++ b/hw/phb3.c\n@@ -295,6 +295,11 @@ static uint8_t phb3_choose_bus(struct phb *phb __unused,\n \treturn candidate;\n }\n \n+static int64_t phb3_get_reserved_pe_number(void)\n+{\n+\treturn PHB3_RESERVED_PE_NUM;\n+}\n+\n static void phb3_root_port_init(struct phb *phb, struct pci_device *dev,\n \t\t\t\tint ecap, int aercap)\n {\n@@ -3580,6 +3585,7 @@ static const struct phb_ops phb3_ops = {\n \t.cfg_write16\t\t= phb3_pcicfg_write16,\n \t.cfg_write32\t\t= phb3_pcicfg_write32,\n \t.choose_bus\t\t= phb3_choose_bus,\n+\t.get_reserved_pe_number\t= phb3_get_reserved_pe_number,\n \t.device_init\t\t= phb3_device_init,\n \t.presence_detect\t= phb3_presence_detect,\n \t.ioda_reset\t\t= phb3_ioda_reset,\ndiff --git a/include/pci.h b/include/pci.h\nindex aec4808..bd966ba 100644\n--- a/include/pci.h\n+++ b/include/pci.h\n@@ -254,6 +254,7 @@ struct phb_ops {\n \tuint8_t (*choose_bus)(struct phb *phb, struct pci_device *bridge,\n \t\t\t uint8_t candidate, uint8_t *max_bus,\n \t\t\t bool *use_max);\n+\tint64_t (*get_reserved_pe_number)(void);\n \n \t/*\n \t * Device init method is called after a device has been detected\n", "prefixes": [ "v12", "09/23" ] }