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GET /api/patches/627662/?format=api
{ "id": 627662, "url": "http://patchwork.ozlabs.org/api/patches/627662/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1464432715-10996-3-git-send-email-eddy.petrisor@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1464432715-10996-3-git-send-email-eddy.petrisor@gmail.com>", "list_archive_url": null, "date": "2016-05-28T10:51:55", "name": "[U-Boot,v4,2/2] armv8: s32v234: Introduce basic support for s32v234evb", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "256aad41d4ebf171cb3ec957ab4ae5d997dbe424", "submitter": { "id": 68207, "url": "http://patchwork.ozlabs.org/api/people/68207/?format=api", "name": "Eddy Petrișor", "email": "eddy.petrisor@gmail.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1464432715-10996-3-git-send-email-eddy.petrisor@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/627662/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/627662/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 3rJ9zn6PX0z9t5T\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 30 May 2016 19:19:17 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 9FDB5A763D;\n\tMon, 30 May 2016 11:18:05 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id BSRU3chi85et; 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a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:in-reply-to:references:mime-version:content-transfer-encoding;\n\tbh=WP/kQy3WdGhyqNrei1mYpTlQ92E4gekyv0tqJyrOCBA=;\n\tb=gimTPnVauHqh1FrtZ7e/nPPbFrHLrmKnHYM/agO0i5nZ3CEUMFGRAYB3t7Q5G58xy1\n\tDnLGci5VeEVuDDnTczPSMYQRumWgbK1N8sYKMDlbMER2NxLvnVy3QDFFdNWqLqV078bC\n\t1giVojkQ78gTB8J8FbDtFati86Rn5LlyyicWC7vbhQE3SCb2vJ6hl5qgdLx6TF7mF1Fh\n\taDsckEJZ0ObRJIA+vMay44eco1ytlkBffqhffUaMObtP+LCECHExFkIlWOG0rOLYU1xr\n\t8MMDwPBU1ywLGccxFDCB797C2nfoAqfMb7QQF3tCFfme+oO7EnZ7JD+gNPw4nbKpRYOQ\n\ta0ZA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:in-reply-to:references:mime-version\n\t:content-transfer-encoding;\n\tbh=WP/kQy3WdGhyqNrei1mYpTlQ92E4gekyv0tqJyrOCBA=;\n\tb=EWCXVwHTT0lCSFb5CGpcqGBEq4/Wo3xwClDu7jeEcDlgH+OUfbDiHfixnw6d8C7n2O\n\tCTXTgEQ+YwsTfQrFG1s85Gx4eN3l0KpSjNPUFN84suEezoe9xC91LLHeg1aRcNYisa5n\n\t8HbekaApt7nuQNaqyUHjOuXU+LEtuTPXdcj4XCcW0vBr6u8bJvCRn2o8bKzkmBgEujuw\n\tzBMbg9obh9LEYZbLCNIL94v2/1sH2izUIjmtjNCOmbuP+poRFJa4nE1lqLrp7jYd1qCP\n\t+WgK8aX8UH781BH4yZvV6bw8JA7CRH0J0ROgXW7FJdlYg0uNxZRDT8pR1+lWT4FtzXnh\n\teiAw==", "X-Gm-Message-State": "ALyK8tJ6SJJkmkKR25ugwcmXJUE3sBiCd8LTSn1AI/HxObtTjtovJ4B2SdrKMtgxoTIeZg==", "X-Received": "by 10.28.29.7 with SMTP id d7mr2798700wmd.27.1464432756012;\n\tSat, 28 May 2016 03:52:36 -0700 (PDT)", "From": "=?UTF-8?q?Eddy=20Petri=C8=99or?= <eddy.petrisor@gmail.com>", "To": "U-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Sat, 28 May 2016 13:51:55 +0300", "Message-Id": "<1464432715-10996-3-git-send-email-eddy.petrisor@gmail.com>", "X-Mailer": "git-send-email 2.5.0", "In-Reply-To": [ "<1464432715-10996-1-git-send-email-eddy.petrisor@gmail.com>", "<1459642206-20101-1-git-send-email-eddy.petrisor@gmail.com>" ], "References": [ "<1464432715-10996-1-git-send-email-eddy.petrisor@gmail.com>", "<1459642206-20101-1-git-send-email-eddy.petrisor@gmail.com>\n\t<1459642206-20101-2-git-send-email-eddy.petrisor@gmail.com>\n\t<1461794874-6105-3-git-send-email-eddy.petrisor@nxp.com>\n\t<1464429375-6191-3-git-send-email-eddy.petrisor@gmail.com>" ], "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>,\n\t=?UTF-8?q?Eddy=20Petri=C8=99or?= <eddy.petrisor@nxp.com>,\n\t=?UTF-8?q?Eddy=20Petri=C8=99or?= <eddy.petrisor@gmail.com>", "Subject": "[U-Boot] [PATCH v4 2/2] armv8: s32v234: Introduce basic support for\n\ts32v234evb", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add initial support for NXP's S32V234 SoC and S32V234EVB board.\n\nThe S32V230 family is designed to support computation-intensive applications\nfor image processing. The S32V234, as part of the S32V230 family, is a\nhigh-performance automotive processor designed to support safe\ncomputation-intensive applications in the area of vision and sensor fusion.\n\nCode originally writen by:\nOriginal-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>\nOriginal-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>\nOriginal-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>\n\nSigned-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>\n---\n\nNotes:\n Changes in v2:\n - Added support for device model. Compatibility with non-DM code is kept\n for easier synchronization with the code on the vendor branch where the\n conversion to DM is not done for all boards.\n - remove TODO-s\n - remove '#if 0'-ed code\n - switched to SPDX headers\n - removed uselss guard around 'DECLARE_GLOBAL_DATA_PTR;'\n - replaced 'CONFIG_SYS_FSL' with 'S32V234' in defines for MMU bases and sizes\n - reset_cpu now says it's not implemented\n - moved OF_LIBFDT and BOOTZ config options to Kconfig\n \n Changes in v3:\n - Switch s32v234evb to config_distro_defaults.h and config_distro_bootcmd.h\n \n Changes in v4:\n - None\n\n arch/arm/Kconfig | 5 +\n arch/arm/cpu/armv8/Makefile | 1 +\n arch/arm/cpu/armv8/s32v234/Makefile | 8 +\n arch/arm/cpu/armv8/s32v234/cpu.c | 97 +++++++\n arch/arm/cpu/armv8/s32v234/cpu.h | 8 +\n arch/arm/cpu/armv8/s32v234/generic.c | 350 ++++++++++++++++++++++++\n arch/arm/include/asm/arch-s32v234/clock.h | 34 +++\n arch/arm/include/asm/arch-s32v234/ddr.h | 157 +++++++++++\n arch/arm/include/asm/arch-s32v234/imx-regs.h | 329 ++++++++++++++++++++++\n arch/arm/include/asm/arch-s32v234/lpddr2.h | 75 +++++\n arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h | 254 +++++++++++++++++\n arch/arm/include/asm/arch-s32v234/mc_me_regs.h | 199 ++++++++++++++\n arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h | 31 +++\n arch/arm/include/asm/arch-s32v234/mmdc.h | 89 ++++++\n arch/arm/include/asm/arch-s32v234/siul.h | 150 ++++++++++\n board/freescale/s32v234evb/Kconfig | 23 ++\n board/freescale/s32v234evb/MAINTAINERS | 8 +\n board/freescale/s32v234evb/Makefile | 11 +\n board/freescale/s32v234evb/clock.c | 344 +++++++++++++++++++++++\n board/freescale/s32v234evb/lpddr2.c | 137 ++++++++++\n board/freescale/s32v234evb/s32v234evb.c | 183 +++++++++++++\n board/freescale/s32v234evb/s32v234evb.cfg | 29 ++\n configs/s32v234evb_defconfig | 6 +\n drivers/mmc/fsl_esdhc.c | 10 +-\n include/configs/s32v234evb.h | 260 ++++++++++++++++++\n 25 files changed, 2793 insertions(+), 5 deletions(-)\n create mode 100644 arch/arm/cpu/armv8/s32v234/Makefile\n create mode 100644 arch/arm/cpu/armv8/s32v234/cpu.c\n create mode 100644 arch/arm/cpu/armv8/s32v234/cpu.h\n create mode 100644 arch/arm/cpu/armv8/s32v234/generic.c\n create mode 100644 arch/arm/include/asm/arch-s32v234/clock.h\n create mode 100644 arch/arm/include/asm/arch-s32v234/ddr.h\n create mode 100644 arch/arm/include/asm/arch-s32v234/imx-regs.h\n create mode 100644 arch/arm/include/asm/arch-s32v234/lpddr2.h\n create mode 100644 arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h\n create mode 100644 arch/arm/include/asm/arch-s32v234/mc_me_regs.h\n create mode 100644 arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h\n create mode 100644 arch/arm/include/asm/arch-s32v234/mmdc.h\n create mode 100644 arch/arm/include/asm/arch-s32v234/siul.h\n create mode 100644 board/freescale/s32v234evb/Kconfig\n create mode 100644 board/freescale/s32v234evb/MAINTAINERS\n create mode 100644 board/freescale/s32v234evb/Makefile\n create mode 100644 board/freescale/s32v234evb/clock.c\n create mode 100644 board/freescale/s32v234evb/lpddr2.c\n create mode 100644 board/freescale/s32v234evb/s32v234evb.c\n create mode 100644 board/freescale/s32v234evb/s32v234evb.cfg\n create mode 100644 configs/s32v234evb_defconfig\n create mode 100644 include/configs/s32v234evb.h", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex 5fd20b9..d424922 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -511,6 +511,10 @@ config RMOBILE\n \tbool \"Renesas ARM SoCs\"\n \tselect CPU_V7\n \n+config TARGET_S32V234EVB\n+\tbool \"Support s32v234evb\"\n+\tselect ARM64\n+\n config ARCH_SNAPDRAGON\n \tbool \"Qualcomm Snapdragon SoCs\"\n \tselect ARM64\n@@ -853,6 +857,7 @@ source \"board/freescale/mx53ard/Kconfig\"\n source \"board/freescale/mx53evk/Kconfig\"\n source \"board/freescale/mx53loco/Kconfig\"\n source \"board/freescale/mx53smd/Kconfig\"\n+source \"board/freescale/s32v234evb/Kconfig\"\n source \"board/freescale/vf610twr/Kconfig\"\n source \"board/gumstix/pepper/Kconfig\"\n source \"board/h2200/Kconfig\"\ndiff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile\nindex 1c85aa9..bf8644c 100644\n--- a/arch/arm/cpu/armv8/Makefile\n+++ b/arch/arm/cpu/armv8/Makefile\n@@ -17,5 +17,6 @@ obj-y\t+= transition.o\n obj-y\t+= fwcall.o\n \n obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/\n+obj-$(CONFIG_S32V234) += s32v234/\n obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/\n obj-$(CONFIG_TARGET_HIKEY) += hisilicon/\ndiff --git a/arch/arm/cpu/armv8/s32v234/Makefile b/arch/arm/cpu/armv8/s32v234/Makefile\nnew file mode 100644\nindex 0000000..49774f6\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/s32v234/Makefile\n@@ -0,0 +1,8 @@\n+#\n+# (C) Copyright 2013-2016, Freescale Semiconductor, Inc.\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y += generic.o\n+obj-y += cpu.o\ndiff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c\nnew file mode 100644\nindex 0000000..dac12a2\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/s32v234/cpu.c\n@@ -0,0 +1,97 @@\n+/*\n+ * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <asm/system.h>\n+#include <asm/armv8/mmu.h>\n+#include <asm/io.h>\n+#include <asm/arch/mc_me_regs.h>\n+#include \"cpu.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+u32 cpu_mask(void)\n+{\n+\treturn readl(MC_ME_CS);\n+}\n+\n+#ifndef CONFIG_SYS_DCACHE_OFF\n+\n+#define S32V234_IRAM_BASE 0x3e800000UL\n+#define S32V234_IRAM_SIZE 0x800000UL\n+#define S32V234_DRAM_BASE1 0x80000000UL\n+#define S32V234_DRAM_SIZE1 0x40000000UL\n+#define S32V234_DRAM_BASE2 0xC0000000UL\n+#define S32V234_DRAM_SIZE2 0x20000000UL\n+#define S32V234_PERIPH_BASE 0x40000000UL\n+#define S32V234_PERIPH_SIZE 0x40000000UL\n+\n+static struct mm_region s32v234_mem_map[] = {\n+\t{\n+\t\t.base = S32V234_IRAM_BASE,\n+\t\t.size = S32V234_IRAM_SIZE,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t PTE_BLOCK_OUTER_SHARE\n+\t}, {\n+\t\t.base = S32V234_DRAM_BASE1,\n+\t\t.size = S32V234_DRAM_SIZE1,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t PTE_BLOCK_OUTER_SHARE\n+\t}, {\n+\t\t.base = S32V234_PERIPH_BASE,\n+\t\t.size = S32V234_PERIPH_SIZE,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t PTE_BLOCK_NON_SHARE\n+\t\t\t /* TODO: Do we need these? */\n+\t\t\t /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */\n+\t}, {\n+\t\t.base = S32V234_DRAM_BASE2,\n+\t\t.size = S32V234_DRAM_SIZE2,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |\n+\t\t\t PTE_BLOCK_OUTER_SHARE\n+\t}, {\n+\t\t/* List terminator */\n+\t\t0,\n+\t}\n+};\n+\n+struct mm_region *mem_map = s32v234_mem_map;\n+\n+#endif\n+\n+/*\n+ * Return the number of cores on this SOC.\n+ */\n+int cpu_numcores(void)\n+{\n+\tint numcores;\n+\tu32 mask;\n+\n+\tmask = cpu_mask();\n+\tnumcores = hweight32(cpu_mask());\n+\n+\t/* Verify if M4 is deactivated */\n+\tif (mask & 0x1)\n+\t\tnumcores--;\n+\n+\treturn numcores;\n+}\n+\n+#if defined(CONFIG_ARCH_EARLY_INIT_R)\n+int arch_early_init_r(void)\n+{\n+\tint rv;\n+\tasm volatile (\"dsb sy\");\n+\trv = fsl_s32v234_wake_seconday_cores();\n+\n+\tif (rv)\n+\t\tprintf(\"Did not wake secondary cores\\n\");\n+\n+\tasm volatile (\"sev\");\n+\treturn 0;\n+}\n+#endif /* CONFIG_ARCH_EARLY_INIT_R */\ndiff --git a/arch/arm/cpu/armv8/s32v234/cpu.h b/arch/arm/cpu/armv8/s32v234/cpu.h\nnew file mode 100644\nindex 0000000..402ac29\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/s32v234/cpu.h\n@@ -0,0 +1,8 @@\n+/*\n+ * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+u32 cpu_mask(void);\n+int cpu_numcores(void);\ndiff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c\nnew file mode 100644\nindex 0000000..7bb894e\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/s32v234/generic.c\n@@ -0,0 +1,350 @@\n+/*\n+ * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/mc_cgm_regs.h>\n+#include <asm/arch/mc_me_regs.h>\n+#include <asm/arch/mc_rgm_regs.h>\n+#include <netdev.h>\n+#include <div64.h>\n+#include <errno.h>\n+\n+u32 get_cpu_rev(void)\n+{\n+\tstruct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;\n+\tu32 cpu = readl(&mscmir->cpxtype);\n+\n+\treturn cpu;\n+}\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,\n+\t\t\t u32 pllfd, u32 selected_output)\n+{\n+\tu32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;\n+\tu32 plldv_rfdphi_div = 0, fout = 0;\n+\tu32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;\n+\n+\tif (selected_output > DFS_MAXNUMBER) {\n+\t\treturn -1;\n+\t}\n+\n+\tplldv_prediv =\n+\t (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;\n+\tplldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);\n+\n+\tpllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);\n+\n+\tplldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;\n+\n+\t/* The formula for VCO is from TR manual, rev. D */\n+\tvco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);\n+\n+\tif (selected_output != 0) {\n+\t\t/* Determine the RFDPHI for PHI1 */\n+\t\tplldv_rfdphi_div =\n+\t\t (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>\n+\t\t PLLDIG_PLLDV_RFDPHI1_OFFSET;\n+\t\tplldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;\n+\t\tif (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {\n+\t\t\tdfs_portn =\n+\t\t\t readl(DFS_DVPORTn(pll, selected_output - 1));\n+\t\t\tdfs_mfi =\n+\t\t\t (dfs_portn & DFS_DVPORTn_MFI_MASK) >>\n+\t\t\t DFS_DVPORTn_MFI_OFFSET;\n+\t\t\tdfs_mfn =\n+\t\t\t (dfs_portn & DFS_DVPORTn_MFI_MASK) >>\n+\t\t\t DFS_DVPORTn_MFI_OFFSET;\n+\t\t\tfout = vco / (dfs_mfi + (dfs_mfn / 256));\n+\t\t} else {\n+\t\t\tfout = vco / plldv_rfdphi_div;\n+\t\t}\n+\n+\t} else {\n+\t\t/* Determine the RFDPHI for PHI0 */\n+\t\tplldv_rfdphi_div =\n+\t\t (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>\n+\t\t PLLDIG_PLLDV_RFDPHI_OFFSET;\n+\t\tfout = vco / plldv_rfdphi_div;\n+\t}\n+\n+\treturn fout;\n+\n+}\n+\n+/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */\n+static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,\n+\t\t\t u32 selected_output)\n+{\n+\tu32 plldv, pllfd;\n+\n+\tplldv = readl(PLLDIG_PLLDV(pll));\n+\tpllfd = readl(PLLDIG_PLLFD(pll));\n+\n+\treturn get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);\n+}\n+\n+static u32 get_mcu_main_clk(void)\n+{\n+\tu32 coreclk_div;\n+\tu32 sysclk_sel;\n+\tu32 freq = 0;\n+\n+\tsysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;\n+\tsysclk_sel >>= MC_CGM_SC_SEL_OFFSET;\n+\n+\tcoreclk_div =\n+\t readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;\n+\tcoreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;\n+\tcoreclk_div += 1;\n+\n+\tswitch (sysclk_sel) {\n+\tcase MC_CGM_SC_SEL_FIRC:\n+\t\tfreq = FIRC_CLK_FREQ;\n+\t\tbreak;\n+\tcase MC_CGM_SC_SEL_XOSC:\n+\t\tfreq = XOSC_CLK_FREQ;\n+\t\tbreak;\n+\tcase MC_CGM_SC_SEL_ARMPLL:\n+\t\t/* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */\n+\t\tfreq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);\n+\t\tbreak;\n+\tcase MC_CGM_SC_SEL_CLKDISABLE:\n+\t\tprintf(\"Sysclk is disabled\\n\");\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"unsupported system clock select\\n\");\n+\t}\n+\n+\treturn freq / coreclk_div;\n+}\n+\n+static u32 get_sys_clk(u32 number)\n+{\n+\tu32 sysclk_div, sysclk_div_number;\n+\tu32 sysclk_sel;\n+\tu32 freq = 0;\n+\n+\tswitch (number) {\n+\tcase 3:\n+\t\tsysclk_div_number = 0;\n+\t\tbreak;\n+\tcase 6:\n+\t\tsysclk_div_number = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"unsupported system clock \\n\");\n+\t\treturn -1;\n+\t}\n+\tsysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;\n+\tsysclk_sel >>= MC_CGM_SC_SEL_OFFSET;\n+\n+\tsysclk_div =\n+\t readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &\n+\t MC_CGM_SC_DCn_PREDIV_MASK;\n+\tsysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;\n+\tsysclk_div += 1;\n+\n+\tswitch (sysclk_sel) {\n+\tcase MC_CGM_SC_SEL_FIRC:\n+\t\tfreq = FIRC_CLK_FREQ;\n+\t\tbreak;\n+\tcase MC_CGM_SC_SEL_XOSC:\n+\t\tfreq = XOSC_CLK_FREQ;\n+\t\tbreak;\n+\tcase MC_CGM_SC_SEL_ARMPLL:\n+\t\t/* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */\n+\t\tfreq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);\n+\t\tbreak;\n+\tcase MC_CGM_SC_SEL_CLKDISABLE:\n+\t\tprintf(\"Sysclk is disabled\\n\");\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"unsupported system clock select\\n\");\n+\t}\n+\n+\treturn freq / sysclk_div;\n+}\n+\n+static u32 get_peripherals_clk(void)\n+{\n+\tu32 aux5clk_div;\n+\tu32 freq = 0;\n+\n+\taux5clk_div =\n+\t readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &\n+\t MC_CGM_ACn_DCm_PREDIV_MASK;\n+\taux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;\n+\taux5clk_div += 1;\n+\n+\tfreq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);\n+\n+\treturn freq / aux5clk_div;\n+\n+}\n+\n+static u32 get_uart_clk(void)\n+{\n+\tu32 auxclk3_div, auxclk3_sel, freq = 0;\n+\n+\tauxclk3_sel =\n+\t readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;\n+\tauxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;\n+\n+\tauxclk3_div =\n+\t readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &\n+\t MC_CGM_ACn_DCm_PREDIV_MASK;\n+\tauxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;\n+\tauxclk3_div += 1;\n+\n+\tswitch (auxclk3_sel) {\n+\tcase MC_CGM_ACn_SEL_FIRC:\n+\t\tfreq = FIRC_CLK_FREQ;\n+\t\tbreak;\n+\tcase MC_CGM_ACn_SEL_XOSC:\n+\t\tfreq = XOSC_CLK_FREQ;\n+\t\tbreak;\n+\tcase MC_CGM_ACn_SEL_PERPLLDIVX:\n+\t\tfreq = get_peripherals_clk() / 3;\n+\t\tbreak;\n+\tcase MC_CGM_ACn_SEL_SYSCLK:\n+\t\tfreq = get_sys_clk(6);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"unsupported system clock select\\n\");\n+\t}\n+\n+\treturn freq / auxclk3_div;\n+}\n+\n+static u32 get_fec_clk(void)\n+{\n+\tu32 aux2clk_div;\n+\tu32 freq = 0;\n+\n+\taux2clk_div =\n+\t readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &\n+\t MC_CGM_ACn_DCm_PREDIV_MASK;\n+\taux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;\n+\taux2clk_div += 1;\n+\n+\tfreq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);\n+\n+\treturn freq / aux2clk_div;\n+}\n+\n+static u32 get_usdhc_clk(void)\n+{\n+\tu32 aux15clk_div;\n+\tu32 freq = 0;\n+\n+\taux15clk_div =\n+\t readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &\n+\t MC_CGM_ACn_DCm_PREDIV_MASK;\n+\taux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;\n+\taux15clk_div += 1;\n+\n+\tfreq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);\n+\n+\treturn freq / aux15clk_div;\n+}\n+\n+static u32 get_i2c_clk(void)\n+{\n+\treturn get_peripherals_clk();\n+}\n+\n+/* return clocks in Hz */\n+unsigned int mxc_get_clock(enum mxc_clock clk)\n+{\n+\tswitch (clk) {\n+\tcase MXC_ARM_CLK:\n+\t\treturn get_mcu_main_clk();\n+\tcase MXC_PERIPHERALS_CLK:\n+\t\treturn get_peripherals_clk();\n+\tcase MXC_UART_CLK:\n+\t\treturn get_uart_clk();\n+\tcase MXC_FEC_CLK:\n+\t\treturn get_fec_clk();\n+\tcase MXC_I2C_CLK:\n+\t\treturn get_i2c_clk();\n+\tcase MXC_USDHC_CLK:\n+\t\treturn get_usdhc_clk();\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\tprintf(\"Error: Unsupported function to read the frequency! \\\n+\t\t\tPlease define it correctly!\");\n+\treturn -1;\n+}\n+\n+/* Not yet implemented - int soc_clk_dump(); */\n+\n+#if defined(CONFIG_DISPLAY_CPUINFO)\n+static char *get_reset_cause(void)\n+{\n+\tu32 cause = readl(MC_RGM_BASE_ADDR + 0x300);\n+\n+\tswitch (cause) {\n+\tcase F_SWT4:\n+\t\treturn \"WDOG\";\n+\tcase F_JTAG:\n+\t\treturn \"JTAG\";\n+\tcase F_FCCU_SOFT:\n+\t\treturn \"FCCU soft reaction\";\n+\tcase F_FCCU_HARD:\n+\t\treturn \"FCCU hard reaction\";\n+\tcase F_SOFT_FUNC:\n+\t\treturn \"Software Functional reset\";\n+\tcase F_ST_DONE:\n+\t\treturn \"Self Test done reset\";\n+\tcase F_EXT_RST:\n+\t\treturn \"External reset\";\n+\tdefault:\n+\t\treturn \"unknown reset\";\n+\t}\n+\n+}\n+\n+#define SRC_SCR_SW_RST\t\t\t\t\t(1<<12)\n+\n+void reset_cpu(ulong addr)\n+{\n+\tprintf(\"Feature not supported.\\n\");\n+};\n+\n+int print_cpuinfo(void)\n+{\n+\tprintf(\"CPU: Freescale Treerunner S32V234 at %d MHz\\n\",\n+\t mxc_get_clock(MXC_ARM_CLK) / 1000000);\n+\tprintf(\"Reset cause: %s\\n\", get_reset_cause());\n+\n+\treturn 0;\n+}\n+#endif\n+\n+int cpu_eth_init(bd_t * bis)\n+{\n+\tint rc = -ENODEV;\n+\n+#if defined(CONFIG_FEC_MXC)\n+\trc = fecmxc_initialize(bis);\n+#endif\n+\n+\treturn rc;\n+}\n+\n+int get_clocks(void)\n+{\n+#ifdef CONFIG_FSL_ESDHC\n+\tgd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);\n+#endif\n+\treturn 0;\n+}\ndiff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h\nnew file mode 100644\nindex 0000000..df92fb2\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/clock.h\n@@ -0,0 +1,34 @@\n+/*\n+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ASM_ARCH_CLOCK_H\n+#define __ASM_ARCH_CLOCK_H\n+\n+#include <common.h>\n+\n+enum mxc_clock {\n+\tMXC_ARM_CLK = 0,\n+\tMXC_BUS_CLK,\n+\tMXC_PERIPHERALS_CLK,\n+\tMXC_UART_CLK,\n+\tMXC_USDHC_CLK,\n+\tMXC_FEC_CLK,\n+\tMXC_I2C_CLK,\n+};\n+enum pll_type {\n+\tARM_PLL = 0,\n+\tPERIPH_PLL,\n+\tENET_PLL,\n+\tDDR_PLL,\n+\tVIDEO_PLL,\n+};\n+\n+unsigned int mxc_get_clock(enum mxc_clock clk);\n+void clock_init(void);\n+\n+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)\n+\n+#endif /* __ASM_ARCH_CLOCK_H */\ndiff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h\nnew file mode 100644\nindex 0000000..10a9a79\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/ddr.h\n@@ -0,0 +1,157 @@\n+/*\n+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__\n+#define __ARCH_ARM_MACH_S32V234_DDR_H__\n+\n+#define DDR0\t0\n+#define DDR1\t1\n+\n+/* DDR offset in MSCR register */\n+#define _DDR0_RESET\t168\n+#define _DDR0_CLK0\t169\n+#define _DDR0_CAS\t170\n+#define _DDR0_RAS\t171\n+#define _DDR0_WE_B\t172\n+#define _DDR0_CKE0\t173\n+#define _DDR0_CKE1\t174\n+#define _DDR0_CS_B0\t175\n+#define _DDR0_CS_B1\t176\n+#define _DDR0_BA0\t177\n+#define _DDR0_BA1\t178\n+#define _DDR0_BA2\t179\n+#define _DDR0_A0\t180\n+#define _DDR0_A1\t181\n+#define _DDR0_A2\t182\n+#define _DDR0_A3\t183\n+#define _DDR0_A4\t184\n+#define _DDR0_A5\t185\n+#define _DDR0_A6\t186\n+#define _DDR0_A7\t187\n+#define _DDR0_A8\t188\n+#define _DDR0_A9\t189\n+#define _DDR0_A10\t190\n+#define _DDR0_A11\t191\n+#define _DDR0_A12\t192\n+#define _DDR0_A13\t193\n+#define _DDR0_A14\t194\n+#define _DDR0_A15\t195\n+#define _DDR0_DM0\t196\n+#define _DDR0_DM1\t197\n+#define _DDR0_DM2\t198\n+#define _DDR0_DM3\t199\n+#define _DDR0_DQS0\t200\n+#define _DDR0_DQS1\t201\n+#define _DDR0_DQS2\t202\n+#define _DDR0_DQS3\t203\n+#define _DDR0_D0\t204\n+#define _DDR0_D1\t205\n+#define _DDR0_D2\t206\n+#define _DDR0_D3\t207\n+#define _DDR0_D4\t208\n+#define _DDR0_D5\t209\n+#define _DDR0_D6\t210\n+#define _DDR0_D7\t211\n+#define _DDR0_D8\t212\n+#define _DDR0_D9\t213\n+#define _DDR0_D10\t214\n+#define _DDR0_D11\t215\n+#define _DDR0_D12\t216\n+#define _DDR0_D13\t217\n+#define _DDR0_D14\t218\n+#define _DDR0_D15\t219\n+#define _DDR0_D16\t220\n+#define _DDR0_D17\t221\n+#define _DDR0_D18\t222\n+#define _DDR0_D19\t223\n+#define _DDR0_D20\t224\n+#define _DDR0_D21\t225\n+#define _DDR0_D22\t226\n+#define _DDR0_D23\t227\n+#define _DDR0_D24\t228\n+#define _DDR0_D25\t229\n+#define _DDR0_D26\t230\n+#define _DDR0_D27\t231\n+#define _DDR0_D28\t232\n+#define _DDR0_D29\t233\n+#define _DDR0_D30\t234\n+#define _DDR0_D31\t235\n+#define _DDR0_ODT0\t236\n+#define _DDR0_ODT1\t237\n+#define _DDR0_ZQ\t238\n+#define _DDR1_RESET\t239\n+#define _DDR1_CLK0\t240\n+#define _DDR1_CAS\t241\n+#define _DDR1_RAS\t242\n+#define _DDR1_WE_B\t243\n+#define _DDR1_CKE0\t244\n+#define _DDR1_CKE1\t245\n+#define _DDR1_CS_B0\t246\n+#define _DDR1_CS_B1\t247\n+#define _DDR1_BA0\t248\n+#define _DDR1_BA1\t249\n+#define _DDR1_BA2\t250\n+#define _DDR1_A0\t251\n+#define _DDR1_A1\t252\n+#define _DDR1_A2\t253\n+#define _DDR1_A3\t254\n+#define _DDR1_A4\t255\n+#define _DDR1_A5\t256\n+#define _DDR1_A6\t257\n+#define _DDR1_A7\t258\n+#define _DDR1_A8\t259\n+#define _DDR1_A9\t260\n+#define _DDR1_A10\t261\n+#define _DDR1_A11\t262\n+#define _DDR1_A12\t263\n+#define _DDR1_A13\t264\n+#define _DDR1_A14\t265\n+#define _DDR1_A15\t266\n+#define _DDR1_DM0\t267\n+#define _DDR1_DM1\t268\n+#define _DDR1_DM2\t269\n+#define _DDR1_DM3\t270\n+#define _DDR1_DQS0\t271\n+#define _DDR1_DQS1\t272\n+#define _DDR1_DQS2\t273\n+#define _DDR1_DQS3\t274\n+#define _DDR1_D0\t275\n+#define _DDR1_D1\t276\n+#define _DDR1_D2\t277\n+#define _DDR1_D3\t278\n+#define _DDR1_D4\t279\n+#define _DDR1_D5\t280\n+#define _DDR1_D6\t281\n+#define _DDR1_D7\t282\n+#define _DDR1_D8\t283\n+#define _DDR1_D9\t284\n+#define _DDR1_D10\t285\n+#define _DDR1_D11\t286\n+#define _DDR1_D12\t287\n+#define _DDR1_D13\t288\n+#define _DDR1_D14\t289\n+#define _DDR1_D15\t290\n+#define _DDR1_D16\t291\n+#define _DDR1_D17\t292\n+#define _DDR1_D18\t293\n+#define _DDR1_D19\t294\n+#define _DDR1_D20\t295\n+#define _DDR1_D21\t296\n+#define _DDR1_D22\t297\n+#define _DDR1_D23\t298\n+#define _DDR1_D24\t299\n+#define _DDR1_D25\t300\n+#define _DDR1_D26\t301\n+#define _DDR1_D27\t302\n+#define _DDR1_D28\t303\n+#define _DDR1_D29\t304\n+#define _DDR1_D30\t305\n+#define _DDR1_D31\t306\n+#define _DDR1_ODT0\t307\n+#define _DDR1_ODT1\t308\n+#define _DDR1_ZQ\t309\n+\n+#endif\ndiff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h\nnew file mode 100644\nindex 0000000..a42f6cc\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/imx-regs.h\n@@ -0,0 +1,329 @@\n+/*\n+ * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ASM_ARCH_IMX_REGS_H__\n+#define __ASM_ARCH_IMX_REGS_H__\n+\n+#define ARCH_MXC\n+\n+#define IRAM_BASE_ADDR 0x3E800000\t/* internal ram */\n+#define IRAM_SIZE 0x00400000\t/* 4MB */\n+\n+#define AIPS0_BASE_ADDR (0x40000000UL)\n+#define AIPS1_BASE_ADDR (0x40080000UL)\n+\n+/* AIPS 0 */\n+#define AXBS_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00000000)\n+#define CSE3_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00001000)\n+#define EDMA_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00002000)\n+#define XRDC_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00004000)\n+#define SWT0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0000A000)\n+#define SWT1_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0000B000)\n+#define STM0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0000D000)\n+#define NIC301_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00010000)\n+#define GC3000_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00020000)\n+#define DEC200_DECODER_BASE_ADDR\t\t(AIPS0_BASE_ADDR + 0x00026000)\n+#define DEC200_ENCODER_BASE_ADDR\t\t(AIPS0_BASE_ADDR + 0x00027000)\n+#define TWOD_ACE_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00028000)\n+#define MIPI_CSI0_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00030000)\n+#define DMAMUX0_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00031000)\n+#define ENET_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00032000)\n+#define FLEXRAY_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00034000)\n+#define MMDC0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00036000)\n+#define MEW0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00037000)\n+#define MONITOR_DDR0_BASE_ADDR\t\t\t(AIPS0_BASE_ADDR + 0x00038000)\n+#define MONITOR_CCI0_BASE_ADDR\t\t\t(AIPS0_BASE_ADDR + 0x00039000)\n+#define PIT0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0003A000)\n+#define MC_CGM0_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x0003C000)\n+#define MC_CGM1_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x0003F000)\n+#define MC_CGM2_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00042000)\n+#define MC_CGM3_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00045000)\n+#define MC_RGM_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00048000)\n+#define MC_ME_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0004A000)\n+#define MC_PCU_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x0004B000)\n+#define ADC0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0004D000)\n+#define FLEXTIMER_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x0004F000)\n+#define I2C0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00051000)\n+#define LINFLEXD0_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00053000)\n+#define FLEXCAN0_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x00055000)\n+#define SPI0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00057000)\n+#define SPI2_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00059000)\n+#define CRC0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0005B000)\n+#define USDHC_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0005D000)\n+#define OCOTP_CONTROLLER_BASE_ADDR\t\t(AIPS0_BASE_ADDR + 0x0005F000)\n+#define WKPU_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00063000)\n+#define VIU0_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00064000)\n+#define HPSMI_SRAM_CONTROLLER_BASE_ADDR\t(AIPS0_BASE_ADDR + 0x00068000)\n+#define SIUL2_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x0006C000)\n+#define SIPI_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00074000)\n+#define LFAST_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00078000)\n+#define SSE_BASE_ADDR\t\t\t\t\t(AIPS0_BASE_ADDR + 0x00079000)\n+#define SRC_SOC_BASE_ADDR\t\t\t\t(AIPS0_BASE_ADDR + 0x0007C000)\n+\n+/* AIPS 1 */\n+#define ERM_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000000000)\n+#define MSCM_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000001000)\n+#define SEMA42_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X000002000)\n+#define INTC_MON_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X000003000)\n+#define SWT2_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000004000)\n+#define SWT3_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000005000)\n+#define SWT4_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000006000)\n+#define STM1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000007000)\n+#define EIM_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000008000)\n+#define APB_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000009000)\n+#define XBIC_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000012000)\n+#define MIPI_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000020000)\n+#define DMAMUX1_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X000021000)\n+#define MMDC1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000022000)\n+#define MEW1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000023000)\n+#define DDR1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000024000)\n+#define CCI1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000025000)\n+#define QUADSPI0_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X000026000)\n+#define PIT1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X00002A000)\n+#define FCCU_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000030000)\n+#define FLEXTIMER_FTM1_BASE_ADDR\t\t(AIPS1_BASE_ADDR + 0X000036000)\n+#define I2C1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000038000)\n+#define I2C2_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X00003A000)\n+#define LINFLEXD1_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X00003C000)\n+#define FLEXCAN1_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X00003E000)\n+#define SPI1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000040000)\n+#define SPI3_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000042000)\n+#define IPL_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000043000)\n+#define CGM_CMU_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X000044000)\n+#define PMC_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000048000)\n+#define CRC1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X00004C000)\n+#define TMU_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X00004E000)\n+#define VIU1_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000050000)\n+#define JPEG_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000054000)\n+#define H264_DEC_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X000058000)\n+#define H264_ENC_BASE_ADDR\t\t\t\t(AIPS1_BASE_ADDR + 0X00005C000)\n+#define MEMU_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000060000)\n+#define STCU_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000064000)\n+#define SLFTST_CTRL_BASE_ADDR\t\t\t(AIPS1_BASE_ADDR + 0X000066000)\n+#define MCT_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X000068000)\n+#define REP_BASE_ADDR\t\t\t\t\t(AIPS1_BASE_ADDR + 0X00006A000)\n+#define MBIST_CONTROLLER_BASE_ADDR\t\t(AIPS1_BASE_ADDR + 0X00006C000)\n+#define BOOT_LOADER_BASE_ADDR\t\t\t(AIPS1_BASE_ADDR + 0X00006F000)\n+\n+/* TODO Remove this after the IOMUX framework is implemented */\n+#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR\n+\n+/* MUX mode and PAD ctrl are in one register */\n+#define CONFIG_IOMUX_SHARE_CONF_REG\n+\n+#define FEC_QUIRK_ENET_MAC\n+#define I2C_QUIRK_REG\n+\n+/* MSCM interrupt router */\n+#define MSCM_IRSPRC_CPn_EN\t\t3\n+#define MSCM_IRSPRC_NUM\t\t\t176\n+#define MSCM_CPXTYPE_RYPZ_MASK\t\t0xFF\n+#define MSCM_CPXTYPE_RYPZ_OFFSET\t0\n+#define MSCM_CPXTYPE_PERS_MASK\t\t0xFFFFFF00\n+#define MSCM_CPXTYPE_PERS_OFFSET\t8\n+#define MSCM_CPXTYPE_PERS_A53\t\t0x413533\n+#define MSCM_CPXTYPE_PERS_CM4\t\t0x434d34\n+\n+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))\n+#include <asm/types.h>\n+\n+/* System Reset Controller (SRC) */\n+struct src {\n+\tu32 bmr1;\n+\tu32 bmr2;\n+\tu32 gpr1_boot;\n+\tu32 reserved_0x00C[61];\n+\tu32 gpr1;\n+\tu32 gpr2;\n+\tu32 gpr3;\n+\tu32 gpr4;\n+\tu32 gpr5;\n+\tu32 gpr6;\n+\tu32 gpr7;\n+\tu32 reserved_0x11C[1];\n+\tu32 gpr9;\n+\tu32 gpr10;\n+\tu32 gpr11;\n+\tu32 gpr12;\n+\tu32 gpr13;\n+\tu32 gpr14;\n+\tu32 gpr15;\n+\tu32 gpr16;\n+\tu32 reserved_0x140[1];\n+\tu32 gpr17;\n+\tu32 gpr18;\n+\tu32 gpr19;\n+\tu32 gpr20;\n+\tu32 gpr21;\n+\tu32 gpr22;\n+\tu32 gpr23;\n+\tu32 gpr24;\n+\tu32 gpr25;\n+\tu32 gpr26;\n+\tu32 gpr27;\n+\tu32 reserved_0x16C[5];\n+\tu32 pcie_config1;\n+\tu32 ddr_self_ref_ctrl;\n+\tu32 pcie_config0;\n+\tu32 reserved_0x18C[4];\n+\tu32 soc_misc_config2;\n+};\n+\n+/* SRC registers definitions */\n+\n+/* SRC_GPR1 */\n+#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \\\n+\t\t\t\t\t\t\t\t\t\t(SRC_GPR1_PLL_OFFSET + (pll)) )\n+#define SRC_GPR1_PLL_SOURCE_MASK\t(0x1)\n+\n+#define SRC_GPR1_PLL_OFFSET\t\t\t(27)\n+#define SRC_GPR1_FIRC_CLK_SOURCE\t(0x0)\n+#define SRC_GPR1_XOSC_CLK_SOURCE\t(0x1)\n+\n+/* Periodic Interrupt Timer (PIT) */\n+struct pit_reg {\n+\tu32 mcr;\n+\tu32 recv0[55];\n+\tu32 ltmr64h;\n+\tu32 ltmr64l;\n+\tu32 recv1[6];\n+\tu32 ldval0;\n+\tu32 cval0;\n+\tu32 tctrl0;\n+\tu32 tflg0;\n+\tu32 ldval1;\n+\tu32 cval1;\n+\tu32 tctrl1;\n+\tu32 tflg1;\n+\tu32 ldval2;\n+\tu32 cval2;\n+\tu32 tctrl2;\n+\tu32 tflg2;\n+\tu32 ldval3;\n+\tu32 cval3;\n+\tu32 tctrl3;\n+\tu32 tflg3;\n+\tu32 ldval4;\n+\tu32 cval4;\n+\tu32 tctrl4;\n+\tu32 tflg4;\n+\tu32 ldval5;\n+\tu32 cval5;\n+\tu32 tctrl5;\n+\tu32 tflg5;\n+};\n+\n+/* Watchdog Timer (WDOG) */\n+struct wdog_regs {\n+\tu32 cr;\n+\tu32 ir;\n+\tu32 to;\n+\tu32 wn;\n+\tu32 sr;\n+\tu32 co;\n+\tu32 sk;\n+};\n+\n+/* UART */\n+struct linflex_fsl {\n+\tu32 lincr1;\n+\tu32 linier;\n+\tu32 linsr;\n+\tu32 linesr;\n+\tu32 uartcr;\n+\tu32 uartsr;\n+\tu32 lintcsr;\n+\tu32 linocr;\n+\tu32 lintocr;\n+\tu32 linfbrr;\n+\tu32 linibrr;\n+\tu32 lincfr;\n+\tu32 lincr2;\n+\tu32 bidr;\n+\tu32 bdrl;\n+\tu32 bdrm;\n+\tu32 ifer;\n+\tu32 ifmi;\n+\tu32 ifmr;\n+\tu32 ifcr0;\n+\tu32 ifcr1;\n+\tu32 ifcr2;\n+\tu32 ifcr3;\n+\tu32 ifcr4;\n+\tu32 ifcr5;\n+\tu32 ifcr6;\n+\tu32 ifcr7;\n+\tu32 ifcr8;\n+\tu32 ifcr9;\n+\tu32 ifcr10;\n+\tu32 ifcr11;\n+\tu32 ifcr12;\n+\tu32 ifcr13;\n+\tu32 ifcr14;\n+\tu32 ifcr15;\n+\tu32 gcr;\n+\tu32 uartpto;\n+\tu32 uartcto;\n+\tu32 dmatxe;\n+\tu32 dmarxe;\n+};\n+\n+/* MSCM Interrupt Router */\n+struct mscm_ir {\n+\tu32 cpxtype;\t\t/* Processor x Type Register */\n+\tu32 cpxnum;\t\t/* Processor x Number Register */\n+\tu32 cpxmaster;\t\t/* Processor x Master Number Register */\n+\tu32 cpxcount;\t\t/* Processor x Count Register */\n+\tu32 cpxcfg0;\t\t/* Processor x Configuration 0 Register */\n+\tu32 cpxcfg1;\t\t/* Processor x Configuration 1 Register */\n+\tu32 cpxcfg2;\t\t/* Processor x Configuration 2 Register */\n+\tu32 cpxcfg3;\t\t/* Processor x Configuration 3 Register */\n+\tu32 cp0type;\t\t/* Processor 0 Type Register */\n+\tu32 cp0num;\t\t/* Processor 0 Number Register */\n+\tu32 cp0master;\t\t/* Processor 0 Master Number Register */\n+\tu32 cp0count;\t\t/* Processor 0 Count Register */\n+\tu32 cp0cfg0;\t\t/* Processor 0 Configuration 0 Register */\n+\tu32 cp0cfg1;\t\t/* Processor 0 Configuration 1 Register */\n+\tu32 cp0cfg2;\t\t/* Processor 0 Configuration 2 Register */\n+\tu32 cp0cfg3;\t\t/* Processor 0 Configuration 3 Register */\n+\tu32 cp1type;\t\t/* Processor 1 Type Register */\n+\tu32 cp1num;\t\t/* Processor 1 Number Register */\n+\tu32 cp1master;\t\t/* Processor 1 Master Number Register */\n+\tu32 cp1count;\t\t/* Processor 1 Count Register */\n+\tu32 cp1cfg0;\t\t/* Processor 1 Configuration 0 Register */\n+\tu32 cp1cfg1;\t\t/* Processor 1 Configuration 1 Register */\n+\tu32 cp1cfg2;\t\t/* Processor 1 Configuration 2 Register */\n+\tu32 cp1cfg3;\t\t/* Processor 1 Configuration 3 Register */\n+\tu32 reserved_0x060[232];\n+\tu32 ocmdr0;\t\t/* On-Chip Memory Descriptor Register */\n+\tu32 reserved_0x404[2];\n+\tu32 ocmdr3;\t\t/* On-Chip Memory Descriptor Register */\n+\tu32 reserved_0x410[28];\n+\tu32 tcmdr[4];\t\t/* Generic Tightly Coupled Memory Descriptor Register */\n+\tu32 reserved_0x490[28];\n+\tu32 cpce0;\t\t/* Core Parity Checking Enable Register 0 */\n+\tu32 reserved_0x504[191];\n+\tu32 ircp0ir;\t\t/* Interrupt Router CP0 Interrupt Register */\n+\tu32 ircp1ir;\t\t/* Interrupt Router CP1 Interrupt Register */\n+\tu32 reserved_0x808[6];\n+\tu32 ircpgir;\t\t/* Interrupt Router CPU Generate Interrupt Register */\n+\tu32 reserved_0x824[23];\n+\tu16 irsprc[176];\t/* Interrupt Router Shared Peripheral Routing Control Register */\n+\tu32 reserved_0x9e0[136];\n+\tu32 iahbbe0;\t\t/* Gasket Burst Enable Register */\n+\tu32 reserved_0xc04[63];\n+\tu32 ipcge;\t\t/* Interconnect Parity Checking Global Enable Register */\n+\tu32 reserved_0xd04[3];\n+\tu32 ipce[4];\t\t/* Interconnect Parity Checking Enable Register */\n+\tu32 reserved_0xd20[8];\n+\tu32 ipcgie;\t\t/* Interconnect Parity Checking Global Injection Enable Register */\n+\tu32 reserved_0xd44[3];\n+\tu32 ipcie[4];\t\t/* Interconnect Parity Checking Injection Enable Register */\n+};\n+\n+#endif /* __ASSEMBLER__ */\n+\n+#endif /* __ASM_ARCH_IMX_REGS_H__ */\ndiff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h\nnew file mode 100644\nindex 0000000..5a05965\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/lpddr2.h\n@@ -0,0 +1,75 @@\n+/*\n+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__\n+#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__\n+\n+/* definitions for LPDDR2 PAD values */\n+#define LPDDR2_CLK0_PAD\t\\\n+\t(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\\\n+\t SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 |\t\t\t\\\n+\t SIUL2_MSCR_DCYCLE_TRIM_NONE)\n+#define LPDDR2_CKEn_PAD\t\\\n+\t(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\\\n+\t SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)\n+#define LPDDR2_CS_Bn_PAD\t\\\n+\t(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\\\n+\t SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)\n+#define LPDDR2_DMn_PAD\t\\\n+\t(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\\\n+\t SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)\n+#define LPDDR2_DQSn_PAD\t\\\n+\t(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\t\\\n+\t SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN |\t\t\t\t\t\t\\\n+\t SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)\n+#define LPDDR2_An_PAD\t\\\n+\t(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\t\\\n+\t SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT\t\t|\t\\\n+\t SIUL2_MSCR_PUS_100K_UP)\n+#define LPDDR2_Dn_PAD\t\\\n+\t(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\t\\\n+\t SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT\t\t|\t\\\n+\t SIUL2_MSCR_PUS_100K_UP)\n+\n+#define _MDCTL\t\t\t\t\t\t\t0x03010000\n+\n+#define MMDC_MDSCR_CFG_VALUE\t\t\t0x00008000\t/* Set MDSCR[CON_REQ] (configuration request) */\n+#define MMDC_MDCFG0_VALUE\t\t\t\t0x464F61A5\t/* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */\n+#define MMDC_MDCFG1_VALUE\t\t\t\t0x00180E63\t/* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */\n+#define MMDC_MDCFG2_VALUE\t\t\t\t0x000000DD\t/* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */\n+#define MMDC_MDCFG3LP_VALUE\t\t\t\t0x001F099B\t/* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */\n+#define MMDC_MDOTC_VALUE\t\t\t\t0x00000000\t/* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */\n+#define MMDC_MDMISC_VALUE\t\t\t\t0x00001688\t/* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */\n+#define MMDC_MDOR_VALUE\t\t\t\t\t0x00000010\t/* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */\n+#define MMDC_MPMUR0_VALUE\t\t\t\t0x00000800\t/* Force delay line initialisation */\n+#define MMDC_MDSCR_RST_VALUE\t\t\t0x003F8030\t/* Reset command CS0 */\n+#define MMDC_MPZQLP2CTL_VALUE\t\t\t0x1B5F0109\t/* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */\n+#define MMDC_MPZQHWCTRL_VALUE\t\t\t0xA0010003\t/* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */\n+#define MMDC_MDSCR_MR1_VALUE\t\t\t0xC2018030\t/* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */\n+#define MMDC_MDSCR_MR2_VALUE\t\t\t0x06028030\t/* Configure MR2: RL=8, WL=4 */\n+#define MMDC_MDSCR_MR3_VALUE\t\t\t0x01038030\t/* Configure MR3: DS=34R */\n+#define MMDC_MDSCR_MR10_VALUE\t\t\t0xFF0A8030\t/* Configure MR10: Calibration at init */\n+#define MMDC_MDASP_MODULE0_VALUE\t\t0x0000007F\t/* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */\n+#define MMDC_MPRDDLCTL_MODULE0_VALUE\t0x4D4B4F4B\t/* Read delay line offsets */\n+#define MMDC_MPWRDLCTL_MODULE0_VALUE\t0x38383737\t/* Write delay line offsets */\n+#define MMDC_MPDGCTRL0_MODULE0_VALUE\t0x20000000\t/* Read DQS gating control 0 (disabled) */\n+#define MMDC_MPDGCTRL1_MODULE0_VALUE\t0x00000000\t/* Read DQS gating control 1 */\n+#define MMDC_MDASP_MODULE1_VALUE\t\t0x0000007F\t/* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */\n+#define MMDC_MPRDDLCTL_MODULE1_VALUE\t0x4D4B4F4B\t/* Read delay line offsets */\n+#define MMDC_MPWRDLCTL_MODULE1_VALUE\t0x38383737\t/* Write delay line offsets */\n+#define MMDC_MPDGCTRL0_MODULE1_VALUE\t0x20000000\t/* Read DQS gating control 0 (disabled) */\n+#define MMDC_MPDGCTRL1_MODULE1_VALUE\t0x00000000\t/* Read DQS gating control 1 */\n+#define MMDC_MDRWD_VALUE\t\t\t\t0x0F9F26D2\t/* Read/write command delay - default used */\n+#define MMDC_MDPDC_VALUE\t\t\t\t0x00020024\t/* Power down control */\n+#define MMDC_MDREF_VALUE\t\t\t\t0x30B01800\t/* Refresh control */\n+#define MMDC_MPODTCTRL_VALUE\t\t\t0x00000000\t/* No ODT */\n+#define MMDC_MDSCR_DEASSERT_VALUE\t\t\t\t0x00000000\t/* Deassert the configuration request */\n+\n+/* set I/O pads for DDR */\n+void lpddr2_config_iomux(uint8_t module);\n+void config_mmdc(uint8_t module);\n+\n+#endif\ndiff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h\nnew file mode 100644\nindex 0000000..eb50475\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h\n@@ -0,0 +1,254 @@\n+/*\n+ * (C) Copyright 2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__\n+#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__\n+\n+#ifndef __ASSEMBLY__\n+\n+/* MC_CGM registers definitions */\n+/* MC_CGM_SC_SS */\n+#define CGM_SC_SS(cgm_addr)\t\t\t( ((cgm_addr) + 0x000007E4) )\n+#define MC_CGM_SC_SEL_FIRC\t\t\t(0x0)\n+#define MC_CGM_SC_SEL_XOSC\t\t\t(0x1)\n+#define MC_CGM_SC_SEL_ARMPLL\t\t(0x2)\n+#define MC_CGM_SC_SEL_CLKDISABLE\t(0xF)\n+\n+/* MC_CGM_SC_DCn */\n+#define CGM_SC_DCn(cgm_addr,dc)\t\t( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )\n+#define MC_CGM_SC_DCn_PREDIV(val)\t(MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))\n+#define MC_CGM_SC_DCn_PREDIV_MASK\t(0x00070000)\n+#define MC_CGM_SC_DCn_PREDIV_OFFSET\t(16)\n+#define MC_CGM_SC_DCn_DE\t\t\t(1 << 31)\n+#define MC_CGM_SC_SEL_MASK\t\t\t(0x0F000000)\n+#define MC_CGM_SC_SEL_OFFSET\t\t(24)\n+\n+/* MC_CGM_ACn_DCm */\n+#define CGM_ACn_DCm(cgm_addr,ac,dc)\t\t( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )\n+#define MC_CGM_ACn_DCm_PREDIV(val)\t\t(MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))\n+\n+/*\n+ * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown\n+ * that the 5th bit is always ignored during writes if the current\n+ * MC_CGM_ACn_DCm_PREDIV field has only 4 bits\n+ *\n+ * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits\n+ *\n+ * This should be changed if any problems occur.\n+ */\n+#define MC_CGM_ACn_DCm_PREDIV_MASK\t\t(0x001F0000)\n+#define MC_CGM_ACn_DCm_PREDIV_OFFSET\t(16)\n+#define MC_CGM_ACn_DCm_DE\t\t\t\t(1 << 31)\n+\n+/*\n+ * MC_CGM_ACn_SC/MC_CGM_ACn_SS\n+ */\n+#define CGM_ACn_SC(cgm_addr,ac)\t\t\t((cgm_addr + 0x00000800) + ((ac) * 0x20))\n+#define CGM_ACn_SS(cgm_addr,ac)\t\t\t((cgm_addr + 0x00000804) + ((ac) * 0x20))\n+#define MC_CGM_ACn_SEL_MASK\t\t\t\t(0x07000000)\n+#define MC_CGM_ACn_SEL_SET(source)\t\t(MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))\n+#define MC_CGM_ACn_SEL_OFFSET\t\t\t(24)\n+\n+#define MC_CGM_ACn_SEL_FIRC\t\t\t\t(0x0)\n+#define MC_CGM_ACn_SEL_XOSC\t\t\t\t(0x1)\n+#define MC_CGM_ACn_SEL_ARMPLL\t\t\t(0x2)\n+/*\n+ * According to the manual some PLL can be divided by X (X={1,3,5}):\n+ * PERPLLDIVX, VIDEOPLLDIVX.\n+ */\n+#define MC_CGM_ACn_SEL_PERPLLDIVX\t\t(0x3)\n+#define MC_CGM_ACn_SEL_ENETPLL\t\t\t(0x4)\n+#define MC_CGM_ACn_SEL_DDRPLL\t\t\t(0x5)\n+#define MC_CGM_ACn_SEL_EXTSRCPAD\t\t(0x7)\n+#define MC_CGM_ACn_SEL_SYSCLK\t\t\t(0x8)\n+#define MC_CGM_ACn_SEL_VIDEOPLLDIVX\t\t(0x9)\n+#define MC_CGM_ACn_SEL_PERCLK\t\t\t(0xA)\n+\n+/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */\n+#define PLLDIG_PLLDV(pll)\t\t\t\t((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))\n+#define PLLDIG_PLLDV_MFD(div)\t\t\t(PLLDIG_PLLDV_MFD_MASK & (div))\n+#define PLLDIG_PLLDV_MFD_MASK\t\t\t(0x000000FF)\n+\n+/*\n+ * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to\n+ * the reference manual. This other value respect the formula 2^[RFDPHIBY+1]\n+ */\n+#define PLLDIG_PLLDV_RFDPHI_SET(val)\t(PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))\n+#define PLLDIG_PLLDV_RFDPHI_MASK\t\t(0x003F0000)\n+#define PLLDIG_PLLDV_RFDPHI_MAXVALUE\t(0x3F)\n+#define PLLDIG_PLLDV_RFDPHI_OFFSET\t\t(16)\n+\n+#define PLLDIG_PLLDV_RFDPHI1_SET(val)\t(PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))\n+#define PLLDIG_PLLDV_RFDPHI1_MASK\t\t(0x7E000000)\n+#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE\t(0x3F)\n+#define PLLDIG_PLLDV_RFDPHI1_OFFSET\t\t(25)\n+\n+#define PLLDIG_PLLDV_PREDIV_SET(val)\t(PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))\n+#define PLLDIG_PLLDV_PREDIV_MASK\t\t(0x00007000)\n+#define PLLDIG_PLLDV_PREDIV_MAXVALUE\t(0x7)\n+#define PLLDIG_PLLDV_PREDIV_OFFSET\t\t(12)\n+\n+/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */\n+#define PLLDIG_PLLFD(pll)\t\t\t\t((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))\n+#define PLLDIG_PLLFD_MFN_SET(val)\t\t(PLLDIG_PLLFD_MFN_MASK & (val))\n+#define PLLDIG_PLLFD_MFN_MASK\t\t\t(0x00007FFF)\n+#define PLLDIG_PLLFD_SMDEN\t\t\t\t(1 << 30)\n+\n+/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */\n+#define PLLDIG_PLLCAL1(pll)\t\t\t\t((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))\n+#define PLLDIG_PLLCAL1_NDAC1_SET(val)\t(PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))\n+#define PLLDIG_PLLCAL1_NDAC1_OFFSET\t\t(24)\n+#define PLLDIG_PLLCAL1_NDAC1_MASK\t\t(0x7F000000)\n+\n+/* Digital Frequency Synthesizer (DFS) */\n+/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */\n+#define DFS0_BASE_ADDR\t\t\t\t(MC_CGM0_BASE_ADDR + 0x00000040)\n+\n+/* DFS DLL Program Register 1 */\n+#define DFS_DLLPRG1(pll)\t\t\t(DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))\n+\n+#define DFS_DLLPRG1_V2IGC_SET(val)\t(DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))\n+#define DFS_DLLPRG1_V2IGC_OFFSET\t(0)\n+#define DFS_DLLPRG1_V2IGC_MASK\t\t(0x00000007)\n+\n+#define DFS_DLLPRG1_LCKWT_SET(val)\t\t(DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))\n+#define DFS_DLLPRG1_LCKWT_OFFSET\t\t(4)\n+#define DFS_DLLPRG1_LCKWT_MASK\t\t\t(0x00000030)\n+\n+#define DFS_DLLPRG1_DACIN_SET(val)\t\t(DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))\n+#define DFS_DLLPRG1_DACIN_OFFSET\t\t(6)\n+#define DFS_DLLPRG1_DACIN_MASK\t\t\t(0x000001C0)\n+\n+#define DFS_DLLPRG1_CALBYPEN_SET(val)\t(DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))\n+#define DFS_DLLPRG1_CALBYPEN_OFFSET\t\t(9)\n+#define DFS_DLLPRG1_CALBYPEN_MASK\t\t(0x00000200)\n+\n+#define DFS_DLLPRG1_VSETTLCTRL_SET(val)\t(DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))\n+#define DFS_DLLPRG1_VSETTLCTRL_OFFSET\t(10)\n+#define DFS_DLLPRG1_VSETTLCTRL_MASK\t\t(0x00000C00)\n+\n+#define DFS_DLLPRG1_CPICTRL_SET(val)\t(DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))\n+#define DFS_DLLPRG1_CPICTRL_OFFSET\t\t(12)\n+#define DFS_DLLPRG1_CPICTRL_MASK\t\t(0x00007000)\n+\n+/* DFS Control Register (DFS_CTRL) */\n+#define DFS_CTRL(pll)\t\t\t\t\t(DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))\n+#define DFS_CTRL_DLL_LOLIE\t\t\t\t(1 << 0)\n+#define DFS_CTRL_DLL_RESET\t\t\t\t(1 << 1)\n+\n+/* DFS Port Status Register (DFS_PORTSR) */\n+#define DFS_PORTSR(pll)\t\t\t\t\t\t(DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))\n+/* DFS Port Reset Register (DFS_PORTRESET) */\n+#define DFS_PORTRESET(pll)\t\t\t\t\t(DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))\n+#define DFS_PORTRESET_PORTRESET_SET(val)\t(DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))\n+#define DFS_PORTRESET_PORTRESET_MAXVAL\t\t(0xF)\n+#define DFS_PORTRESET_PORTRESET_MASK\t\t(0x0000000F)\n+#define DFS_PORTRESET_PORTRESET_OFFSET\t\t(0)\n+\n+/* DFS Divide Register Portn (DFS_DVPORTn) */\n+#define DFS_DVPORTn(pll,n)\t\t\t(DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))\n+\n+/*\n+ * The mathematical formula for fdfs_clockout is the following:\n+ * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )\n+ */\n+#define DFS_DVPORTn_MFI_SET(val)\t(DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )\n+#define DFS_DVPORTn_MFN_SET(val)\t(DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )\n+#define DFS_DVPORTn_MFI_MASK\t\t(0x0000FF00)\n+#define DFS_DVPORTn_MFN_MASK\t\t(0x000000FF)\n+#define DFS_DVPORTn_MFI_MAXVAL\t\t(0xFF)\n+#define DFS_DVPORTn_MFN_MAXVAL\t\t(0xFF)\n+#define DFS_DVPORTn_MFI_OFFSET\t\t(8)\n+#define DFS_DVPORTn_MFN_OFFSET\t\t(0)\n+#define DFS_MAXNUMBER\t\t\t\t(4)\n+\n+#define DFS_PARAMS_Nr\t\t\t\t(3)\n+\n+/* Frequencies are in Hz */\n+#define FIRC_CLK_FREQ\t\t\t\t(48000000)\n+#define XOSC_CLK_FREQ\t\t\t\t(40000000)\n+\n+#define PLL_MIN_FREQ\t\t\t\t(650000000)\n+#define PLL_MAX_FREQ\t\t\t\t(1300000000)\n+\n+#define ARM_PLL_PHI0_FREQ\t\t\t(1000000000)\n+#define ARM_PLL_PHI1_FREQ\t\t\t(1000000000)\n+/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */\n+#define ARM_PLL_PHI1_DFS1_EN\t\t(1)\n+#define ARM_PLL_PHI1_DFS1_MFI\t\t(3)\n+#define ARM_PLL_PHI1_DFS1_MFN\t\t(194)\n+/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */\n+#define ARM_PLL_PHI1_DFS2_EN\t\t(1)\n+#define ARM_PLL_PHI1_DFS2_MFI\t\t(1)\n+#define ARM_PLL_PHI1_DFS2_MFN\t\t(170)\n+/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */\n+#define ARM_PLL_PHI1_DFS3_EN\t\t(1)\n+#define ARM_PLL_PHI1_DFS3_MFI\t\t(1)\n+#define ARM_PLL_PHI1_DFS3_MFN\t\t(170)\n+#define ARM_PLL_PHI1_DFS_Nr\t\t\t(3)\n+#define ARM_PLL_PLLDV_PREDIV\t\t(2)\n+#define ARM_PLL_PLLDV_MFD\t\t\t(50)\n+#define ARM_PLL_PLLDV_MFN\t\t\t(0)\n+\n+#define PERIPH_PLL_PHI0_FREQ\t\t(400000000)\n+#define PERIPH_PLL_PHI1_FREQ\t\t(100000000)\n+#define PERIPH_PLL_PHI1_DFS_Nr\t\t(0)\n+#define PERIPH_PLL_PLLDV_PREDIV\t\t(1)\n+#define PERIPH_PLL_PLLDV_MFD\t\t(30)\n+#define PERIPH_PLL_PLLDV_MFN\t\t(0)\n+\n+#define ENET_PLL_PHI0_FREQ\t\t\t(500000000)\n+#define ENET_PLL_PHI1_FREQ\t\t\t(1000000000)\n+/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/\n+#define ENET_PLL_PHI1_DFS1_EN\t\t(1)\n+#define ENET_PLL_PHI1_DFS1_MFI\t\t(2)\n+#define ENET_PLL_PHI1_DFS1_MFN\t\t(219)\n+/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/\n+#define ENET_PLL_PHI1_DFS2_EN\t\t(1)\n+#define ENET_PLL_PHI1_DFS2_MFI\t\t(2)\n+#define ENET_PLL_PHI1_DFS2_MFN\t\t(219)\n+/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/\n+#define ENET_PLL_PHI1_DFS3_EN\t\t(1)\n+#define ENET_PLL_PHI1_DFS3_MFI\t\t(3)\n+#define ENET_PLL_PHI1_DFS3_MFN\t\t(32)\n+/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/\n+#define ENET_PLL_PHI1_DFS4_EN\t\t(1)\n+#define ENET_PLL_PHI1_DFS4_MFI\t\t(2)\n+#define ENET_PLL_PHI1_DFS4_MFN\t\t(0)\n+#define ENET_PLL_PHI1_DFS_Nr\t\t(4)\n+#define ENET_PLL_PLLDV_PREDIV\t\t(2)\n+#define ENET_PLL_PLLDV_MFD\t\t\t(50)\n+#define ENET_PLL_PLLDV_MFN\t\t\t(0)\n+\n+#define DDR_PLL_PHI0_FREQ\t\t\t(533000000)\n+#define DDR_PLL_PHI1_FREQ\t\t\t(1066000000)\n+/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */\n+#define DDR_PLL_PHI1_DFS1_EN\t\t(1)\n+#define DDR_PLL_PHI1_DFS1_MFI\t\t(2)\n+#define DDR_PLL_PHI1_DFS1_MFN\t\t(33)\n+/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */\n+#define DDR_PLL_PHI1_DFS2_EN\t\t(1)\n+#define DDR_PLL_PHI1_DFS2_MFI\t\t(2)\n+#define DDR_PLL_PHI1_DFS2_MFN\t\t(33)\n+/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */\n+#define DDR_PLL_PHI1_DFS3_EN\t\t(1)\n+#define DDR_PLL_PHI1_DFS3_MFI\t\t(3)\n+#define DDR_PLL_PHI1_DFS3_MFN\t\t(11)\n+#define DDR_PLL_PHI1_DFS_Nr\t\t\t(3)\n+#define DDR_PLL_PLLDV_PREDIV\t\t(2)\n+#define DDR_PLL_PLLDV_MFD\t\t\t(53)\n+#define DDR_PLL_PLLDV_MFN\t\t\t(6144)\n+\n+#define VIDEO_PLL_PHI0_FREQ\t\t\t(600000000)\n+#define VIDEO_PLL_PHI1_FREQ\t\t\t(0)\n+#define VIDEO_PLL_PHI1_DFS_Nr\t\t(0)\n+#define VIDEO_PLL_PLLDV_PREDIV\t\t(1)\n+#define VIDEO_PLL_PLLDV_MFD\t\t\t(30)\n+#define VIDEO_PLL_PLLDV_MFN\t\t\t(0)\n+\n+#endif\n+\n+#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */\ndiff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h\nnew file mode 100644\nindex 0000000..a1172e0\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h\n@@ -0,0 +1,199 @@\n+/*\n+ * (C) Copyright 2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__\n+#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__\n+\n+#ifndef __ASSEMBLY__\n+\n+/* MC_ME registers definitions */\n+\n+/* MC_ME_GS */\n+#define MC_ME_GS\t\t\t\t\t\t(MC_ME_BASE_ADDR + 0x00000000)\n+\n+#define MC_ME_GS_S_SYSCLK_FIRC\t\t\t(0x0 << 0)\n+#define MC_ME_GS_S_SYSCLK_FXOSC\t\t\t(0x1 << 0)\n+#define MC_ME_GS_S_SYSCLK_ARMPLL\t\t(0x2 << 0)\n+#define MC_ME_GS_S_STSCLK_DISABLE\t\t(0xF << 0)\n+#define MC_ME_GS_S_FIRC\t\t\t\t\t(1 << 4)\n+#define MC_ME_GS_S_XOSC\t\t\t\t\t(1 << 5)\n+#define MC_ME_GS_S_ARMPLL\t\t\t\t(1 << 6)\n+#define MC_ME_GS_S_PERPLL\t\t\t\t(1 << 7)\n+#define MC_ME_GS_S_ENETPLL\t\t\t\t(1 << 8)\n+#define MC_ME_GS_S_DDRPLL\t\t\t\t(1 << 9)\n+#define MC_ME_GS_S_VIDEOPLL\t\t\t\t(1 << 10)\n+#define MC_ME_GS_S_MVR\t\t\t\t\t(1 << 20)\n+#define MC_ME_GS_S_PDO\t\t\t\t\t(1 << 23)\n+#define MC_ME_GS_S_MTRANS\t\t\t\t(1 << 27)\n+#define MC_ME_GS_S_CRT_MODE_RESET\t\t(0x0 << 28)\n+#define MC_ME_GS_S_CRT_MODE_TEST\t\t(0x1 << 28)\n+#define MC_ME_GS_S_CRT_MODE_DRUN\t\t(0x3 << 28)\n+#define MC_ME_GS_S_CRT_MODE_RUN0\t\t(0x4 << 28)\n+#define MC_ME_GS_S_CRT_MODE_RUN1\t\t(0x5 << 28)\n+#define MC_ME_GS_S_CRT_MODE_RUN2\t\t(0x6 << 28)\n+#define MC_ME_GS_S_CRT_MODE_RUN3\t\t(0x7 << 28)\n+\n+/* MC_ME_MCTL */\n+#define MC_ME_MCTL\t\t\t\t\t\t(MC_ME_BASE_ADDR + 0x00000004)\n+\n+#define MC_ME_MCTL_KEY\t\t\t\t\t(0x00005AF0)\n+#define MC_ME_MCTL_INVERTEDKEY\t\t\t(0x0000A50F)\n+#define MC_ME_MCTL_RESET\t\t\t\t(0x0 << 28)\n+#define MC_ME_MCTL_TEST\t\t\t\t\t(0x1 << 28)\n+#define MC_ME_MCTL_DRUN\t\t\t\t\t(0x3 << 28)\n+#define MC_ME_MCTL_RUN0\t\t\t\t\t(0x4 << 28)\n+#define MC_ME_MCTL_RUN1\t\t\t\t\t(0x5 << 28)\n+#define MC_ME_MCTL_RUN2\t\t\t\t\t(0x6 << 28)\n+#define MC_ME_MCTL_RUN3\t\t\t\t\t(0x7 << 28)\n+\n+/* MC_ME_ME */\n+#define MC_ME_ME\t\t\t\t\t\t(MC_ME_BASE_ADDR + 0x00000008)\n+\n+#define MC_ME_ME_RESET_FUNC\t\t\t\t(1 << 0)\n+#define MC_ME_ME_TEST\t\t\t\t\t(1 << 1)\n+#define MC_ME_ME_DRUN\t\t\t\t\t(1 << 3)\n+#define MC_ME_ME_RUN0\t\t\t\t\t(1 << 4)\n+#define MC_ME_ME_RUN1\t\t\t\t\t(1 << 5)\n+#define MC_ME_ME_RUN2\t\t\t\t\t(1 << 6)\n+#define MC_ME_ME_RUN3\t\t\t\t\t(1 << 7)\n+\n+/* MC_ME_RUN_PCn */\n+#define MC_ME_RUN_PCn(n)\t\t\t\t(MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))\n+\n+#define MC_ME_RUN_PCn_RESET\t\t\t\t(1 << 0)\n+#define MC_ME_RUN_PCn_TEST\t\t\t\t(1 << 1)\n+#define MC_ME_RUN_PCn_DRUN\t\t\t\t(1 << 3)\n+#define MC_ME_RUN_PCn_RUN0\t\t\t\t(1 << 4)\n+#define MC_ME_RUN_PCn_RUN1\t\t\t\t(1 << 5)\n+#define MC_ME_RUN_PCn_RUN2\t\t\t\t(1 << 6)\n+#define MC_ME_RUN_PCn_RUN3\t\t\t\t(1 << 7)\n+\n+/*\n+ * MC_ME_RESET_MC/MC_ME_TEST_MC\n+ * MC_ME_DRUN_MC\n+ * MC_ME_RUNn_MC\n+ */\n+#define MC_ME_RESET_MC\t\t\t\t\t\t(MC_ME_BASE_ADDR + 0x00000020)\n+#define MC_ME_TEST_MC\t\t\t\t\t\t(MC_ME_BASE_ADDR + 0x00000024)\n+#define MC_ME_DRUN_MC\t\t\t\t\t\t(MC_ME_BASE_ADDR + 0x0000002C)\n+#define MC_ME_RUNn_MC(n)\t\t\t\t\t(MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))\n+\n+#define MC_ME_RUNMODE_MC_SYSCLK(val)\t(MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))\n+#define MC_ME_RUNMODE_MC_SYSCLK_MASK\t(0x0000000F)\n+#define MC_ME_RUNMODE_MC_FIRCON\t\t\t(1 << 4)\n+#define MC_ME_RUNMODE_MC_XOSCON\t\t\t(1 << 5)\n+#define MC_ME_RUNMODE_MC_PLL(pll)\t\t(1 << (6 + (pll)))\n+#define MC_ME_RUNMODE_MC_MVRON\t\t\t(1 << 20)\n+#define MC_ME_RUNMODE_MC_PDO\t\t\t(1 << 23)\n+#define MC_ME_RUNMODE_MC_PWRLVL0\t\t(1 << 28)\n+#define MC_ME_RUNMODE_MC_PWRLVL1\t\t(1 << 29)\n+#define MC_ME_RUNMODE_MC_PWRLVL2\t\t(1 << 30)\n+\n+/* MC_ME_DRUN_SEC_CC_I */\n+#define MC_ME_DRUN_SEC_CC_I\t\t\t\t\t(MC_ME_BASE_ADDR + 0x260)\n+/* MC_ME_RUNn_SEC_CC_I */\n+#define MC_ME_RUNn_SEC_CC_I(n)\t\t\t\t(MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)\n+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset)\t((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)\n+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET\t(4)\n+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET\t(8)\n+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET\t(12)\n+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK\t\t(0x3)\n+\n+/*\n+ * ME_PCTLn\n+ * Please note that these registers are 8 bits width, so\n+ * the operations over them should be done using 8 bits operations.\n+ */\n+#define MC_ME_PCTLn_RUNPCm(n)\t\t\t( (n) & MC_ME_PCTLn_RUNPCm_MASK )\n+#define MC_ME_PCTLn_RUNPCm_MASK\t\t\t(0x7)\n+\n+/* DEC200 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL39\t(MC_ME_BASE_ADDR + 0x000000E4)\n+/* 2D-ACE Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL40\t(MC_ME_BASE_ADDR + 0x000000EB)\n+/* ENET Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL50\t(MC_ME_BASE_ADDR + 0x000000F1)\n+/* DMACHMUX0 Peripheral Control Register\t*/\n+#define MC_ME_PCTL49\t(MC_ME_BASE_ADDR + 0x000000F2)\n+/* CSI0 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL48\t(MC_ME_BASE_ADDR + 0x000000F3)\n+/* MMDC0 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL54\t(MC_ME_BASE_ADDR + 0x000000F5)\n+/* FRAY Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL52\t(MC_ME_BASE_ADDR + 0x000000F7)\n+/* PIT0 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL58\t(MC_ME_BASE_ADDR + 0x000000F9)\n+/* FlexTIMER0 Peripheral Control Register\t*/\n+#define MC_ME_PCTL79\t(MC_ME_BASE_ADDR + 0x0000010C)\n+/* SARADC0 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL77\t(MC_ME_BASE_ADDR + 0x0000010E)\n+/* LINFLEX0 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL83\t(MC_ME_BASE_ADDR + 0x00000110)\n+/* IIC0 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL81\t(MC_ME_BASE_ADDR + 0x00000112)\n+/* DSPI0 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL87\t(MC_ME_BASE_ADDR + 0x00000114)\n+/* CANFD0 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL85\t(MC_ME_BASE_ADDR + 0x00000116)\n+/* CRC0 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL91\t(MC_ME_BASE_ADDR + 0x00000118)\n+/* DSPI2 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL89\t(MC_ME_BASE_ADDR + 0x0000011A)\n+/* SDHC Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL93\t(MC_ME_BASE_ADDR + 0x0000011E)\n+/* VIU0 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL100\t(MC_ME_BASE_ADDR + 0x00000127)\n+/* HPSMI Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL104\t(MC_ME_BASE_ADDR + 0x0000012B)\n+/* SIPI Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL116\t(MC_ME_BASE_ADDR + 0x00000137)\n+/* LFAST Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL120\t(MC_ME_BASE_ADDR + 0x0000013B)\n+/* MMDC1 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL162\t(MC_ME_BASE_ADDR + 0x00000161)\n+/* DMACHMUX1 Peripheral Control Register\t*/\n+#define MC_ME_PCTL161\t(MC_ME_BASE_ADDR + 0x00000162)\n+/* CSI1 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL160\t(MC_ME_BASE_ADDR + 0x00000163)\n+/* QUADSPI0 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL166\t(MC_ME_BASE_ADDR + 0x00000165)\n+/* PIT1 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL170\t(MC_ME_BASE_ADDR + 0x00000169)\n+/* FlexTIMER1 Peripheral Control Register\t*/\n+#define MC_ME_PCTL182\t(MC_ME_BASE_ADDR + 0x00000175)\n+/* IIC2 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL186\t(MC_ME_BASE_ADDR + 0x00000179)\n+/* IIC1 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL184\t(MC_ME_BASE_ADDR + 0x0000017B)\n+/* CANFD1 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL190\t(MC_ME_BASE_ADDR + 0x0000017D)\n+/* LINFLEX1 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL188\t(MC_ME_BASE_ADDR + 0x0000017F)\n+/* DSPI3 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL194\t(MC_ME_BASE_ADDR + 0x00000181)\n+/* DSPI1 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL192\t(MC_ME_BASE_ADDR + 0x00000183)\n+/* TSENS Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL206\t(MC_ME_BASE_ADDR + 0x0000018D)\n+/* CRC1 Peripheral Control Register\t\t\t*/\n+#define MC_ME_PCTL204\t(MC_ME_BASE_ADDR + 0x0000018F)\n+/* VIU1 Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL208\t(MC_ME_BASE_ADDR + 0x00000193)\n+/* JPEG Peripheral Control Register\t\t*/\n+#define MC_ME_PCTL212\t(MC_ME_BASE_ADDR + 0x00000197)\n+/* H264_DEC Peripheral Control Register\t*/\n+#define MC_ME_PCTL216\t(MC_ME_BASE_ADDR + 0x0000019B)\n+/* H264_ENC Peripheral Control Register\t*/\n+#define MC_ME_PCTL220\t(MC_ME_BASE_ADDR + 0x0000019F)\n+/* MBIST Peripheral Control Register\t*/\n+#define MC_ME_PCTL236\t(MC_ME_BASE_ADDR + 0x000001A9)\n+\n+/* Core status register */\n+#define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0)\n+\n+#endif\n+\n+#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */\ndiff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h\nnew file mode 100644\nindex 0000000..f39e81b\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h\n@@ -0,0 +1,31 @@\n+/*\n+ * (C) Copyright 2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__\n+#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__\n+\n+#define MC_RGM_DES\t\t\t(MC_RGM_BASE_ADDR)\n+#define MC_RGM_FES\t\t\t(MC_RGM_BASE_ADDR + 0x300)\n+#define MC_RGM_FERD\t\t\t(MC_RGM_BASE_ADDR + 0x310)\n+#define MC_RGM_FBRE\t\t\t(MC_RGM_BASE_ADDR + 0x330)\n+#define MC_RGM_FESS\t\t\t(MC_RGM_BASE_ADDR + 0x340)\n+#define MC_RGM_DDR_HE\t\t\t(MC_RGM_BASE_ADDR + 0x350)\n+#define MC_RGM_DDR_HS\t\t\t(MC_RGM_BASE_ADDR + 0x354)\n+#define MC_RGM_FRHE\t\t\t(MC_RGM_BASE_ADDR + 0x358)\n+#define MC_RGM_FREC\t\t\t(MC_RGM_BASE_ADDR + 0x600)\n+#define MC_RGM_FRET\t\t\t(MC_RGM_BASE_ADDR + 0x607)\n+#define MC_RGM_DRET\t\t\t(MC_RGM_BASE_ADDR + 0x60B)\n+\n+/* function reset sources mask */\n+#define F_SWT4\t\t\t\t0x8000\n+#define F_JTAG\t\t\t\t0x400\n+#define F_FCCU_SOFT\t\t\t0x40\n+#define F_FCCU_HARD\t\t\t0x20\n+#define F_SOFT_FUNC\t\t\t0x8\n+#define F_ST_DONE\t\t\t0x4\n+#define F_EXT_RST\t\t\t0x1\n+\n+#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */\ndiff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h\nnew file mode 100644\nindex 0000000..504aa68\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/mmdc.h\n@@ -0,0 +1,89 @@\n+/*\n+ * (C) Copyright 2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__\n+#define __ARCH_ARM_MACH_S32V234_MMDC_H__\n+\n+#define MMDC0\t\t\t\t0\n+#define MMDC1\t\t\t\t1\n+\n+#define MMDC_MDCTL\t\t\t0x0\n+#define MMDC_MDPDC\t\t\t0x4\n+#define MMDC_MDOTC\t\t\t0x8\n+#define MMDC_MDCFG0\t\t\t0xC\n+#define MMDC_MDCFG1\t\t\t0x10\n+#define MMDC_MDCFG2\t\t\t0x14\n+#define MMDC_MDMISC\t\t\t0x18\n+#define MMDC_MDSCR\t\t\t0x1C\n+#define MMDC_MDREF\t\t\t0x20\n+#define MMDC_MDRWD\t\t\t0x2C\n+#define MMDC_MDOR\t\t\t0x30\n+#define MMDC_MDMRR\t\t\t0x34\n+#define MMDC_MDCFG3LP\t\t0x38\n+#define MMDC_MDMR4\t\t\t0x3C\n+#define MMDC_MDASP\t\t\t0x40\n+#define MMDC_MAARCR\t\t\t0x400\n+#define MMDC_MAPSR\t\t\t0x404\n+#define MMDC_MAEXIDR0\t\t0x408\n+#define MMDC_MAEXIDR1\t\t0x40C\n+#define MMDC_MADPCR0\t\t0x410\n+#define MMDC_MADPCR1\t\t0x414\n+#define MMDC_MADPSR0\t\t0x418\n+#define MMDC_MADPSR1\t\t0x41C\n+#define MMDC_MADPSR2\t\t0x420\n+#define MMDC_MADPSR3\t\t0x424\n+#define MMDC_MADPSR4\t\t0x428\n+#define MMDC_MADPSR5\t\t0x42C\n+#define MMDC_MASBS0\t\t\t0x430\n+#define MMDC_MASBS1\t\t\t0x434\n+#define MMDC_MAGENP\t\t\t0x440\n+#define MMDC_MPZQHWCTRL\t\t0x800\n+#define MMDC_MPWLGCR\t\t0x808\n+#define MMDC_MPWLDECTRL0\t0x80C\n+#define MMDC_MPWLDECTRL1\t0x810\n+#define MMDC_MPWLDLST\t\t0x814\n+#define MMDC_MPODTCTRL\t\t0x818\n+#define MMDC_MPRDDQBY0DL\t0x81C\n+#define MMDC_MPRDDQBY1DL\t0x820\n+#define MMDC_MPRDDQBY2DL\t0x824\n+#define MMDC_MPRDDQBY3DL\t0x828\n+#define MMDC_MPDGCTRL0\t\t0x83C\n+#define MMDC_MPDGCTRL1\t\t0x840\n+#define MMDC_MPDGDLST0\t\t0x844\n+#define MMDC_MPRDDLCTL\t\t0x848\n+#define MMDC_MPRDDLST\t\t0x84C\n+#define MMDC_MPWRDLCTL\t\t0x850\n+#define MMDC_MPWRDLST\t\t0x854\n+#define MMDC_MPZQLP2CTL\t\t0x85C\n+#define MMDC_MPRDDLHWCTL\t0x860\n+#define MMDC_MPWRDLHWCTL\t0x864\n+#define MMDC_MPRDDLHWST0\t0x868\n+#define MMDC_MPRDDLHWST1\t0x86C\n+#define MMDC_MPWRDLHWST1\t0x870\n+#define MMDC_MPWRDLHWST2\t0x874\n+#define MMDC_MPWLHWERR\t\t0x878\n+#define MMDC_MPDGHWST0\t\t0x87C\n+#define MMDC_MPDGHWST1\t\t0x880\n+#define MMDC_MPDGHWST2\t\t0x884\n+#define MMDC_MPDGHWST3\t\t0x888\n+#define MMDC_MPPDCMPR1\t\t0x88C\n+#define MMDC_MPPDCMPR2\t\t0x890\n+#define MMDC_MPSWDAR0\t\t0x894\n+#define MMDC_MPSWDRDR0\t\t0x898\n+#define MMDC_MPSWDRDR1\t\t0x89C\n+#define MMDC_MPSWDRDR2\t\t0x8A0\n+#define MMDC_MPSWDRDR3\t\t0x8A4\n+#define MMDC_MPSWDRDR4\t\t0x8A8\n+#define MMDC_MPSWDRDR5\t\t0x8AC\n+#define MMDC_MPSWDRDR6\t\t0x8B0\n+#define MMDC_MPSWDRDR7\t\t0x8B4\n+#define MMDC_MPMUR0\t\t\t0x8B8\n+#define MMDC_MPDCCR\t\t\t0x8C0\n+\n+#define MMDC_MPMUR0_FRC_MSR\t\t\t(1 << 11)\n+#define MMDC_MPZQHWCTRL_ZQ_HW_FOR\t(1 << 16)\n+\n+#endif\ndiff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h\nnew file mode 100644\nindex 0000000..2e8c211\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-s32v234/siul.h\n@@ -0,0 +1,150 @@\n+/*\n+ * (C) Copyright 2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__\n+#define __ARCH_ARM_MACH_S32V234_SIUL_H__\n+\n+#include \"ddr.h\"\n+\n+#define SIUL2_MIDR1\t\t\t\t(SIUL2_BASE_ADDR + 0x00000004)\n+#define SIUL2_MIDR2\t\t\t\t(SIUL2_BASE_ADDR + 0x00000008)\n+#define SIUL2_DISR0\t\t\t\t(SIUL2_BASE_ADDR + 0x00000010)\n+#define SIUL2_DIRER0\t\t\t\t(SIUL2_BASE_ADDR + 0x00000018)\n+#define SIUL2_DIRSR0\t\t\t\t(SIUL2_BASE_ADDR + 0x00000020)\n+#define SIUL2_IREER0\t\t\t\t(SIUL2_BASE_ADDR + 0x00000028)\n+#define SIUL2_IFEER0\t\t\t\t(SIUL2_BASE_ADDR + 0x00000030)\n+#define SIUL2_IFER0\t\t\t\t(SIUL2_BASE_ADDR + 0x00000038)\n+\n+#define SIUL2_IFMCR_BASE\t\t\t(SIUL2_BASE_ADDR + 0x00000040)\n+#define SIUL2_IFMCRn(i)\t\t\t\t(SIUL2_IFMCR_BASE + 4 * (i))\n+\n+#define SIUL2_IFCPR\t\t\t\t(SIUL2_BASE_ADDR + 0x000000C0)\n+\n+/* SIUL2_MSCR specifications as stated in Reference Manual:\n+ * 0 - 359 Output Multiplexed Signal Configuration Registers\n+ * 512- 1023 Input Multiplexed Signal Configuration Registers */\n+#define SIUL2_MSCR_BASE\t\t\t\t(SIUL2_BASE_ADDR + 0x00000240)\n+#define SIUL2_MSCRn(i)\t\t\t\t(SIUL2_MSCR_BASE + 4 * (i))\n+\n+#define SIUL2_IMCR_BASE\t\t\t\t(SIUL2_BASE_ADDR + 0x00000A40)\n+#define SIUL2_IMCRn(i)\t\t\t\t(SIUL2_IMCR_BASE + 4 * (i))\n+\n+#define SIUL2_GPDO_BASE\t\t\t\t(SIUL2_BASE_ADDR + 0x00001300)\n+#define SIUL2_GPDOn(i)\t\t\t\t(SIUL2_GPDO_BASE + 4 * (i))\n+\n+#define SIUL2_GPDI_BASE\t\t\t\t(SIUL2_BASE_ADDR + 0x00001500)\n+#define SIUL2_GPDIn(i)\t\t\t\t(SIUL2_GPDI_BASE + 4 * (i))\n+\n+#define SIUL2_PGPDO_BASE\t\t\t(SIUL2_BASE_ADDR + 0x00001700)\n+#define SIUL2_PGPDOn(i)\t\t\t\t(SIUL2_PGPDO_BASE + 2 * (i))\n+\n+#define SIUL2_PGPDI_BASE\t\t\t(SIUL2_BASE_ADDR + 0x00001740)\n+#define SIUL2_PGPDIn(i)\t\t\t\t(SIUL2_PGPDI_BASE + 2 * (i))\n+\n+#define SIUL2_MPGPDO_BASE\t\t\t(SIUL2_BASE_ADDR + 0x00001780)\n+#define SIUL2_MPGPDOn(i)\t\t\t(SIUL2_MPGPDO_BASE + 4 * (i))\n+\n+/* SIUL2_MSCR masks */\n+#define SIUL2_MSCR_DDR_DO_TRIM(v)\t((v) & 0xC0000000)\n+#define SIUL2_MSCR_DDR_DO_TRIM_MIN\t(0 << 30)\n+#define SIUL2_MSCR_DDR_DO_TRIM_50PS\t(1 << 30)\n+#define SIUL2_MSCR_DDR_DO_TRIM_100PS\t(2 << 30)\n+#define SIUL2_MSCR_DDR_DO_TRIM_150PS\t(3 << 30)\n+\n+#define SIUL2_MSCR_DDR_INPUT(v)\t\t((v) & 0x20000000)\n+#define SIUL2_MSCR_DDR_INPUT_CMOS\t(0 << 29)\n+#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR\t(1 << 29)\n+\n+#define SIUL2_MSCR_DDR_SEL(v)\t\t((v) & 0x18000000)\n+#define SIUL2_MSCR_DDR_SEL_DDR3\t\t(0 << 27)\n+#define SIUL2_MSCR_DDR_SEL_LPDDR2\t(2 << 27)\n+\n+#define SIUL2_MSCR_DDR_ODT(v)\t\t((v) & 0x07000000)\n+#define SIUL2_MSCR_DDR_ODT_120ohm\t(1 << 24)\n+#define SIUL2_MSCR_DDR_ODT_60ohm\t(2 << 24)\n+#define SIUL2_MSCR_DDR_ODT_40ohm\t(3 << 24)\n+#define SIUL2_MSCR_DDR_ODT_30ohm\t(4 << 24)\n+#define SIUL2_MSCR_DDR_ODT_24ohm\t(5 << 24)\n+#define SIUL2_MSCR_DDR_ODT_20ohm\t(6 << 24)\n+#define SIUL2_MSCR_DDR_ODT_17ohm\t(7 << 24)\n+\n+#define SIUL2_MSCR_DCYCLE_TRIM(v)\t((v) & 0x00C00000)\n+#define SIUL2_MSCR_DCYCLE_TRIM_NONE\t(0 << 22)\n+#define SIUL2_MSCR_DCYCLE_TRIM_LEFT\t(1 << 22)\n+#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT\t(2 << 22)\n+\n+#define SIUL2_MSCR_OBE(v)\t\t((v) & 0x00200000)\n+#define SIUL2_MSCR_OBE_EN\t\t(1 << 21)\n+\n+#define SIUL2_MSCR_ODE(v)\t\t((v) & 0x00100000)\n+#define SIUL2_MSCR_ODE_EN\t\t(1 << 20)\n+\n+#define SIUL2_MSCR_IBE(v)\t\t((v) & 0x00010000)\n+#define SIUL2_MSCR_IBE_EN\t\t(1 << 19)\n+\n+#define SIUL2_MSCR_HYS(v)\t\t((v) & 0x00400000)\n+#define SIUL2_MSCR_HYS_EN\t\t(1 << 18)\n+\n+#define SIUL2_MSCR_INV(v)\t\t((v) & 0x00020000)\n+#define SIUL2_MSCR_INV_EN\t\t(1 << 17)\n+\n+#define SIUL2_MSCR_PKE(v)\t\t((v) & 0x00010000)\n+#define SIUL2_MSCR_PKE_EN\t\t(1 << 16)\n+\n+#define SIUL2_MSCR_SRE(v)\t\t((v) & 0x0000C000)\n+#define SIUL2_MSCR_SRE_SPEED_LOW_50\t(0 << 14)\n+#define SIUL2_MSCR_SRE_SPEED_LOW_100\t(1 << 14)\n+#define SIUL2_MSCR_SRE_SPEED_HIGH_100\t(2 << 14)\n+#define SIUL2_MSCR_SRE_SPEED_HIGH_200\t(3 << 14)\n+\n+#define SIUL2_MSCR_PUE(v)\t\t((v) & 0x00002000)\n+#define SIUL2_MSCR_PUE_EN\t\t(1 << 13)\n+\n+#define SIUL2_MSCR_PUS(v)\t\t((v) & 0x00001800)\n+#define SIUL2_MSCR_PUS_100K_DOWN\t(0 << 11)\n+#define SIUL2_MSCR_PUS_50K_DOWN\t\t(1 << 11)\n+#define SIUL2_MSCR_PUS_100K_UP\t\t(2 << 11)\n+#define SIUL2_MSCR_PUS_33K_UP\t\t(3 << 11)\n+\n+#define SIUL2_MSCR_DSE(v)\t\t((v) & 0x00000700)\n+#define SIUL2_MSCR_DSE_240ohm\t\t(1 << 8)\n+#define SIUL2_MSCR_DSE_120ohm\t\t(2 << 8)\n+#define SIUL2_MSCR_DSE_80ohm\t\t(3 << 8)\n+#define SIUL2_MSCR_DSE_60ohm\t\t(4 << 8)\n+#define SIUL2_MSCR_DSE_48ohm\t\t(5 << 8)\n+#define SIUL2_MSCR_DSE_40ohm\t\t(6 << 8)\n+#define SIUL2_MSCR_DSE_34ohm\t\t(7 << 8)\n+\n+#define SIUL2_MSCR_CRPOINT_TRIM(v)\t((v) & 0x000000C0)\n+#define SIUL2_MSCR_CRPOINT_TRIM_1\t(1 << 6)\n+\n+#define SIUL2_MSCR_SMC(v)\t\t((v) & 0x00000020)\n+#define SIUL2_MSCR_MUX_MODE(v)\t\t((v) & 0x0000000f)\n+#define SIUL2_MSCR_MUX_MODE_ALT1\t(0x1)\n+#define SIUL2_MSCR_MUX_MODE_ALT2\t(0x2)\n+#define SIUL2_MSCR_MUX_MODE_ALT3\t(0x3)\n+\n+/* UART settings */\n+#define SIUL2_UART0_TXD_PAD\t12\n+#define SIUL2_UART_TXD\t\t(SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm |\t\\\n+\t\t\t\tSIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)\n+\n+#define SIUL2_UART0_MSCR_RXD_PAD\t11\n+#define SIUL2_UART0_IMCR_RXD_PAD\t200\n+\n+#define SIUL2_UART_MSCR_RXD\t(SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)\n+#define SIUL2_UART_IMCR_RXD\t(SIUL2_MSCR_MUX_MODE_ALT2)\n+\n+/* uSDHC settings */\n+#define SIUL2_USDHC_PAD_CTRL_BASE\t(SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN |\t\\\n+\t\t\t\t\t\tSIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN |\t\t\\\n+\t\t\t\t\t\tSIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )\n+#define SIUL2_USDHC_PAD_CTRL_CMD\t(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)\n+#define SIUL2_USDHC_PAD_CTRL_CLK\t(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)\n+#define SIUL2_USDHC_PAD_CTRL_DAT0_3\t(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)\n+#define SIUL2_USDHC_PAD_CTRL_DAT4_7\t(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)\n+\n+#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */\ndiff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig\nnew file mode 100644\nindex 0000000..e71dfc4\n--- /dev/null\n+++ b/board/freescale/s32v234evb/Kconfig\n@@ -0,0 +1,23 @@\n+if TARGET_S32V234EVB\n+\n+config SYS_CPU\n+\tstring\n+\tdefault \"armv8\"\n+\n+config SYS_BOARD\n+\tstring\n+\tdefault \"s32v234evb\"\n+\n+config SYS_VENDOR\n+\tstring\n+\tdefault \"freescale\"\n+\n+config SYS_SOC\n+\tstring\n+\tdefault \"s32v234\"\n+\n+config SYS_CONFIG_NAME\n+\tstring\n+\tdefault \"s32v234evb\"\n+\n+endif\ndiff --git a/board/freescale/s32v234evb/MAINTAINERS b/board/freescale/s32v234evb/MAINTAINERS\nnew file mode 100644\nindex 0000000..62b2e1b\n--- /dev/null\n+++ b/board/freescale/s32v234evb/MAINTAINERS\n@@ -0,0 +1,8 @@\n+S32V234 Evaluation BOARD\n+M:\tEddy Petrișor <eddy.petrisor@gmail.com>\n+S:\tMaintained\n+F:\tarch/arm/cpu/armv8/s32v234/\n+F:\tarch/arm/include/asm/arch-s32v234/\n+F:\tboard/freescale/s32v234evb/\n+F:\tinclude/configs/s32v234evb.h\n+F:\tconfigs/s32v234evb_defconfig\ndiff --git a/board/freescale/s32v234evb/Makefile b/board/freescale/s32v234evb/Makefile\nnew file mode 100644\nindex 0000000..69e6d3e\n--- /dev/null\n+++ b/board/freescale/s32v234evb/Makefile\n@@ -0,0 +1,11 @@\n+#\n+# (C) Copyright 2013-2015, Freescale Semiconductor, Inc.\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y := clock.o\n+obj-y += lpddr2.o\n+obj-y += s32v234evb.o\n+\n+#########################################################################\ndiff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c\nnew file mode 100644\nindex 0000000..d218c21\n--- /dev/null\n+++ b/board/freescale/s32v234evb/clock.c\n@@ -0,0 +1,344 @@\n+/*\n+ * (C) Copyright 2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm/io.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/mc_cgm_regs.h>\n+#include <asm/arch/mc_me_regs.h>\n+#include <asm/arch/clock.h>\n+\n+/*\n+ * Select the clock reference for required pll.\n+ * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.\n+ * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)\n+ */\n+static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq)\n+{\n+\tu32 clk_src;\n+\tu32 pll_idx;\n+\tvolatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR;\n+\n+\t/* select the pll clock source */\n+\tswitch (refclk_freq) {\n+\tcase FIRC_CLK_FREQ:\n+\t\tclk_src = SRC_GPR1_FIRC_CLK_SOURCE;\n+\t\tbreak;\n+\tcase XOSC_CLK_FREQ:\n+\t\tclk_src = SRC_GPR1_XOSC_CLK_SOURCE;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* The clock frequency for the source clock is unknown */\n+\t\treturn -1;\n+\t}\n+\t/*\n+\t * The hardware definition is not uniform, it has to calculate again\n+\t * the recurrence formula.\n+\t */\n+\tswitch (pll) {\n+\tcase PERIPH_PLL:\n+\t\tpll_idx = 3;\n+\t\tbreak;\n+\tcase ENET_PLL:\n+\t\tpll_idx = 1;\n+\t\tbreak;\n+\tcase DDR_PLL:\n+\t\tpll_idx = 2;;\n+\t\tbreak;\n+\tdefault:\n+\t\tpll_idx = pll;\n+\t}\n+\n+\twritel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src),\n+\t &src->gpr1);\n+\n+\treturn 0;\n+}\n+\n+static void entry_to_target_mode(u32 mode)\n+{\n+\twritel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL);\n+\twritel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL);\n+\twhile ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ;\n+}\n+\n+/*\n+ * Program the pll according to the input parameters.\n+ * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.\n+ * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)\n+ * freq - expected output frequency for PHY0\n+ * freq1 - expected output frequency for PHY1\n+ * dfs_nr - number of DFS modules for current PLL\n+ * dfs - array with the activation dfs field, mfn and mfi\n+ * plldv_prediv - divider of clkfreq_ref\n+ * plldv_mfd - loop multiplication factor divider\n+ * pllfd_mfn - numerator loop multiplication factor divider\n+ * Please consult the PLLDIG chapter of platform manual\n+ * before to use this function.\n+ *)\n+ */\n+static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1,\n+\t\t u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv,\n+\t\t u32 plldv_mfd, u32 pllfd_mfn)\n+{\n+\tu32 i, rfdphi1, rfdphi, dfs_on = 0, fvco;\n+\n+\t/*\n+\t * This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter.\n+\t */\n+\tfvco =\n+\t (refclk_freq / plldv_prediv) * (plldv_mfd +\n+\t\t\t\t\t pllfd_mfn / (float)20480);\n+\n+\t/*\n+\t * VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult\n+\t * the platform DataSheet in order to determine the allowed values.\n+\t */\n+\n+\tif (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) {\n+\t\treturn -1;\n+\t}\n+\n+\tif (select_pll_source_clk(pll, refclk_freq) < 0) {\n+\t\treturn -1;\n+\t}\n+\n+\trfdphi = fvco / freq0;\n+\n+\trfdphi1 = (freq1 == 0) ? 0 : fvco / freq1;\n+\n+\twritel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) |\n+\t PLLDIG_PLLDV_RFDPHI_SET(rfdphi) |\n+\t PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) |\n+\t PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll));\n+\n+\twritel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) |\n+\t PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll));\n+\n+\t/* switch on the pll in current mode */\n+\twritel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll),\n+\t MC_ME_RUNn_MC(0));\n+\n+\tentry_to_target_mode(MC_ME_MCTL_RUN0);\n+\n+\t/* Only ARM_PLL, ENET_PLL and DDR_PLL */\n+\tif ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) {\n+\t\t/* DFS clk enable programming */\n+\t\twritel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll));\n+\n+\t\twritel(DFS_DLLPRG1_CPICTRL_SET(0x5) |\n+\t\t DFS_DLLPRG1_VSETTLCTRL_SET(0x1) |\n+\t\t DFS_DLLPRG1_CALBYPEN_SET(0x0) |\n+\t\t DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) |\n+\t\t DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll));\n+\n+\t\tfor (i = 0; i < dfs_nr; i++) {\n+\t\t\tif (dfs[i][0]) {\n+\t\t\t\twritel(DFS_DVPORTn_MFI_SET(dfs[i][2]) |\n+\t\t\t\t DFS_DVPORTn_MFN_SET(dfs[i][1]),\n+\t\t\t\t DFS_DVPORTn(pll, i));\n+\t\t\t\tdfs_on |= (dfs[i][0] << i);\n+\t\t\t}\n+\t\t}\n+\n+\t\twritel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET,\n+\t\t DFS_CTRL(pll));\n+\t\twritel(readl(DFS_PORTRESET(pll)) &\n+\t\t ~DFS_PORTRESET_PORTRESET_SET(dfs_on),\n+\t\t DFS_PORTRESET(pll));\n+\t\twhile ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ;\n+\t}\n+\n+\tentry_to_target_mode(MC_ME_MCTL_RUN0);\n+\n+\treturn 0;\n+\n+}\n+\n+static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source)\n+{\n+\t/* select the clock source */\n+\twritel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac));\n+}\n+\n+static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider)\n+{\n+\t/* set the divider */\n+\twritel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider),\n+\t CGM_ACn_DCm(cgm_addr, ac, dc));\n+}\n+\n+static void setup_sys_clocks(void)\n+{\n+\n+\t/* set ARM PLL DFS 1 as SYSCLK */\n+\twritel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) |\n+\t MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0));\n+\n+\tentry_to_target_mode(MC_ME_MCTL_RUN0);\n+\n+\t/* select sysclks ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */\n+\twritel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK\n+\t (0x2,\n+\t\tMC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) |\n+\t MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,\n+\t\t\t\t\t MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET)\n+\t | MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,\n+\t\t\t\t\t MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET),\n+\t MC_ME_RUNn_SEC_CC_I(0));\n+\n+\t/* setup the sys clock divider for CORE_CLK (1000MHz) */\n+\twritel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),\n+\t CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0));\n+\n+\t/* setup the sys clock divider for CORE2_CLK (500MHz) */\n+\twritel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),\n+\t CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1));\n+\t/* setup the sys clock divider for SYS3_CLK (266 MHz) */\n+\twritel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),\n+\t CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0));\n+\n+\t/* setup the sys clock divider for SYS6_CLK (133 Mhz) */\n+\twritel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),\n+\t CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1));\n+\n+\tentry_to_target_mode(MC_ME_MCTL_RUN0);\n+\n+}\n+\n+static void setup_aux_clocks(void)\n+{\n+\t/*\n+\t * setup the aux clock divider for PERI_CLK\n+\t * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz)\n+\t */\n+\taux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX);\n+\taux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4);\n+\n+\t/* setup the aux clock divider for LIN_CLK (40MHz) */\n+\taux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX);\n+\taux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1);\n+\n+\t/* setup the aux clock divider for ENET_TIME_CLK (50MHz) */\n+\taux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL);\n+\taux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9);\n+\n+\t/* setup the aux clock divider for ENET_CLK (50MHz) */\n+\taux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL);\n+\taux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9);\n+\n+\t/* setup the aux clock divider for SDHC_CLK (50 MHz). */\n+\taux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL);\n+\taux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9);\n+\n+\t/* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */\n+\taux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL);\n+\taux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0);\n+\t/* setup the aux clock divider for DDR4_CLK (133,25MHz) */\n+\taux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3);\n+\n+\tentry_to_target_mode(MC_ME_MCTL_RUN0);\n+\n+}\n+\n+static void enable_modules_clock(void)\n+{\n+\t/* PIT0 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58);\n+\t/* PIT1 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170);\n+\t/* LINFLEX0 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83);\n+\t/* LINFLEX1 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188);\n+\t/* ENET */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50);\n+\t/* SDHC */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93);\n+\t/* IIC0 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81);\n+\t/* IIC1 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184);\n+\t/* IIC2 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186);\n+\t/* MMDC0 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54);\n+\t/* MMDC1 */\n+\twriteb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162);\n+\n+\tentry_to_target_mode(MC_ME_MCTL_RUN0);\n+}\n+\n+void clock_init(void)\n+{\n+\tunsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {\n+\t\t{ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN,\n+\t\t ARM_PLL_PHI1_DFS1_MFI},\n+\t\t{ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN,\n+\t\t ARM_PLL_PHI1_DFS2_MFI},\n+\t\t{ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN,\n+\t\t ARM_PLL_PHI1_DFS3_MFI}\n+\t};\n+\n+\tunsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {\n+\t\t{ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN,\n+\t\t ENET_PLL_PHI1_DFS1_MFI},\n+\t\t{ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN,\n+\t\t ENET_PLL_PHI1_DFS2_MFI},\n+\t\t{ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN,\n+\t\t ENET_PLL_PHI1_DFS3_MFI},\n+\t\t{ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN,\n+\t\t ENET_PLL_PHI1_DFS4_MFI}\n+\t};\n+\n+\tunsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {\n+\t\t{DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN,\n+\t\t DDR_PLL_PHI1_DFS1_MFI},\n+\t\t{DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN,\n+\t\t DDR_PLL_PHI1_DFS2_MFI},\n+\t\t{DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN,\n+\t\t DDR_PLL_PHI1_DFS3_MFI}\n+\t};\n+\n+\twritel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 |\n+\t MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0));\n+\n+\t/* turn on FXOSC */\n+\twritel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON |\n+\t MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1),\n+\t MC_ME_RUNn_MC(0));\n+\n+\tentry_to_target_mode(MC_ME_MCTL_RUN0);\n+\n+\tprogram_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ,\n+\t\t ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs,\n+\t\t ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN);\n+\n+\tsetup_sys_clocks();\n+\n+\tprogram_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ,\n+\t\t PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL,\n+\t\t PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD,\n+\t\t PERIPH_PLL_PLLDV_MFN);\n+\n+\tprogram_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ,\n+\t\t ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs,\n+\t\t ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD,\n+\t\t ENET_PLL_PLLDV_MFN);\n+\n+\tprogram_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ,\n+\t\t DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs,\n+\t\t DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN);\n+\n+\tprogram_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ,\n+\t\t VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL,\n+\t\t VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD,\n+\t\t VIDEO_PLL_PLLDV_MFN);\n+\n+\tsetup_aux_clocks();\n+\n+\tenable_modules_clock();\n+\n+}\ndiff --git a/board/freescale/s32v234evb/lpddr2.c b/board/freescale/s32v234evb/lpddr2.c\nnew file mode 100644\nindex 0000000..ecc0842\n--- /dev/null\n+++ b/board/freescale/s32v234evb/lpddr2.c\n@@ -0,0 +1,137 @@\n+/*\n+ * (C) Copyright 2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm/io.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/siul.h>\n+#include <asm/arch/lpddr2.h>\n+#include <asm/arch/mmdc.h>\n+\n+volatile int mscr_offset_ck0;\n+\n+void lpddr2_config_iomux(uint8_t module)\n+{\n+\tint i;\n+\n+\tswitch (module) {\n+\tcase DDR0:\n+\t\tmscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);\n+\t\twritel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));\n+\n+\t\twritel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));\n+\t\twritel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));\n+\n+\t\twritel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));\n+\t\twritel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));\n+\n+\t\tfor (i = _DDR0_DM0; i <= _DDR0_DM3; i++)\n+\t\t\twritel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));\n+\n+\t\tfor (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)\n+\t\t\twritel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));\n+\n+\t\tfor (i = _DDR0_A0; i <= _DDR0_A9; i++)\n+\t\t\twritel(LPDDR2_An_PAD, SIUL2_MSCRn(i));\n+\n+\t\tfor (i = _DDR0_D0; i <= _DDR0_D31; i++)\n+\t\t\twritel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));\n+\t\tbreak;\n+\tcase DDR1:\n+\t\twritel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));\n+\n+\t\twritel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));\n+\t\twritel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));\n+\n+\t\twritel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));\n+\t\twritel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));\n+\n+\t\tfor (i = _DDR1_DM0; i <= _DDR1_DM3; i++)\n+\t\t\twritel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));\n+\n+\t\tfor (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)\n+\t\t\twritel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));\n+\n+\t\tfor (i = _DDR1_A0; i <= _DDR1_A9; i++)\n+\t\t\twritel(LPDDR2_An_PAD, SIUL2_MSCRn(i));\n+\n+\t\tfor (i = _DDR1_D0; i <= _DDR1_D31; i++)\n+\t\t\twritel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));\n+\t\tbreak;\n+\t}\n+}\n+\n+void config_mmdc(uint8_t module)\n+{\n+\tunsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;\n+\n+\twritel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);\n+\n+\twritel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);\n+\twritel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);\n+\twritel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);\n+\twritel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);\n+\twritel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);\n+\twritel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);\n+\twritel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);\n+\twritel(_MDCTL, mmdc_addr + MMDC_MDCTL);\n+\n+\twritel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);\n+\n+\twhile (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {\n+\t}\n+\n+\twritel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);\n+\n+\t/* Perform ZQ calibration */\n+\twritel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);\n+\twritel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);\n+\twhile (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {\n+\t}\n+\n+\t/* Enable MMDC with CS0 */\n+\twritel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);\n+\n+\t/* Complete the initialization sequence as defined by JEDEC */\n+\twritel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);\n+\twritel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);\n+\twritel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);\n+\twritel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);\n+\n+\t/* Set the amount of DRAM */\n+\t/* Set DQS settings based on board type */\n+\n+\tswitch (module) {\n+\tcase MMDC0:\n+\t\twritel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);\n+\t\twritel(MMDC_MPRDDLCTL_MODULE0_VALUE,\n+\t\t mmdc_addr + MMDC_MPRDDLCTL);\n+\t\twritel(MMDC_MPWRDLCTL_MODULE0_VALUE,\n+\t\t mmdc_addr + MMDC_MPWRDLCTL);\n+\t\twritel(MMDC_MPDGCTRL0_MODULE0_VALUE,\n+\t\t mmdc_addr + MMDC_MPDGCTRL0);\n+\t\twritel(MMDC_MPDGCTRL1_MODULE0_VALUE,\n+\t\t mmdc_addr + MMDC_MPDGCTRL1);\n+\t\tbreak;\n+\tcase MMDC1:\n+\t\twritel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);\n+\t\twritel(MMDC_MPRDDLCTL_MODULE1_VALUE,\n+\t\t mmdc_addr + MMDC_MPRDDLCTL);\n+\t\twritel(MMDC_MPWRDLCTL_MODULE1_VALUE,\n+\t\t mmdc_addr + MMDC_MPWRDLCTL);\n+\t\twritel(MMDC_MPDGCTRL0_MODULE1_VALUE,\n+\t\t mmdc_addr + MMDC_MPDGCTRL0);\n+\t\twritel(MMDC_MPDGCTRL1_MODULE1_VALUE,\n+\t\t mmdc_addr + MMDC_MPDGCTRL1);\n+\t\tbreak;\n+\t}\n+\n+\twritel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);\n+\twritel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);\n+\twritel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);\n+\twritel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);\n+\twritel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);\n+\n+}\ndiff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c\nnew file mode 100644\nindex 0000000..3100f09\n--- /dev/null\n+++ b/board/freescale/s32v234evb/s32v234evb.c\n@@ -0,0 +1,183 @@\n+/*\n+ * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/siul.h>\n+#include <asm/arch/lpddr2.h>\n+#include <asm/arch/clock.h>\n+#include <mmc.h>\n+#include <fsl_esdhc.h>\n+#include <miiphy.h>\n+#include <netdev.h>\n+#include <i2c.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+void setup_iomux_ddr(void)\n+{\n+\tlpddr2_config_iomux(DDR0);\n+\tlpddr2_config_iomux(DDR1);\n+\n+}\n+\n+void ddr_phy_init(void)\n+{\n+}\n+\n+void ddr_ctrl_init(void)\n+{\n+\tconfig_mmdc(0);\n+\tconfig_mmdc(1);\n+}\n+\n+int dram_init(void)\n+{\n+\tsetup_iomux_ddr();\n+\n+\tddr_ctrl_init();\n+\n+\tgd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);\n+\n+\treturn 0;\n+}\n+\n+static void setup_iomux_uart(void)\n+{\n+\t/* Muxing for linflex */\n+\t/* Replace the magic values after bringup */\n+\n+\t/* set TXD - MSCR[12] PA12 */\n+\twritel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));\n+\n+\t/* set RXD - MSCR[11] - PA11 */\n+\twritel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));\n+\n+\t/* set RXD - IMCR[200] - 200 */\n+\twritel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));\n+}\n+\n+static void setup_iomux_enet(void)\n+{\n+}\n+\n+static void setup_iomux_i2c(void)\n+{\n+}\n+\n+#ifdef CONFIG_SYS_USE_NAND\n+void setup_iomux_nfc(void)\n+{\n+}\n+#endif\n+\n+#ifdef CONFIG_FSL_ESDHC\n+struct fsl_esdhc_cfg esdhc_cfg[1] = {\n+\t{USDHC_BASE_ADDR},\n+};\n+\n+int board_mmc_getcd(struct mmc *mmc)\n+{\n+\t/* eSDHC1 is always present */\n+\treturn 1;\n+}\n+\n+int board_mmc_init(bd_t * bis)\n+{\n+\tesdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);\n+\n+\t/* Set iomux PADS for USDHC */\n+\n+\t/* PK6 pad: uSDHC clk */\n+\twritel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));\n+\twritel(0x3, SIUL2_MSCRn(902));\n+\n+\t/* PK7 pad: uSDHC CMD */\n+\twritel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));\n+\twritel(0x3, SIUL2_MSCRn(901));\n+\n+\t/* PK8 pad: uSDHC DAT0 */\n+\twritel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));\n+\twritel(0x3, SIUL2_MSCRn(903));\n+\n+\t/* PK9 pad: uSDHC DAT1 */\n+\twritel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));\n+\twritel(0x3, SIUL2_MSCRn(904));\n+\n+\t/* PK10 pad: uSDHC DAT2 */\n+\twritel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));\n+\twritel(0x3, SIUL2_MSCRn(905));\n+\n+\t/* PK11 pad: uSDHC DAT3 */\n+\twritel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));\n+\twritel(0x3, SIUL2_MSCRn(906));\n+\n+\t/* PK15 pad: uSDHC DAT4 */\n+\twritel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));\n+\twritel(0x3, SIUL2_MSCRn(907));\n+\n+\t/* PL0 pad: uSDHC DAT5 */\n+\twritel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));\n+\twritel(0x3, SIUL2_MSCRn(908));\n+\n+\t/* PL1 pad: uSDHC DAT6 */\n+\twritel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));\n+\twritel(0x3, SIUL2_MSCRn(909));\n+\n+\t/* PL2 pad: uSDHC DAT7 */\n+\twritel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));\n+\twritel(0x3, SIUL2_MSCRn(910));\n+\n+\treturn fsl_esdhc_initialize(bis, &esdhc_cfg[0]);\n+}\n+#endif\n+\n+static void mscm_init(void)\n+{\n+\tstruct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;\n+\tint i;\n+\n+\tfor (i = 0; i < MSCM_IRSPRC_NUM; i++)\n+\t\twritew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);\n+}\n+\n+int board_phy_config(struct phy_device *phydev)\n+{\n+\tif (phydev->drv->config)\n+\t\tphydev->drv->config(phydev);\n+\n+\treturn 0;\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tclock_init();\n+\tmscm_init();\n+\n+\tsetup_iomux_uart();\n+\tsetup_iomux_enet();\n+\tsetup_iomux_i2c();\n+#ifdef CONFIG_SYS_USE_NAND\n+\tsetup_iomux_nfc();\n+#endif\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\t/* address of boot parameters */\n+\tgd->bd->bi_boot_params = PHYS_SDRAM + 0x100;\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: s32v234evb\\n\");\n+\n+\treturn 0;\n+}\ndiff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg\nnew file mode 100644\nindex 0000000..6017a40\n--- /dev/null\n+++ b/board/freescale/s32v234evb/s32v234evb.cfg\n@@ -0,0 +1,29 @@\n+/*\n+ * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/*\n+ * Refer docs/README.imxmage for more details about how-to configure\n+ * and create imximage boot image\n+ *\n+ * The syntax is taken as close as possible with the kwbimage\n+ */\n+#include <asm/imx-common/imximage.cfg>\n+\n+/* image version */\n+IMAGE_VERSION\t2\n+BOOT_FROM sd\n+\n+\n+/*\n+ * Boot Device : one of qspi, sd:\n+ * qspi: flash_offset: 0x1000\n+ * sd/mmc: flash_offset: 0x1000\n+ */\n+\n+\n+#ifdef CONFIG_SECURE_BOOT\n+SECURE_BOOT\n+#endif\ndiff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig\nnew file mode 100644\nindex 0000000..847de63\n--- /dev/null\n+++ b/configs/s32v234evb_defconfig\n@@ -0,0 +1,6 @@\n+CONFIG_ARM=y\n+CONFIG_TARGET_S32V234EVB=y\n+CONFIG_SYS_MALLOC_F=y\n+CONFIG_SYS_EXTRA_OPTIONS=\"IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg\"\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_OF_LIBFDT=y\ndiff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c\nindex 3acf9e8..6e878cb 100644\n--- a/drivers/mmc/fsl_esdhc.c\n+++ b/drivers/mmc/fsl_esdhc.c\n@@ -208,7 +208,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)\n \tint timeout;\n \tstruct fsl_esdhc_priv *priv = mmc->priv;\n \tstruct fsl_esdhc *regs = priv->esdhc_regs;\n-#ifdef CONFIG_FSL_LAYERSCAPE\n+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)\n \tdma_addr_t addr;\n #endif\n \tuint wml_value;\n@@ -221,7 +221,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)\n \n \t\tesdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);\n #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO\n-#ifdef CONFIG_FSL_LAYERSCAPE\n+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)\n \t\taddr = virt_to_phys((void *)(data->dest));\n \t\tif (upper_32_bits(addr))\n \t\t\tprintf(\"Error found for upper 32 bits\\n\");\n@@ -247,7 +247,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)\n \t\tesdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,\n \t\t\t\t\twml_value << 16);\n #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO\n-#ifdef CONFIG_FSL_LAYERSCAPE\n+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)\n \t\taddr = virt_to_phys((void *)(data->src));\n \t\tif (upper_32_bits(addr))\n \t\t\tprintf(\"Error found for upper 32 bits\\n\");\n@@ -308,7 +308,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)\n static void check_and_invalidate_dcache_range\n \t(struct mmc_cmd *cmd,\n \t struct mmc_data *data) {\n-#ifdef CONFIG_FSL_LAYERSCAPE\n+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)\n \tunsigned start = 0;\n #else\n \tunsigned start = (unsigned)data->dest ;\n@@ -316,7 +316,7 @@ static void check_and_invalidate_dcache_range\n \tunsigned size = roundup(ARCH_DMA_MINALIGN,\n \t\t\t\tdata->blocks*data->blocksize);\n \tunsigned end = start+size ;\n-#ifdef CONFIG_FSL_LAYERSCAPE\n+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)\n \tdma_addr_t addr;\n \n \taddr = virt_to_phys((void *)(data->dest));\ndiff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h\nnew file mode 100644\nindex 0000000..9723bab\n--- /dev/null\n+++ b/include/configs/s32v234evb.h\n@@ -0,0 +1,260 @@\n+/*\n+ * (C) Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ *\n+ * Configuration settings for the Freescale S32V234 EVB board.\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#ifndef CONFIG_SPL_BUILD\n+#include <config_distro_defaults.h>\n+#endif\n+\n+#include <asm/arch/imx-regs.h>\n+\n+#define CONFIG_S32V234\n+#define CONFIG_DM\n+\n+#define CONFIG_DISPLAY_CPUINFO\n+#define CONFIG_DISPLAY_BOARDINFO\n+\n+/* Config GIC */\n+#define CONFIG_GICV2\n+#define GICD_BASE 0x7D001000\n+#define GICC_BASE 0x7D002000\n+\n+#define CONFIG_REMAKE_ELF\n+#undef CONFIG_RUN_FROM_IRAM_ONLY\n+\n+#define CONFIG_RUN_FROM_DDR1\n+#undef CONFIG_RUN_FROM_DDR0\n+\n+/* Run by default from DDR1 */\n+#ifdef CONFIG_RUN_FROM_DDR0\n+#define DDR_BASE_ADDR\t\t0x80000000\n+#else\n+#define DDR_BASE_ADDR\t\t0xC0000000\n+#endif\n+\n+#define CONFIG_MACH_TYPE\t\t4146\n+\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+\n+/* Config CACHE */\n+#define CONFIG_CMD_CACHE\n+\n+#define CONFIG_SYS_FULL_VA\n+\n+/* Enable passing of ATAGs */\n+#define CONFIG_CMDLINE_TAG\n+\n+/* SMP Spin Table Definitions */\n+#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)\n+\n+/* Generic Timer Definitions */\n+#define COUNTER_FREQUENCY (1000000000)\t/* 1000MHz */\n+#define CONFIG_SYS_FSL_ERRATUM_A008585\n+\n+/* Size of malloc() pool */\n+#ifdef CONFIG_RUN_FROM_IRAM_ONLY\n+#define CONFIG_SYS_MALLOC_LEN\t\t(CONFIG_ENV_SIZE + 1 * 1024 * 1024)\n+#else\n+#define CONFIG_SYS_MALLOC_LEN\t\t(CONFIG_ENV_SIZE + 2 * 1024 * 1024)\n+#endif\n+#define CONFIG_BOARD_EARLY_INIT_F\n+\n+#define CONFIG_DM_SERIAL\n+#define CONFIG_FSL_LINFLEXUART\n+#define LINFLEXUART_BASE\t\tLINFLEXD0_BASE_ADDR\n+\n+#define CONFIG_DEBUG_UART_LINFLEXUART\n+#define CONFIG_DEBUG_UART_BASE\t\tLINFLEXUART_BASE\n+\n+/* Allow to overwrite serial and ethaddr */\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_SYS_UART_PORT\t\t(1)\n+#define CONFIG_BAUDRATE\t\t\t\t115200\n+\n+#undef CONFIG_CMD_IMLS\n+\n+#define CONFIG_MMC\n+#define CONFIG_FSL_ESDHC\n+#define CONFIG_FSL_USDHC\n+#define CONFIG_SYS_FSL_ESDHC_ADDR\tUSDHC_BASE_ADDR\n+#define CONFIG_SYS_FSL_ESDHC_NUM\t1\n+\n+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111\n+\n+#define CONFIG_CMD_MMC\n+#define CONFIG_GENERIC_MMC\n+/* #define CONFIG_CMD_EXT2 EXT2 Support */\n+#define CONFIG_CMD_FAT\t\t/* FAT support */\n+#define CONFIG_DOS_PARTITION\n+\n+#if 0\n+\n+/* Ethernet config */\n+#define CONFIG_CMD_PING\n+#define CONFIG_CMD_DHCP\n+#define CONFIG_CMD_MII\n+#define CONFIG_FEC_MXC\n+#define CONFIG_MII\n+#define IMX_FEC_BASE ENET_BASE_ADDR\n+#define CONFIG_FEC_XCV_TYPE RMII\n+#define CONFIG_FEC_MXC_PHYADDR 0\n+#define CONFIG_PHYLIB\n+#define CONFIG_PHY_MICREL\n+#endif\n+\n+#if 0\t\t\t\t/* Disable until the I2C driver will be updated */\n+\n+/* I2C Configs */\n+#define CONFIG_CMD_I2C\n+#define CONFIG_HARD_I2C\n+#define CONFIG_I2C_MXC\n+#define CONFIG_SYS_I2C_BASE\t\tI2C0_BASE_ADDR\n+#define CONFIG_SYS_I2C_SPEED\t\t100000\n+#endif\n+\n+#if 0\t\t\t\t/* Disable until the FLASH will be implemented */\n+#define CONFIG_SYS_USE_NAND\n+#endif\n+\n+#ifdef CONFIG_SYS_USE_NAND\n+/* Nand Flash Configs */\n+#define\tCONFIG_CMD_NAND\n+#define CONFIG_JFFS2_NAND\n+#define MTD_NAND_FSL_NFC_SWECC 1\n+#define CONFIG_NAND_FSL_NFC\n+#define CONFIG_SYS_NAND_BASE\t\t0x400E0000\n+#define CONFIG_SYS_MAX_NAND_DEVICE\t1\n+#define NAND_MAX_CHIPS\t\t\tCONFIG_SYS_MAX_NAND_DEVICE\n+#define CONFIG_SYS_NAND_SELECT_DEVICE\n+#define CONFIG_SYS_64BIT_VSPRINTF\t/* needed for nand_util.c */\n+#endif\n+\n+#define CONFIG_CMD_DHCP\n+\n+#define CONFIG_LOADADDR\t\t\t0xC307FFC0\n+#define CONFIG_BOOTARGS\t\t\t\"console=ttyLF0 root=/dev/ram rw\"\n+\n+#define CONFIG_CMD_ENV\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"boot_scripts=boot.scr.uimg boot.scr\\0\" \\\n+\t\"scriptaddr=\" __stringify(CONFIG_LOADADDR) \"\\0\" \\\n+\t\"console=ttyLF0,115200\\0\" \\\n+\t\"fdt_file=s32v234-evb.dtb\\0\" \\\n+\t\"fdt_high=0xffffffff\\0\" \\\n+\t\"initrd_high=0xffffffff\\0\" \\\n+\t\"fdt_addr_r=0xC2000000\\0\" \\\n+\t\"kernel_addr_r=0xC307FFC0\\0\" \\\n+\t\"ramdisk_addr_r=0xC4000000\\0\" \\\n+\t\"ramdisk=rootfs.uimg\\0\"\\\n+\t\"ip_dyn=yes\\0\" \\\n+\t\"mmcdev=\" __stringify(CONFIG_SYS_MMC_ENV_DEV) \"\\0\" \\\n+\t\"update_sd_firmware_filename=u-boot.imx\\0\" \\\n+\t\"update_sd_firmware=\" \\\n+\t\t\"if test ${ip_dyn} = yes; then \" \\\n+\t\t\t\"setenv get_cmd dhcp; \" \\\n+\t\t\"else \" \\\n+\t\t\t\"setenv get_cmd tftp; \" \\\n+\t\t\"fi; \" \\\n+\t\t\"if mmc dev ${mmcdev}; then \"\t\\\n+\t\t\t\"if ${get_cmd} ${update_sd_firmware_filename}; then \" \\\n+\t\t\t\t\"setexpr fw_sz ${filesize} / 0x200; \" \\\n+\t\t\t\t\"setexpr fw_sz ${fw_sz} + 1; \"\t\\\n+\t\t\t\t\"mmc write ${loadaddr} 0x2 ${fw_sz}; \" \\\n+\t\t\t\"fi; \"\t\\\n+\t\t\"fi\\0\" \\\n+\t\"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\\0\" \\\n+\t\"jtagboot=echo Booting using jtag...; \" \\\n+\t\t\"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\\0\" \\\n+\t\"jtagsdboot=echo Booting loading Linux with ramdisk from SD...; \" \\\n+\t\t\"run loaduimage; run loadramdisk; run loadfdt;\"\\\n+\t\t\"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\\0\" \\\n+\t\"boot_net_usb_start=true\\0\" \\\n+\tBOOTENV\n+\n+#define BOOT_TARGET_DEVICES(func) \\\n+\tfunc(MMC, mmc, 1) \\\n+\tfunc(MMC, mmc, 0) \\\n+\tfunc(DHCP, dhcp, na)\n+\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"run distro_bootcmd\"\n+\n+#include <config_distro_bootcmd.h>\n+\n+/* Miscellaneous configurable options */\n+#define CONFIG_SYS_LONGHELP\t/* undef to save memory */\n+#define CONFIG_SYS_HUSH_PARSER\t/* use \"hush\" command parser */\n+#define CONFIG_SYS_PROMPT_HUSH_PS2\t\"> \"\n+#define CONFIG_SYS_PROMPT\t\t\"=> \"\n+#undef CONFIG_AUTO_COMPLETE\n+#define CONFIG_SYS_CBSIZE\t\t256\t/* Console I/O Buffer Size */\n+#define CONFIG_SYS_PBSIZE\t\t\\\n+\t\t\t(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)\n+#define CONFIG_SYS_MAXARGS\t\t16\t/* max number of command args */\n+#define CONFIG_SYS_BARGSIZE\t\tCONFIG_SYS_CBSIZE\n+#define CONFIG_CMDLINE_EDITING\n+\n+#define CONFIG_CMD_MEMTEST\n+#define CONFIG_SYS_MEMTEST_START\t(DDR_BASE_ADDR)\n+#define CONFIG_SYS_MEMTEST_END\t\t(DDR_BASE_ADDR + 0x7C00000)\n+\n+#define CONFIG_SYS_LOAD_ADDR\t\tCONFIG_LOADADDR\n+#define CONFIG_SYS_HZ\t\t\t\t1000\n+\n+#define CONFIG_SYS_TEXT_BASE\t\t0x3E800000\t/* SDRAM */\n+\n+#ifdef CONFIG_RUN_FROM_IRAM_ONLY\n+#define CONFIG_SYS_MALLOC_BASE\t\t(DDR_BASE_ADDR)\n+#endif\n+\n+/*\n+ * Stack sizes\n+ * The stack sizes are set up in start.S using the settings below\n+ */\n+#define CONFIG_STACKSIZE\t\t(128 * 1024)\t/* regular stack */\n+\n+#if 0\n+/* Configure PXE */\n+#define CONFIG_CMD_PXE\n+#define CONFIG_BOOTP_PXE\n+#define CONFIG_BOOTP_PXE_CLIENTARCH\t0x100\n+#endif\n+\n+/* Physical memory map */\n+/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */\n+#define CONFIG_NR_DRAM_BANKS\t\t1\n+#define PHYS_SDRAM\t\t\t(DDR_BASE_ADDR)\n+#define PHYS_SDRAM_SIZE\t\t\t(256 * 1024 * 1024)\n+\n+#define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM\n+#define CONFIG_SYS_INIT_RAM_ADDR\tIRAM_BASE_ADDR\n+#define CONFIG_SYS_INIT_RAM_SIZE\tIRAM_SIZE\n+\n+#define CONFIG_SYS_INIT_SP_OFFSET \\\n+\t(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)\n+#define CONFIG_SYS_INIT_SP_ADDR \\\n+\t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n+\n+/* FLASH and environment organization */\n+#define CONFIG_SYS_NO_FLASH\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_ENV_IS_IN_MMC\n+\n+#define CONFIG_ENV_OFFSET\t\t(12 * 64 * 1024)\n+#define CONFIG_SYS_MMC_ENV_DEV\t\t0\n+\n+\n+#define CONFIG_BOOTP_BOOTFILESIZE\n+#define CONFIG_BOOTP_BOOTPATH\n+#define CONFIG_BOOTP_GATEWAY\n+#define CONFIG_BOOTP_HOSTNAME\n+\n+#endif\n", "prefixes": [ "U-Boot", "v4", "2/2" ] }