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GET /api/patches/626880/?format=api
{ "id": 626880, "url": "http://patchwork.ozlabs.org/api/patches/626880/?format=api", "web_url": "http://patchwork.ozlabs.org/project/lede/patch/1464296907-28020-9-git-send-email-dev@kresin.me/", "project": { "id": 54, "url": "http://patchwork.ozlabs.org/api/projects/54/?format=api", "name": "LEDE development", "link_name": "lede", "list_id": "lede-dev.lists.infradead.org", "list_email": "lede-dev@lists.infradead.org", "web_url": "http://lede-project.org/", "scm_url": "", "webscm_url": "http://git.lede-project.org/", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1464296907-28020-9-git-send-email-dev@kresin.me>", "list_archive_url": null, "date": "2016-05-26T21:08:27", "name": "[LEDE-DEV,9/9] uboot-lantiq: Add Arcadyan VGV7519 support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "16a319492a77009d4e8eb527d354a3dcde38a950", "submitter": { "id": 69023, "url": "http://patchwork.ozlabs.org/api/people/69023/?format=api", "name": "Mathias Kresin", "email": "dev@kresin.me" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/lede/patch/1464296907-28020-9-git-send-email-dev@kresin.me/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/626880/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/626880/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<lede-dev-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3rG1wq4lV3z9t44\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 27 May 2016 07:09:15 +1000 (AEST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1b62Wl-0001hf-SG; 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\n\tThu, 26 May 2016 14:08:40 -0700 (PDT)", "From": "Mathias Kresin <dev@kresin.me>", "To": "lede-dev@lists.infradead.org", "Date": "Thu, 26 May 2016 23:08:27 +0200", "Message-Id": "<1464296907-28020-9-git-send-email-dev@kresin.me>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1464296870-27976-1-git-send-email-dev@kresin.me>", "References": "<1464296870-27976-1-git-send-email-dev@kresin.me>", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20160526_140858_486713_11EFE7A8 ", "X-CRM114-Status": "GOOD ( 16.19 )", "X-Spam-Score": "-2.6 (--)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:400c:c09:0:0:0:243 listed in] [list.dnswl.org]\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid", "Subject": "[LEDE-DEV] [PATCH 9/9] uboot-lantiq: Add Arcadyan VGV7519 support", "X-BeenThere": "lede-dev@lists.infradead.org", "X-Mailman-Version": "2.1.20", "Precedence": "list", "List-Id": "<lede-dev.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/lede-dev>,\n\t<mailto:lede-dev-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/lede-dev/>", "List-Post": "<mailto:lede-dev@lists.infradead.org>", "List-Help": "<mailto:lede-dev-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/lede-dev>,\n\t<mailto:lede-dev-request@lists.infradead.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"Lede-dev\" <lede-dev-bounces@lists.infradead.org>", "Errors-To": "lede-dev-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Based on a submission to the uboot-lantiq repo by Eddi De Pieri.\n\nMajor cleanup and addition of brnboot second stage u-boot was done by\nme.\n\nThe second stage brnboot u-boot is untested, since the brnboot prompt\nis secured by a still unknown password. But should work.\n\nThe former ram values are replaced with the ram values extracted from\nthe original brnboot. The old ones didn't worked with the ramboot\nimage.\n\nSigned-off-by: Mathias Kresin <dev@kresin.me>\n---\n package/boot/uboot-lantiq/Makefile | 22 +-\n ...PS-add-board-support-for-Arcadyan-VGV7519.patch | 288 +++++++++++++++++++++\n 2 files changed, 309 insertions(+), 1 deletion(-)\n create mode 100644 package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch", "diff": "diff --git a/package/boot/uboot-lantiq/Makefile b/package/boot/uboot-lantiq/Makefile\nindex 5b61f14..1f66d6e 100644\n--- a/package/boot/uboot-lantiq/Makefile\n+++ b/package/boot/uboot-lantiq/Makefile\n@@ -295,6 +295,25 @@ define uboot/vgv7510kw22_ram\n DEPS:=@TARGET_lantiq_xrx200_VGV7510KW22NOR||@TARGET_lantiq_xrx200_VGV7510KW22BRN\n endef\n \n+define uboot/vgv7519_brn\n+ TITLE:=U-Boot for Arcadyan VGV7519 (BRN)\n+ SOC:=vr9\n+ DEPS:=@TARGET_lantiq_xrx200_VGV7519NOR||@TARGET_lantiq_xrx200_VGV7519BRN\n+endef\n+\n+define uboot/vgv7519_nor\n+ TITLE:=U-Boot for Arcadyan VGV7519 (NOR)\n+ SOC:=vr9\n+ DEPS:=@TARGET_lantiq_xrx200_VGV7519NOR||@TARGET_lantiq_xrx200_VGV7519BRN\n+endef\n+\n+define uboot/vgv7519_ram\n+ TITLE:=U-Boot for Arcadyan VGV7519 (RAM)\n+ SOC:=vr9\n+ DDR_SETTINGS:=board/arcadyan/vgv7519/ddr_settings.h\n+ DEPS:=@TARGET_lantiq_xrx200_VGV7519NOR||@TARGET_lantiq_xrx200_VGV7519BRN\n+endef\n+\n UBOOTS:= \\\n \tarv4519pw_ram arv4519pw_nor arv4519pw_brn \\\n \tarv7510pw_ram arv7510pw_nor arv7510pw_brn \\\n@@ -309,7 +328,8 @@ UBOOTS:= \\\n \teasy80920_ram easy80920_nor easy80920_norspl easy80920_sfspl \\\n \tfb3370_eva fb3370_ram fb3370_sfspl \\\n \tp2812hnufx_ram p2812hnufx_nandspl \\\n-\tvgv7510kw22_brn vgv7510kw22_nor vgv7510kw22_ram\n+\tvgv7510kw22_brn vgv7510kw22_nor vgv7510kw22_ram \\\n+\tvgv7519_brn vgv7519_nor vgv7519_ram\n \n define Package/uboot/template\n define Package/uboot-lantiq-$(1)\ndiff --git a/package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch b/package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch\nnew file mode 100644\nindex 0000000..952bdce\n--- /dev/null\n+++ b/package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch\n@@ -0,0 +1,288 @@\n+--- /dev/null\n++++ b/board/arcadyan/vgv7519/Makefile\n+@@ -0,0 +1,27 @@\n++#\n++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n++#\n++# SPDX-License-Identifier:\tGPL-2.0+\n++#\n++\n++include $(TOPDIR)/config.mk\n++\n++LIB\t= $(obj)lib$(BOARD).o\n++\n++COBJS\t= $(BOARD).o\n++\n++SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n++OBJS\t:= $(addprefix $(obj),$(COBJS))\n++SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n++\n++$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n++\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n++\n++#########################################################################\n++\n++# defines $(obj).depend target\n++include $(SRCTREE)/rules.mk\n++\n++sinclude $(obj).depend\n++\n++#########################################################################\n+--- /dev/null\n++++ b/board/arcadyan/vgv7519/config.mk\n+@@ -0,0 +1,7 @@\n++#\n++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n++#\n++# SPDX-License-Identifier:\tGPL-2.0+\n++#\n++\n++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n+--- /dev/null\n++++ b/board/arcadyan/vgv7519/ddr_settings.h\n+@@ -0,0 +1,70 @@\n++/*\n++ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>\n++ *\n++ * The values have been extracted from original brnboot.\n++ *\n++ * SPDX-License-Identifier:\tGPL-2.0+\n++ */\n++\n++#define\tMC_CCR00_VALUE\t0x101\n++#define\tMC_CCR01_VALUE\t0x1000100\n++#define\tMC_CCR02_VALUE\t0x1010000\n++#define\tMC_CCR03_VALUE\t0x100\n++#define\tMC_CCR04_VALUE\t0x1000000\n++#define\tMC_CCR05_VALUE\t0x1000101\n++#define\tMC_CCR06_VALUE\t0x1000100\n++#define\tMC_CCR07_VALUE\t0x1010000\n++#define\tMC_CCR08_VALUE\t0x1000101\n++#define\tMC_CCR09_VALUE\t0x0\n++#define\tMC_CCR10_VALUE\t0x2000100\n++#define\tMC_CCR11_VALUE\t0x2000401\n++#define\tMC_CCR12_VALUE\t0x30000\n++#define\tMC_CCR13_VALUE\t0x202\n++#define\tMC_CCR14_VALUE\t0x7080A0F\n++#define\tMC_CCR15_VALUE\t0x2040F\n++#define\tMC_CCR16_VALUE\t0x40000\n++#define\tMC_CCR17_VALUE\t0x70102\n++#define\tMC_CCR18_VALUE\t0x4020002\n++#define\tMC_CCR19_VALUE\t0x30302\n++#define\tMC_CCR20_VALUE\t0x8000700\n++#define\tMC_CCR21_VALUE\t0x40F020A\n++#define\tMC_CCR22_VALUE\t0x0\n++#define\tMC_CCR23_VALUE\t0xC020000\n++#define\tMC_CCR24_VALUE\t0x4401B04\n++#define\tMC_CCR25_VALUE\t0x0\n++#define\tMC_CCR26_VALUE\t0x0\n++#define\tMC_CCR27_VALUE\t0x6420000\n++#define\tMC_CCR28_VALUE\t0x0\n++#define\tMC_CCR29_VALUE\t0x0\n++#define\tMC_CCR30_VALUE\t0x798\n++#define\tMC_CCR31_VALUE\t0x2040F\n++#define\tMC_CCR32_VALUE\t0x0\n++#define\tMC_CCR33_VALUE\t0x650000\n++#define\tMC_CCR34_VALUE\t0x200C8\n++#define\tMC_CCR35_VALUE\t0x1D445D\n++#define\tMC_CCR36_VALUE\t0xC8\n++#define\tMC_CCR37_VALUE\t0xC351\n++#define\tMC_CCR38_VALUE\t0x0\n++#define\tMC_CCR39_VALUE\t0x141F04\n++#define\tMC_CCR40_VALUE\t0x142704\n++#define\tMC_CCR41_VALUE\t0x141B42\n++#define\tMC_CCR42_VALUE\t0x141B42\n++#define\tMC_CCR43_VALUE\t0x566504\n++#define\tMC_CCR44_VALUE\t0x566504\n++#define\tMC_CCR45_VALUE\t0x565F17\n++#define\tMC_CCR46_VALUE\t0x565F17\n++#define\tMC_CCR47_VALUE\t0x2040F\n++#define\tMC_CCR48_VALUE\t0x0\n++#define\tMC_CCR49_VALUE\t0x0\n++#define\tMC_CCR50_VALUE\t0x0\n++#define\tMC_CCR51_VALUE\t0x0\n++#define\tMC_CCR52_VALUE\t0x133\n++#define\tMC_CCR53_VALUE\t0xF3014B27\n++#define\tMC_CCR54_VALUE\t0xF3014B27\n++#define\tMC_CCR55_VALUE\t0xF3014B27\n++#define\tMC_CCR56_VALUE\t0xF3014B27\n++#define\tMC_CCR57_VALUE\t0x7800301\n++#define\tMC_CCR58_VALUE\t0x7800301\n++#define\tMC_CCR59_VALUE\t0x7800301\n++#define\tMC_CCR60_VALUE\t0x7800301\n++#define\tMC_CCR61_VALUE\t0x4\n+--- /dev/null\n++++ b/board/arcadyan/vgv7519/vgv7519.c\n+@@ -0,0 +1,95 @@\n++/*\n++ * This file is released under the terms of GPL v2 and any later version.\n++ * See the file COPYING in the root directory of the source tree for details.\n++ *\n++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n++ */\n++\n++#include <common.h>\n++#include <asm/gpio.h>\n++#include <asm/lantiq/eth.h>\n++#include <asm/lantiq/chipid.h>\n++#include <asm/lantiq/cpu.h>\n++#include <asm/arch/gphy.h>\n++\n++#if defined(CONFIG_SYS_BOOT_RAM)\n++#define do_gpio_init\t1\n++#define do_pll_init\t0\n++#define do_dcdc_init\t1\n++#elif defined(CONFIG_SYS_BOOT_NOR)\n++#define do_gpio_init\t1\n++#define do_pll_init\t1\n++#define do_dcdc_init\t1\n++#else\n++#define do_gpio_init\t0\n++#define do_pll_init\t0\n++#define do_dcdc_init\t1\n++#endif\n++\n++#define GPIO_GPHY_RESET\t47\n++\n++static void gpio_init(void)\n++{\n++\t/* Disable reset on external eth PHY */\n++\tgpio_direction_output(GPIO_GPHY_RESET, 1);\n++}\n++\n++int board_early_init_f(void)\n++{\n++\tif (do_gpio_init)\n++\t\tgpio_init();\n++\n++\tif (do_pll_init)\n++\t\tltq_pll_init();\n++\n++\tif (do_dcdc_init)\n++\t\tltq_dcdc_init(0x7F);\n++\n++\treturn 0;\n++}\n++\n++int checkboard(void)\n++{\n++\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n++\tltq_chip_print_info();\n++\n++\treturn 0;\n++}\n++\n++static const struct ltq_eth_port_config eth_port_config[] = {\n++\t/* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */\n++\t{ 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n++\t/* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */\n++\t{ 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n++\t/* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */\n++\t{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n++\t/* GMAC3: unused */\n++\t{ 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },\n++\t/* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */\n++\t{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n++\t/* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */\n++\t{ 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n++};\n++\n++static const struct ltq_eth_board_config eth_board_config = {\n++\t.ports = eth_port_config,\n++\t.num_ports = ARRAY_SIZE(eth_port_config),\n++};\n++\n++int board_eth_init(bd_t * bis)\n++{\n++\tconst enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;\n++\tconst ulong fw_addr = 0x80FF0000;\n++\n++\tif (ltq_chip_version_get() == 1)\n++\t\tltq_gphy_phy22f_a1x_load(fw_addr);\n++\telse\n++\t\tltq_gphy_phy22f_a2x_load(fw_addr);\n++\n++\tltq_cgu_gphy_clk_src(clk);\n++\n++\tltq_rcu_gphy_boot(0, fw_addr);\n++\tltq_rcu_gphy_boot(1, fw_addr);\n++\n++\treturn ltq_eth_initialize(ð_board_config);\n++}\n+--- a/boards.cfg\n++++ b/boards.cfg\n+@@ -537,6 +537,9 @@ Active mips mips32 incai\n+ Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+ Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+ Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n++Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_brn vgv7519:SYS_BOOT_BRN Mathias Kresin <dev@kresin.me>\n++Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_nor vgv7519:SYS_BOOT_NOR Eddi De Pieri <eddi@depieri.net>\n++Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_ram vgv7519:SYS_BOOT_RAM Eddi De Pieri <eddi@depieri.net>\n+ Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+ Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+ Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+--- /dev/null\n++++ b/include/configs/vgv7519.h\n+@@ -0,0 +1,62 @@\n++/*\n++ * This file is released under the terms of GPL v2 and any later version.\n++ * See the file COPYING in the root directory of the source tree for details.\n++ *\n++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n++ */\n++\n++#ifndef __CONFIG_H\n++#define __CONFIG_H\n++\n++#define CONFIG_MACH_TYPE\t\"VGV7519\"\n++#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n++#define CONFIG_BOARD_NAME\t\"Arcadyan VGV7519\"\n++\n++/* Configure SoC */\n++#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n++\n++#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n++\n++#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n++\n++#define CONFIG_SYS_MAX_FLASH_BANKS\t2\t/* max number of memory banks */\n++#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH2_BASE }\n++\n++/* Environment */\n++#if defined(CONFIG_SYS_BOOT_BRN)\n++#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n++#define CONFIG_SKIP_LOWLEVEL_INIT\n++#define CONFIG_SYS_DISABLE_CACHE\n++#define CONFIG_ENV_IS_NOWHERE\n++#define CONFIG_ENV_OVERWRITE\t\t1\n++#elif defined(CONFIG_SYS_BOOT_NOR)\n++#define CONFIG_ENV_IS_IN_FLASH\n++#define CONFIG_ENV_OVERWRITE\n++#define CONFIG_ENV_OFFSET\t\t(384 * 1024)\n++#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n++#else\n++#define CONFIG_ENV_IS_NOWHERE\n++#endif\n++\n++#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n++\n++#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n++\n++/* Console */\n++#define CONFIG_LTQ_ADVANCED_CONSOLE\n++#define CONFIG_BAUDRATE\t\t\t115200\n++#define CONFIG_CONSOLE_ASC\t\t1\n++#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n++\n++/* Pull in default board configs for Lantiq XWAY VRX200 */\n++#include <asm/lantiq/config.h>\n++#include <asm/arch/config.h>\n++\n++/* Pull in default OpenWrt configs for Lantiq SoC */\n++#include \"openwrt-lantiq-common.h\"\n++\n++#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n++\tCONFIG_ENV_LANTIQ_DEFAULTS \\\n++\t\"kernel_addr=0xB0080000\\0\"\n++\n++#endif /* __CONFIG_H */\n", "prefixes": [ "LEDE-DEV", "9/9" ] }